Analog & Digital VLSI Design Practice Questions

Analog Design Assignment

Analog & Digital VLSI Design EEE C443

August 26
th
, 2014

Abstract
Please read through this entire document carefully before embarking on your assignment or asking any
queries.
Introduction
For this assignment, you are required to design a simple operational amplifier. You will be given a few
classes of circuits along with the specifications. You are required to meet all the given specifications.
You need to make the choice and then decide numerical values for each of the system specs that will be
enumerated for you. For this job, you might need to refer to journals and other publications. The library
IEEE site is a good place to start. The Internet is of course an excellent place to scrounge around for
information.
In real life, the specifications would be provided to you by a "customer". As a designer your job is to meet
those specifications. The ability to look at system specifications and translate them to specs for individual
building blocks is an important aspect of design. This assignment will help you get a feel for this.
Assignment Requirement
The instructions given here will need to be followed by all students. Please note that failure to do the
same will result in a penalty of marks. You have to work on this assignment in groups of three only. Each
group is required to submit one copy of the assignment report,
You have to use Cadence Schematic editor to draw your circuit.
For simulation you have to use Spectre simulators.
Your design should meet all the specifications, at Schematic level.
If you are not able to meet your specs, you can go ahead, but you need to explain why it has
happened at the time of demonstration and in report.
You are advised to use the g
m
/I
D
method for meeting gain requirements, while simultaneously
using the OCTC method for meeting bandwidth requirements.
Validate your design for all process corners and temperatures 0, 27 and 100 C.
Library for circuit simulation; is located at /linuxeda/dk/tsmc018/models/fp1/spectre/log018.scs
with Sections TT_3V, FF_3V, SS_3V
Use Model names pch3 for PMOS and nch3 for NMOS, unless otherwise specified. Connect the
body of PMOS to Vdd and NMOS to Ground.
Min. channel length that can be used is 0.35um.
Current sink means that one of the nodes is connected to ground and current source means that
one of the nodes is connected to the supply.
Your Design Should have only one ideal current Source/Sink .
The suggested topologies are to be used unless there is a valid reason not to do the same.
Make sure that all the transistors are working in saturation region.
OTA stands for Operational Transconductance Amplifier, which is basically an OPAMP with
high output resistance.
All OPAMPs/OTAs used feedback must be compensated for a phase margin of about 50 to 60,
unless your application requires it to be some other value.
Discussing with your friends is highly encouraged (but not copying). Plagiarism will be
penalized.
There will be no deadline extensions or other considerations based on server or software issues.
You are being given ample time and it is expected that you partition your work well into that time
and not just turn up in the O-Lab on the last couple of days to complete the same.
Suggested Design Procedure
Based on the specification given, you will need to decide which OPAMP architecture will help you meet
the specs most easily. For example, if a large bandwidth is required it might be inadvisable to use a two-
stage OPAMP since the compensation capacitance reduces the bandwidth heavily. At the same time
trying to use a large bandwidth OPAMP architecture when a moderate or small bandwidth is required is
considered overkill and will result in penalization in terms of marks.
Specifications
There will be some common specifications which all of the assignment have to meet or follow.

Parameters Specifications
Technology TSMC 180nm technology*
V
DD
3.3
C
L
500fF
Current mirror ratios 20
Reference Current Single ideal current source of arbitrary value, with the positive
node tied to V
DD
or negative node tied to ground
Power Dissipation 3mW unless stated
* Although the technology is 180nm, you are to use the 350nm transistors which are in the design kit for
analog design. The 180nm transistors specifically refer to the digital transistors and will not be able to
sustain the power supply of 3.3V. You will be given a zero in your assignment if you fail to follow this
particular directive.

Ques 1. Design a Two Stage Single-ended output CMOS OPAMP with a -3dB bandwidth of 1KHz, a phase
margin of 60
0
, a gain of 100000 V/V.
(a) Analog schematic for OPAMP (choose appropriate OPAMP).
(b) Analysis of all equations for OPAMP, with a systematic derivation of all transistors W/L ratios.
(Do not use hit-an-trial method)
(c) Use STB Analysis to find the closed loop gain and phase margin for your OPAMP.
(d) Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain and
phase, CMRR plot, ICMR plot, PSRR plot, slew rate, settling time, output voltage swing (dc +
Transient), power consumption, and input and output offset voltage.

Ques 2. Design a two stage single-ended output CMOS OPAMP with a UGB of 100MHz, a phase margin
of 60
0
, a gain of 15000 V/V.

Ques 3. Design a two stage single-ended output CMOS OPAMP having PSRR and CMRR 120dB.

Ques 4. Design a two stage single-ended output CMOS OPAMP having slew rate greater than 20 V/us,
settling time less than 1us, a phase margin of 60
0
and a gain of 5000 V/V.

Ques 5. Design a two stage single-ended output CMOS OPAMP having power dissipation 0.1mW and a
gain of 1500V/V.

Ques 6. Design a CMOS OPAMP.

a) Analog schematic for the above model
b) Analysis of all equations of your design, with a systematic derivative of all transistors W/L ratios
and spectre simulation of circuit for the following specifications.
i) UGB 400 MHz
ii) Phase margin 60
0

iii) Slew rate 50 V/s
c) Use STB Analysis to find the closed loop gain and phase margin for your OPAMP.
d) Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain and


i) DC Gain 120 dB
ii) Phase margin 60
0

iii) Power dissipation 2mW


i) CMRR 140 dB
ii) PSRR 120dB
iii) Output Swing 1.6V


i) 3dB Frequency 100 KHz
ii) Phase margin 60
0

iii) Output swing 2V

Ques 10. Design a telescopic OPAMP given in figure 9.8(a) of Razavi: (Iss should be designed using a
transistor)
a) Analysis of all equations of your design, with a systematic derivative of all transistors W/L ratios
i) -3dB Bandwidth 10 KHz
ii) Slew rate 50 V/s
iii) Output offset voltage 40mV
b) Use STB Analysis to find the closed loop gain and phase margin for your OPAMP.
c) Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain and
phase, CMRR plot, ICMR plot, PSRR plot, slew rate, settling time, Output voltage swing (dc +

Ques 11. Design a Single-ended output Folded Cascode OTA.
a) Analog schematic for OTA
b) Analysis of all equations for OTA, with a systematic derivative of all transistors W/L ratios and
spectre simulation of circuit for the following specifications.
i) DC Gain 120 dB
ii) Phase margin 55
0

c) Show a biasing circuitry to bias all the voltages in your design (except the input).
d) Use STB analysis to measure the closed loop gain and phase margin.
e) Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain and
phase, CMRR plot, ICMR plot, PSRR plot, slew rate, Output voltage swing (dc + Transient), power
consumption, and input and output offset voltage.

Ques 12. Design a Single-ended output Folded Cascode [Differential amplifier + common gate stage]
OTA. Use PMOS as the input transistor.
i) ICMR 1.8 V
ii) CMRR 120dB
iii) output Swing 2V

Ques 13. Design a two stage single-ended output OPAMP (Differential + gain stage) for the following
specification
i) DC gain 100 dB
ii) Output voltage swing 1.5V
iii) ICMR 1.5V
iv) Slew rate 100V/s
v) Settling time 50ns
b) Show a biasing circuitry to bias all the voltages in your design (except the input).
c) STB analysis to calculate the closed loop gain and phase margin for the OPAMP.
transient), power consumption, and input and output offset voltage.
.
Ques 14. Design a two stage single-ended output CMOS OPAMP with a UGB of 500KHz, a phase margin
of 60
0
, a gain of 120dB.

transistor)
i) Open loop gain (DC gain) 80 dB
ii) CMRR 100 dB
iii) power dissipation 1mW
phase, CMRR plot, ICMR plot, PSRR plot, slew rate, Settling time, Output voltage swing (dc +

transistor)
i) Open loop gain (DC gain) 80 dB
ii) Settling time 20 us
iii) power dissipation 0.5mW
phase, CMRR plot, ICMR plot, PSRR plot, slew rate, Settling time, Output voltage swing (dc +

transistor)
i) PSSR 100 dB
ii) DC Gain (open loop) 100dB
iii) Power Dissipation 1mW

transistor)
i) UGB 100 MHz
ii) Output swing 1.5 V

Ques 19. Design a two stage single-ended output OPAMP (Telescopic + gain stage) for the following
specification
a) Analysis of all equations of your design, with a systematic derivative of all transistors W/L
ratios and spectre simulation of circuit for the following specifications.
i) -3dB Frequency 100 KHz
ii) Phase margin 60
0

iii) ICMR 0.9V to 2.2V
c) Use STB analysis to measure the closed loop gain and phase margin.

specification
i) Gain 90 dB
ii) UGB 100 MHz
iii) Phase margin 60
0


specification
i) Gain 120 dB
ii) Phase margin 60
0

iii) Output swing 1.5V

specification
i) Gain 80 dB
ii) power dissipation .2mW

specification
i) Gain 100 dB
ii) PSRR 120 dB
iii) Output swing 1.5V

specification
i) CMRR 150 dB
ii) PSRR 150 dB

Ques 25. Design a two stage single-ended output OPAMP (Folded Cascode[Differential amplifier +
common gate stage] + gain stage) for the following specification
i) Gain 90 dB
ii) UGB 100 MHz
0


i) Gain 120 dB
ii) Phase margin 60
0


i) Gain 80 dB
ii) power dissipation .2mW

Ques 28. Design a two-stage CMOS OPAMP as shown in figure;
a) Analysis of all equations of your design, with a systematic
derivative of all transistors W/L ratios and spectre
simulation of circuit for the following specifications.
i) Open loop gain(DC gain) 90 dB
ii) UGB 200 MHz
0

iv) Differential Output Swing 4.5V
b) Show a biasing circuitry to bias all the voltages in your
design (except the input).
c) Calculate and plot the following parameters for your
OPAMP: DC gain, Bode plot for AC gain and phase, ICMR plot, slew rate, Differential Output
voltage swing (dc + Transient), power consumption, and input and output offset voltage.

Ques 29. Design a two-stage CMOS OPAMP as shown in figure;
a) Analysis of all equations of your design, with a
systematic derivative of all transistors W/L ratios and
spectre simulation of circuit for the following
specifications.
ii) Phase margin 60
0

iii) power dissipation 1mW
c) Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain
and phase, ICMR plot, slew rate, Differential Output voltage swing (dc + Transient), power

OTA.
i) DC Gain 100 dB
ii) UGB 200 MHz
0

iv) Slew rate 100 V/s

OTA.
i) CMRR 120dB
ii) PSRR 120dB

OTA.
i) DC Gain 80 dB
ii) UGB 600 MHz
0


Ques 33. Design a wide Swing Folded-Cascode CMOS OTA as shown in figure;
ii) UGB 200 MHz
0

iv) ICMR 2 V
b) Show a biasing circuitry to bias all the
voltages in your design (except the input).
c) Use STB analysis to measure the closed loop
gain and phase margin.
d) Calculate and plot the following parameters
for your OPAMP: DC gain, Bode plot for AC
gain and phase, CMRR plot, ICMR plot, PSRR
plot, slew rate, settling time, Output voltage swing (dc + Transient), power consumption, and
input and output offset voltage.

systematic derivative of all transistors W/L ratios
and spectre simulation of circuit for the following
specifications.
ii) UGB 100 MHz
0

iv) CMRR 150dB
b) Show a biasing circuitry to bias all the voltages
in your design (except the input).
d) Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain
and phase, CMRR plot, ICMR plot, PSRR plot, slew rate, settling time, Output voltage swing (dc
+ Transient), power consumption, and input and output offset voltage.

specifications.
ii) Phase margin 60
0

iii) output swing 1.4V
iv) power consumption 700 W
b) Show a biasing circuitry to bias all the voltages in
your design (except the input).
c) Use STB analysis to measure the closed loop gain
and phase margin.

Ques 36. Design a wide Swing Folded-Cascode CMOS OTA
as shown in figure below;
specifications.
ii) Phase margin 55
0

iii) PSRR 120 dB
iv) ICMR 150dB

Ques 37. Design a wide Swing Folded-Cascode CMOS OTA as shown in figure below;
specifications.
ii) slew rate 100V/s
iii) settling time 50ns
iv) Phase margin 60
0

v) ICMR 2.2 V

specifications.
ii) UGB 100MHz
iii) slew rate 50V/s
iv) Phase margin 60
0

v) settling time 10ns

specifications.
ii) Power Dissipation 1mW
0

iv) Output Offset 100mV
b) Show a biasing circuitry to bias all the voltages
in your design (except the input).
+ Transient), power consumption, and input and output offset voltage
Ques 40. Design a two stage single-ended output OPAMP(differential +gain stage) for the following
specification
i) DC gain 80 dB
ii) UGB 400MHz
iii) Output voltage swing 2V
iv) PSRR 120dB
v) Output offset voltage 40mV

Ques 41. Design a two stage single-ended output OPAMP (Differential + gain stage) for the following
specification
i) DC gain 110 dB
ii) Power dissipation 0.5mW
iii) Settling time 60ns

Ques 42. Design a two stage single-ended output OPAMP (Differential stage + a cascode second stage)
for the following specification.
i) DC gain 120 dB
ii) Output voltage swing 1.5V

for the following specification
i) DC gain 90 dB
ii) UGB 300MHz

i) CMRR 150 dB
ii) PSRR 140 dB

i) -3dB Frequency 100 KHz
ii) Power Dissipation 1.5mW


i) Gain 100 dB
ii) Settling time 20ns
iii) UGB 200 MHz
iv) Slew rate 20 V/s

Ques 47. Design a two-stage single-ended output CMOS OPAMP with a UGB of 600MHz and a phase
margin of 60
0
.
(c) What is the closed loop gain and phase margin for your OPAMP using STB analysis?

Ques 48. Design a Two stage single-ended output CMOS OPAMP with a -3dB bandwidth of 5MHz.
(c) What is the settling time for your OPAMP?
(d) What is the closed loop gain and phase margin for your OPAMP using STB analysis?
(e) Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain and

Ques 49. Design a fully differential two stage OPAMP (Differential + gain stage) for the following
specification
i) DC gain 100 dB
ii) Differential Output voltage swing 3.5V
phase, ICMR plot, slew rate, Differential Output voltage swing (dc + Transient), power

Ques 50. Design a fully differential two stage OPAMP (Differential + gain stage) for the following
specification
i) DC gain 80 dB
phase, ICMR plot, slew rate, Differential Output voltage swing (dc + Transient), power

Ques 51. Design a folded Cascode OPAMP as shown in figure;
specifications.
ii) UGB 100 MHz
0

phase, ICMR plot, slew rate, Output voltage swing differential (dc + Transient), power

specifications.
i) UGB 300 MHz

specifications.
i) DC gain 120dB
ii) Differential Voltage Swing 4V
iii) ICMR 2.2V
phase, ICMR plot, slew rate, Output voltage swing differential (dc + Transient), power consumption,
and input and output offset voltage.

specifications.
ii) 3dB Frequency 10 KHz
0

OPAMP: DC gain, Bode plot for AC gain and phase, ICMR
plot, slew rate, Output voltage swing differential (dc + Transient), power consumption, and input
and output offset voltage.

specifications.
i) DC Gain 100dB
ii) Differential Voltage Swing 3V
iii) 3dB Frequency 1 KHz
c) Calculate and plot the following parameters for
your OPAMP: DC gain, Bode plot for AC gain and phase, ICMR plot, slew rate, Output voltage swing
differential (dc + Transient), power consumption, and input and output offset voltage.

specifications.
i) Differential Voltage Swing 4V
ii) ICMR 2.2V
iii) power dissipation .1mW
c) Calculate and plot the following parameters for
your OPAMP: DC gain, Bode plot for AC gain and
phase, ICMR plot, Slew rate, Output voltage swing differential (dc + Transient), power consumption,


i) DC Gain 90dB
ii) Power dissipation .5mW
OPAMP: DC gain, Bode plot for AC gain and phase, ICMR plot, Slew rate, Output voltage swing

d) Analysis of all equations of your design, with a
specifications.
iii) DC Gain 80dB
iv) Power Dissipation 0.4mW
e) Show a biasing circuitry to bias all the voltages in your
f) Calculate and plot the following parameters for your
OPAMP: DC gain, Bode plot for AC gain and phase, ICMR plot, slew rate, Output voltage swing

Ques 59. Design a telescopic OPAMP as shown in figure;
ii) UGB 200 MHz
iii) Differential Output voltage swing 4V
c) Also calculate the following parameters for your OPAMP: Bode plot for AC gain and phase
margin, slew rate, ICMR, Differential Output Swing (dc + Transient), Offset voltage and power
consumption.

specifications.
ii) power dissipation 0.1 mW
c) Also calculate the following parameters for your OPAMP: Bode plot for AC gain and phase
margin, slew rate, ICMR, Differential output swing (dc + Transient), input offset voltage and
power consumption.

c) Also calculate the following parameters for your OPAMP:
Bode plot for AC gain and phase margin, slew rate, ICMR,
Differential output swing (dc + Transient), input offset
voltage and power consumption.

Ques 62. To achieve high swing in telescopic OPAMP a student removed the tail current source but at
cost of common-mode rejection and power-supply rejection.
a) Design a high swing telescopic OPAMP.
ii) Output voltage swing 4V

Ques 63. To achieve high swing in telescopic OPAMP a student removed the tail current source but at
cost of common-mode rejection and power-supply rejection.
a) Design a high swing telescopic OPAMP.
ii) UGB 400 MHz
iii) Output voltage swing 4V

Ques 64. Design a two-stage fully-differential OPAMP (Telescopic + gain stage) for the following
specification
i) DC gain 100 dB
ii) Output voltage swing 4V
iii) -3 dB frequency 5 KHz

specification
i) UGB 600 MHz
ii) Phase margin 60
0

iii) Settling time 20ns

specification
i) Gain 90 dB
ii) UGB 100 MHz
0
iv) Differential output Swing 3.5 V

Ques 67. Design a two-stage Fully-Differential OTA (Folded Cascode [Differential amplifier + common
gate stage] + gain stage).
a) Analog schematic for OTA.
i) UGB 400 MHz
ii) Phase margin 55
0
- 65
0

iii) Output voltage swing differential 3V
c) Show the biasing circuitry to bias all the voltages in your design (except the input).
phase, ICMR plot, slew rate, Differential Output Swing (dc + Transient), power consumption,

Que68. Design a two-stage Fully-Differential OTA (Folded Cascode[Differential amplifier + common gate
stage] + gain stage).
i) Gain 80 dB
ii) Phase margin 60
0

iii) Power dissipation 0.5mA

Ques 69. Design a two-stage Fully-Differential OTA (Folded Cascode[Differential amplifier + common
gate stage] + gain stage).
i) DC Gain (Open Loop) 100 dB
ii) UGB 100MHz
0
- 65
0


Ques 70. Design a two-stage Fully-Differential OTA (Folded Cascode[Differential amplifier + common
gate stage] + gain stage) for the following specifications;
i) DC gain (Open Loop) 120 dB
ii) Differential Output swing 2.5V

Common Simulations

The following simulations need to be done for all classes of circuits:

1. Performance Evaluation at:

VDD+10%, FF Corner, Minimum Resistance Corner, 0
0
C
VDD-10%, SS Corner, Maximum Resistance Corner, 100
0
C

Submission Dates

Assignment Submission Before 10
th
September, 2013
Evaluation of the Assignment 12
th
October, 2013

NOTE: Report submission will be at the time of evaluation.

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Analog Design Assignment

Analog & Digital VLSI Design EEE C443

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