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    EEE4134 CO Spring2021

    Uploaded by

    Abdullah Al Sakib
    This document outlines a course on VLSI-I Lab. The course is a 1.5 credit elective offered in the 4th year, 1st semester of the Electrical and Electronic Engineering program. The lab experiments are based on concepts from the VLSI-I theory course and involve designing simple systems using MOSFETs in Cadence Virtuoso and writing Verilog code in Quartus II. Assessment includes class performance, three lab exams, and a final project. Students will construct IC schematics and layouts, measure design parameters, and implement combinational and sequential logic circuits in Verilog.

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    EEE4134 CO Spring2021

    Uploaded by

    Abdullah Al Sakib
    114 views4 pages
    This document outlines a course on VLSI-I Lab. The course is a 1.5 credit elective offered in the 4th year, 1st semester of the Electrical and Electronic Engineering program. The lab experiments are based on concepts from the VLSI-I theory course and involve designing simple systems using MOSFETs in Cadence Virtuoso and writing Verilog code in Quartus II. Assessment includes class performance, three lab exams, and a final project. Students will construct IC schematics and layouts, measure design parameters, and implement combinational and sequential logic circuits in Verilog.

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    EEE4134_CO_Spring2021

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    This document outlines a course on VLSI-I Lab. The course is a 1.5 credit elective offered in the 4th year, 1st semester of the Electrical and Electronic Engineering program. The lab experiments are based on concepts from the VLSI-I theory course and involve designing simple systems using MOSFETs in Cadence Virtuoso and writing Verilog code in Quartus II. Assessment includes class performance, three lab exams, and a final project. Students will construct IC schematics and layouts, measure design parameters, and implement combinational and sequential logic circuits in Verilog.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    114 views4 pages

    EEE4134 CO Spring2021

    Uploaded by

    Abdullah Al Sakib
    This document outlines a course on VLSI-I Lab. The course is a 1.5 credit elective offered in the 4th year, 1st semester of the Electrical and Electronic Engineering program. The lab experiments are based on concepts from the VLSI-I theory course and involve designing simple systems using MOSFETs in Cadence Virtuoso and writing Verilog code in Quartus II. Assessment includes class performance, three lab exams, and a final project. Students will construct IC schematics and layouts, measure design parameters, and implement combinational and sequential logic circuits in Verilog.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 4

    Ahsanullah University of Science and Technology (AUST)

    Bangladesh

    COURSE OUTLINE

    1. Title: VLSI-I Lab.

    2. Code: EEE 4134

    3. Credit hours: 1.5

    4. Level: Year 4, Semester 1

    5. Faculty: Engineering

    6. Department: Electrical and Electronic Engineering (EEE)

    7. Programme: B.Sc. in Electrical and Electronic Engineering

    8. Synopsis:
    Laboratory experiments based on theory and concepts learnt in EEE 4133. Design of simple
    systems using the principles learned in EEE 4133.

    9. Type of course (core/elective): Elective

    10. Prerequisite(s) (if any): N/A

    11. Name of the instructor(s) with contact details and office hours:

    Name Contact Office Hour


    Ms. Shourin Rahman Aura +8801677036086 TBA
    [email protected]
    Mr. S. M. Ishraqul Huq +8801796584370 TBA
    [email protected]
    Ms. Oli Lowna Baroi +8801722601843 TBA
    [email protected]
    Mr. Sk. Aqiluzzaman Shihab +8801680058577 TBA
    [email protected]
    Mr. Adnan Amin Siddique TBA
    N2
    N3

    12. Semester Offered: Spring 2021

    Page 1 of 4
    13. Mapping of Course Outcomes (COs) with Program Outcomes (POs) and Bloom’s
    Taxonomy Level

    By the end of this course, students are expected to:

    Sl. Bloom’s
    No. COs POs Taxonomy
    C A P
    1 Construct schematic and layout of integrated circuits (ICs) 5 5
    made of MOSFETs using Cadence Virtuoso tool.
    2 Measure the performance of a designed IC based on the 2 4
    effects of different parameters.
    3 Build Verilog code for a given problem in digital circuit 3 3
    design using Quartus II software.

    14. Mapping of COs with Knowledge Profiles, Ranges of Complex Engineering


    Problem Solving and Ranges of Complex Engineering Activities

    Course Outcome Knowledge Profile Ranges of Ranges of


    Complex Problem Complex
    Solving Engineering
    Activity
    CO1 K6 P1-P7
    CO2 K3 P1-P7
    CO3 K5 P1-P7

    15. Percentages of Assessment Methods

    Method Percentage
    Class Performance 20
    Lab Exam 1 20
    Lab Exam 2 20
    Lab Exam 3 20
    Project 20

    16. Week wise distribution of contents and assessment methods

    Week Topics Assessment Method(s)


    1 Lab 0 (Introductory Lab)
    Introduction to Custom IC Design flow; Logging into
    Cadence Server; Tool setup; Cell Library creation.

    Page 2 of 4
    2 Lab 1
    Introduction to Virtuoso Schematic Editor; Creating
    Class Performance
    Inverter schematic; Performing transient simulation
    of Inverter schematic.
    3 Lab1 (contd.)
    Average and Static Power; Rise-time, Fall-time and Class Performance
    Delay measurement of designed inverter.
    4 Lab 2
    Parametric analysis of DC simulation; Introduction to Class Performance
    Symbol Editor and symbol creation of Inverter.
    5 Schematic Implementation and Circuit Analysis. Exam 1
    6 Lab 3
    Introduction to Virtuoso Layout Editor L; Layout Class Performance
    drawing of an Inverter.
    7 Lab 4
    DRC and LVS verification; Parasitic extraction of an Class Performance
    Inverter.
    Mid-Break
    8 Lab 5
    Introduction to Virtuoso Layout Editor XL; Schematic Class Performance
    driven layout of a 2-input NAND gate and verification.
    9 Lab 6
    Introduction to Hierarchical Design (2-input AND gate
    using 2-input NAND gate and an Inverter). Class Performance

    Project selection deadline + project discussion.


    10 Schematic and Layout Design using Cadence
    Exam 2
    Virtuoso.
    11 Lab 7 and 8
    Introduction to Verilog HDL and Quartus II;
    Class Performance
    Combinational Logic circuit design in Verilog HDL
    using Quartus II; RTL synthesis.
    12 Lab 9
    Sequential Logic circuit design in Verilog HDL using Class Performance
    Quartus II.
    13 Verilog HDL using Quartus II Exam 3
    14 Project presentations. Project

    Page 3 of 4
    17. References

    17.1. Required (if any):


    1. EEE-4134 Lab Manual, Dept. of EEE, AUST.

    17.2. Recommended (if any):

    1. N. H. E. Weste and D. M. Harris, CMOS VLSI design: a circuits and systems


    perspective. India: Pearson India, 2015.
    2. S. D. Brown and Z. G. Vranesic, Fundamentals of digital logic with Verilog
    design. New York: McGraw-Hill, 2014.
    3. K. Golshan, Physical design essentials: an ASIC design implementation perspective.
    New York: Springer, 2007.
    4. Erik Brunvand, Digital VLSI Chip Design with Cadence and Synopsys CAD tools, 1st
    edition, Pearson, 2009.

    Page 4 of 4

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