Power Electronic Converter Design Handbook

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Manex Barrenetxea Iñarra

Igor Baraia Zubiaurre
Igor Larrazabal Bengoetxea
Ignacio Zubimendi Azaceta
POWER ELECTRONIC CONVERTER
DESIGN HANDBOOK
Authors:
MANEX BARRENETXEA IÑARRA - Mondragon Unibertsitatea, Faculty of Engineering

IGOR BARAIA ZUBIAURRE - Mondragon Unibertsitatea, Faculty of Engineering
IGOR LARRAZABAL BENGOETXEA - Ingeteam Power Technology
IGNACIO ZUBIMENDI AZACETA - Ingeteam Power Technology
Edita: Mondragon Unibertsitateko Zerbitzu Editoriala
Loramendi kalea, 4 - (23 p.k.)
20500 ARRASATE-MONDRAGON (Gipuzkoa)
Diseño y maquetación: AZK Taldea

ISBN: 978-84-09-03771-1
Electronics and Computer Science Department
Mondragon Unibertsitatea
Abstract
Nowadays, power electronic converters play an essential role in the majority of consumer
electronic devices and are widely used in industrial applications. Since most of these
applications are supplied through the AC grid, the use of rectifiers and DC-DC conveters
are mandatory to adapt the grid voltage to the application requirements.
In this book, most used AC-DC rectifier topologies and DC-DC converter topologies are
thoroughly discussed. Basics of each converter, equations for the power losses evaluation
and passive elements design are described. Moreover, the medium frequency transformer
required by several of the studied DC-DC converters is analysed in depth.
Therefore, this book pretends to be a handbook with a wide scope, which could be used
for academic purposes or even by engineers.
Abbreviations
2L-VSC Two-level voltage source converter

3L-NPC Three-level neutral point clamped
AC Alternating-current
AFE Active front end
CCM Continuous current mode
CHB Cascaded H-bridge
DC Direct-current
DCM Discontinuous current mode
DFE Diode front end
EMI Electromagnetic interference
HB H-bridge
IGSE Improved generalized Steinmetz equation
LCC Line commutated converter
MFT Medium frequency transformer
NRF Notch resonance frequency
PRF Parallel resonance frequency
PWL Piecewise linear
PWM Pulse width modulation
SHE Selective harmonic elimination
SRF Series resonance frequency
SVM Space vector modulation
THD Total harmonic distortion
VSC Voltage source converter
Contents
1 AC-DC Rectifiers 3
1.1 Introduction ....................................................................................................... 13
1.2 Three-phase diode front end .............................................................................. 14

1.2.1 Power losses estimation ................................................................................ 14
1.2.2 DC bus capacitor design ................................................................................ 16
1.3 Two-level voltage source converter .................................................................. 17

1.3.1 Power losses estimation ................................................................................. 18
1.3.2 DC bus capacitor design ................................................................................23
1.4 Three-level neutral point clamped converter ..................................................... 23

1.5 Cascaded H-bridge converter ............................................................................ 36

1.6 Summary .......................................................................................................... 41
2 DC-DC converters
2.1 Introduction ....................................................................................................... 43
2.2 Switch mode DC-DC converters ....................................................................... 44

2.2.1 Boost ............................................................................................................. 45
2.2.2 Zeta ................................................................................................................ 50
2.2.3 Sepic .............................................................................................................. 56
2.2.4 Isolated-sepic ................................................................................................. 62
2.2.5 Ćuk ................................................................................................................ 68
2.2.6 Isolated-ćuk ................................................................................................... 73
2.2.7 Flyback .......................................................................................................... 79
2.2.8 Forward ......................................................................................................... 85

2.2.9 Two-transistor forward ................................................................................. 92
2.2.10 Push-pull ........................................................................................................99
2.2.11 Push-pull isolated-boost...............................................................................105
2.2.12 Half-bridge ..................................................................................................112
2.2.13 Half-bridge isolated-boost ...........................................................................117
2.2.14 Full-bridge ...................................................................................................124
2.2.15 Full-bridge isolated-boost ............................................................................133
2.2.16 Single-active-bridge .....................................................................................140
2.2.17 Dual-active-bridge .......................................................................................146
2.3 Resonant mode DC-DC converters.................................................................. 154

2.3.1 Series LC resonant-tank ...............................................................................156
2.3.2 Three-element resonant-tanks ......................................................................159
2.3.2.1 LLC..............................................................................................................159
2.3.2.2 LCC .............................................................................................................161
2.3.2.3 CLL..............................................................................................................162
2.3.2.4 LCL type 1 ...................................................................................................164
2.3.2.5 LCL type 2 ...................................................................................................166
2.3.3 Four-element resonant-tanks .......................................................................167
2.3.3.1 LCLL ...........................................................................................................167
2.3.3.2 LLCL ...........................................................................................................169
2.3.3.3 CLCL ...........................................................................................................171
2.3.4 CLCLL resonant-tank ..................................................................................173
2.4 Summary ....................................................................................................... 175
3 Medium frequency transformer 177
3.1 Introduction...................................................................................................... 177
3.2 Geometry of the transformer............................................................................ 178

3.2.1 Core .............................................................................................................178
3.2.2 Windings......................................................................................................181
3.2.3 Magnetizing and leakage inductances .........................................................184
3.3 Power losses estimation ................................................................................... 187

3.3.1 Core power losses ........................................................................................ 187
3.3.2 Winding power losses ................................................................................. 189
3.3.3 Thermal behaviour ...................................................................................... 191
3.4 Optimization procedure ................................................................................... 192
3.5 Summary ....................................................................................................... 194
4 References 195
Appendix A - Validation of switch mode DC-DC converter models ............................ I

Chapter 1
AC-DC Rectifiers
In this chapter, the main characteristics of various active and passive converter
topologies for AC to DC rectifying purposes are discussed. For each converter,
analytical expressions of semiconductor power losses are described and DC bus
capacitor design criteria are shown.
1.1 Introduction
The electrical devices used to convert an alternating-current (AC) to a direct-current (DC)

are known as rectifiers. So, the AC to DC conversion process is known as rectification.
Depending on the rectifier type and the input AC voltage, the output DC voltage can be
variable or not. Diode rectifiers make the output DC voltage to be input AC voltage
dependent, while active rectifiers maintain the output DC voltage constant.
In order to have a wide pool of choices to select the most suitable rectifier for a given
application, different converters that could be used as rectifiers must be analyzed. In this
chapter, the main characteristics of four different converters are detailed, their operation
is described and DC link capacitor design criterion is discussed. In addition, given that
the efficiency evaluation is mandatory in energy conversion applications, analytical
power loss models for each converter are presented.
13
Chapter 1. AC-DC Rectifiers
1.2 Three-phase diode front end
Fig 2.1 shows a three-phase diode front end (DFE) rectifier composed of a DC bus
capacitor (Cbus) and three legs with two diodes in each leg. As it is composed of diodes,
the power flow is unidirectional (from AC source to DC bus) and the bus voltage cannot
be controlled (it depends on the AC supply and the load). This rectifier is widely used in
industry due to its low manufacturing cost and high efficiency and reliability [1].
However, they generate current harmonics in the AC side, which are detrimental for
electrical generators.
ibus
+
D1 D3 D5
ia a
ib +
ic
b Cbus
-
Vbus
c
D4 D6 D2
-
Fig 2.1. Three-phase diode front end rectifier.
Under the assumption of a highly inductive AC side, the rectifier operates in a continuous
current mode (CCM) [2], [3] and the DC bus current (ibus) can be considered constant.
As shown in Fig 2.2, each diode conducts when it is forward-biased and two diodes are
always current conducting in the bridge. Assuming a highly inductive AC side, the
current ripple in the DC side can be neglected (cf. Fig 2.2). Thus, the current conducted
by all the diodes is considered equal to the DC side current Ibus. This DC side current
varies depending on the transferred power, i.e. the higher the power the higher is the
circulating current. Being conservative, the maximum DC bus voltage (vbus) is equal to
the line to line voltage and hence, the maximum reverse voltage of the diodes is given by
the peak line to line voltage (Vbus). The conducted current and reverse voltage of all
diodes are same and in consequence, it can be assumed that all diodes have same power
losses and thermal stress.
1.2.1 Power losses estimation
Assuming an ideal DC bus capacitor with no losses, the converter power losses are equal
to the diode power losses, which are given by average conduction power losses (Pcond)
and average switching power losses (Psw), Eq. (2.1).
Plosses = Pcond + Psw (2.1)
14
1.2. Three-phase diode front end
vbus
vab vac vbc vba vca vcb vab
Vbus
ibus t
Ibus
D6-D1 D1-D2 D2-D3 D3-D4 D4-D5 D5-D6 D6-D1
T t
Fig 2.2. Voltage and current waveforms in a three-phase diode rectifier.
Average conduction power losses are estimated from the diode forward characteristics
provided by the manufacturer (cf. Fig 2.3a). In order to simplify the final expression, the
real voltage-vs-current curve (grey line) is approximated to a first order equation (black
line) as shown by Fig 2.3a. Thus, the voltage drop over the diode can be expressed by the
threshold voltage (Vth) and the characteristic on-state resistance (rd), see Eq. (2.2).
Therefore, the instantaneous power dissipated in the diode is given by Eq. (2.3) and in
consequence, if the instantaneous power losses are averaged in a fundamental period (T),
average conduction power losses are obtained as in Eq. (2.4).
vF (t ) Vth + iF (t ) ⋅ rd
= (2.2)
p cond (t ) =i F (t ) ⋅ v F (t ) =i F (t ) ⋅ Vth + i F 2 (t ) ⋅ rd (2.3)

Tcond
1
Pcond
= ⋅ (t ) dt
∫ pcond= rd ⋅ I rms 2 + Vth ⋅ I ave (2.4)
T 0
where iF, Irms and Iave are respectively forward, root-mean-square (rms) and average
currents through the diode, vF is the forward voltage drop over the diode, and, Tcond is the
diode conduction time interval.
From Fig 2.2, the rms current and the average current can be derived:
T
1 3 I bus (2.5)
I rms =⋅ ∫ I bus 2 dt =
T 0 3
T
1 3 I bus
(2.6)
T ∫0
I ave =⋅ I bus dt =
3
When a diode is suddenly reverse biased (with high di/dt), the carriers must be recovered
before it starts acting as a blocking device. Average switching power losses (Psw) are due
to this phenomenon. In order to estimate these losses (Erec), the manufacturer provides the
dissipated energy (cf. Fig 2.3b) at the 100FIT test voltage (V100FIT). This curve can be
modelled with a second order equation as Eq. (2.7). The dissipated energy must be
15
normalized to the switched voltage (vsw), Eq. (2.8). Average switching power losses are
equal to the summation of the switching energy losses over a fundamental period (T), Eq.
(2.9).
E rec = Aoff ⋅ i F 2 + Boff ⋅ i F + C off (2.7)
E rec =
v sw
V100 FIT
(
⋅ Aoff ⋅ i F 2 + Boff ⋅ i F + C off ) (2.8)
1 v ( n)
( )
N
Psw = ⋅ ∑ sw ⋅ Aoff ⋅ iF (n) 2 + Boff ⋅ iF (n) + Coff (2.9)
N ⋅ T n =1 V100 FIT
where Aoff, Boff and Coff are the energy loss characteristic coefficients.
iF Erec
real
1
rd
approach
Vth vF iF
a) b)
Fig 2.3. Typical diode characteristics. a) Diode forward characteristic. b) Dissipated
energy vs forward current.
However, as a highly inductive AC side has been assumed, the di/dt of the current
through the diodes is small. Thus, the carriers to be recovered are few and in
consequence, average switching power losses can be neglected. Therefore, Eq. (2.10)
gives the efficiency of the three-phase diode rectifier.
η =1−
(
2 ⋅ Vth ⋅ I bus + rd ⋅ I bus 2 ) (2.10)
Pin
1.2.2 DC bus capacitor design
When the AC side voltage is lower than the capacitor voltage, the DC bus capacitor must
supply the load power guaranteeing a given voltage ripple. To do so, Cbus must store a
certain amount of energy.
The maximum DC bus voltage is provided by the line to line voltage (VLL,rms):
Vbus ,max = 2 ⋅ VLL,rms (2.11)

The energies stored by the capacitor when it is charged with the maximum bus voltage
and with the minimum bus voltage are given respectively by:
2
1  ∆v 
E C max = ⋅ C bus ⋅ Vbus +  (2.12)
2  2 
16
1.3. Two-level voltage source converter
2
1  ∆v 
E C min = ⋅ C bus ⋅ Vbus −  (2.13)
2  2 
where Δv is the voltage ripple.

Considering a ΔT time interval in which the Cbus capacitor is being discharged, the power
provided by the capacitor can be expressed as:
E C max − E C min
P= (2.14)
∆T
If the transient power variation (P) is limited to the 10% of the rated power, the required
DC bus capacitance is calculated introducing Eq. (2.12) and Eq. (2.13) into Eq. (2.14).
2 ⋅ P ⋅ ∆T 3 ⋅ Vmax ⋅ I max ⋅ ∆T
Cbus = 2 2
=
 ∆v   ∆v  20 ⋅ Vbus ⋅ ∆v (2.15)
Vbus +  − Vbus − 
 2   2 
where Vmax and Imax are the peak phase voltage and current.
1.3 Two-level voltage source converter
The two-level voltage source converter (2L-VSC) is composed of a DC bus capacitor

(Cbus) and three legs with two transistors and their respective freewheel diodes in each leg
(cf. Fig 2.4). All the semiconductors have to withstand the DC bus voltage during the off-
state. The low component number makes this converter simple, cost effective and reliable
[4]. In consequence, it is one of the most popular converters in conventional wind
turbines [1], [4]. Space vector modulation (SVM) and pulse width modulation (PWM) are
two of the most used modulation techniques in this converter [5]. In this book, the
analytical expressions for power losses estimation are obtained under the assumption that
a PWM technique is used. The accuracy of obtained analytical expressions is pretty
acceptable [6-7].
ibus
+
D1 D3
S1 S3 S5 D5
ia a
ib b +
Cbus
-
Vbus
ic c
D4 D6
S4 S6 S2 D2
-
N
Fig 2.4. Two-level voltage source converter.
17
In Fig 2.5, typical voltage waveforms of a 2L-VSC operated with PWM are shown. vcr is
the triangular carrier and va*, vb* and vc* are the reference phase voltages to be
synthesized. The reference voltages are 120 degrees phase shifted each other. When the
reference voltage is higher than the triangular carrier, the upper transistor of that leg is
turned-on while the lower transistor is turned-off. Conversely, when the reference voltage
is lower than the triangular carrier, the upper transistor of that leg is turned-off and the
lower transistor is turned-on. Thus, two different voltage levels can be synthesized in
each phase [0, Vbus]. Line to line voltage is obtained by subtracting two-phase voltages as
shown in Fig 2.5. This resulting line to line voltage has three voltage levels.
v vcr va* vb* vc*
vaN S1 on - S4 off
S4 on - S1 off
Vbus
vbN t
S3 on - S6 off
S6 on - S3 off
Vbus
vab t
Vbus
t
vab1 T
Fig 2.5. Typical voltage waveforms of a two-level voltage source converter with a
PWM modulation strategy.
Generally speaking, main converter power losses come from conduction and switching
power losses of the semiconductors. In order to obtain simple analytical expressions for
power losses, the following is assumed:
• The phase current is a purely sinusoidal current.

• The converter operates under a PWM modulation strategy in the linear region
(overmodulation is not considered).
• The switching frequency is very high.
18
• The output characteristics and the switching energy losses characteristics

provided by the manufacturer are used to estimate conduction and switching
power losses.
1.3.1.1 Conduction power losses
Conduction power losses depend on the semiconductor output characteristic and the
average and rms values of the current flowing through it, see Eq. (2.4). Due to the
symmetrical structure of the converter, the circulating current expressions are equal for all
the transistors as well as for all the diodes. As it can be observed in Fig 2.6, a pulsating
current circulates through the transistor S1. Furthermore, considering a very high
switching frequency, this current can be considered constant (Ia).
v vcr va*
ia
iS1
Ia Ton
Tsw t
Fig 2.6. Current circulating through the transistor S1 assuming a very high switching
frequency.
Therefore, the average and rms current expressions in a switching period Tsw are given by:
Ton
I ave = I a ⋅ (2.16)
Tsw
Ton
I rms 2 = I a 2 ⋅ (2.17)
Tsw
where Ton is the conduction time interval.

The current circulating through the semiconductor during the conduction time interval is
the same as the phase current. As the amplitude of this sinusoidal current varies along the
fundamental period, the conduction power losses in a fundamental period can be
estimated by the summation of conduction power losses in each switching period:
19
1 N
Pcond = ⋅ ∑ rd ⋅ I rms (n )2 + Vth ⋅ I ave (n ) =
N n =1
(2.18)
1 N T T
= ⋅ ∑ rd ⋅ I a (n )2 ⋅ on (n ) + Vth ⋅ I a (n ) ⋅ on (n )
N n =1 Tsw Tsw
T
N= (2.19)
Tsw
where Vth is the threshold voltage in the semiconductor and rd is the characteristic on-state
resistance.
v va* vcr
ia
φ
t
vaN S1 on - S4 off
S4 on - S1 off
Vbus
iS1 t
iD4 Ton Ton t

Imax
t
T
Fig 2.7. Current and voltage waveforms of a two-level voltage source converter with a
In Eq. (2.18) the output characteristics of the semiconductors (rd, Vth) are constant. So, in
order to obtain an analytical conduction losses expression, the pulsating current
waveform is converted into a continuous current with similar average and rms current
values.
At each Ton conduction interval, the Ia current value of Eq. (2.16) and Eq. (2.17) has the
same amplitude as the phase current ia:
I a (n ) = ia (t ) = I max ⋅ sin (ωt ) (2.20)
where Imax is the maximum amplitude of the phase current.
If conduction time intervals are observed in Fig 2.7, it can be seen how Ton varies
proportionally to the reference voltage va* of Eq. (2.21). Thus, the lower va* the narrower
20
the Ton period. Therefore, Ton/Tsw can be expressed in function of the reference voltage. As
Ton/Tsw must be positive and its value contained within 0 and 1, the modulation function
can be defined by Eq. (2.22).
va * (t ) = m ⋅ sin (ωt + ϕ ) (2.21)
Ton
(t ) = 1 ⋅ (1 − m ⋅ sin (ωt + ϕ )) (2.22)
Tsw 2
where m is the modulation index and φ is the phase shift between va* and the phase
current ia.
Taking into account that the transistor S1 conducts only when the phase current is
negative (cf. Fig 2.4 and Fig 2.7), the average and rms currents through it in a
fundamental period can be approached to:
1 T 1
⋅ I max ⋅ sin (ωt ) ⋅ ⋅ (1 − m ⋅ sin (ωt + ϕ ))dt
T T∫
I ave = (2.23)
2
2
1 T 1
I rms 2 = ⋅ I max 2 ⋅ sin 2 (ωt ) ⋅ ⋅ (1 − m ⋅ sin (ωt + ϕ ))dt
T T∫ 2 (2.24)
2
As a consequence, average conduction power losses are obtained substituting Eq. (2.23)
and Eq. (2.24) in Eq. (2.18):
1 T 1
⋅ (rd ⋅ I max ⋅ sin (ωt ) + ⋅Vth ) ⋅ I max ⋅ sin (ωt ) ⋅ ⋅ (1 − m ⋅ sin (ωt + ϕ ))dt =
T T∫
Pcond _ S1 =
2
2
(2.25)
1 I I 2 I I 2
= ⋅ (Vth ⋅ max + rd ⋅ max ) − m ⋅ cos(ϕ ) ⋅ (Vth ⋅ max + rd ⋅ max )
2 π 4 8 3⋅π
Average conduction power losses of the diode D4 are calculated similarly. The only
difference is that it conducts when S1 is turned-off. Thus, its modulation function is given
by:
Toff (t ) Ton (t ) 1
= 1− = ⋅ (1 + m ⋅ sin (ωt + ϕ )) (2.26)
Tsw Tsw 2
Therefore, its conduction power losses are given as:
1 I I 2 I I 2
Pcond _ D 4 = ⋅ (Vth ⋅ max + rd ⋅ max ) + m ⋅ cos(ϕ ) ⋅ (Vth ⋅ max + rd ⋅ max ) (2.27)
2 π 4 8 3⋅π
As it can be noticed in Eq. (2.25) and Eq. (2.27), the operation with a low phase-shift
(φ≈0) leads to larger power losses in the diodes than in the transistors. Conversely, if the
converter operates with a high phase-shift of φ≈π, the losses in the transistors are larger
than in the diodes.
21
1.3.1.2 Switching power losses
Average switching losses in a fundamental period can be calculated by the summation of

all turn-on and turn-off losses:
 von (n)
V (
⋅ Aon ⋅ ion (n) 2 + Bon ⋅ ion (n) + Con + ) 

1 N
⋅ ∑ 
100 FIT
Psw = (2.28)
N ⋅ T n =1  voff (n)
+ (
⋅ Aoff ⋅ ioff (n) 2 + Boff ⋅ ioff (n) + Coff )

 V100 FIT 
where von and voff are respectively the voltages commutated during turn-on and turn-off,
ion and ioff are respectively the currents commutated during turn-on and turn-off, V100FIT is
the 100FIT test voltage and Aon, Bon, Con and Aoff, Boff, Coff are respectively the turn-on and
the turn-off energy loss characteristic coefficients.
As a high switching frequency has been assumed, the currents and voltages commutated
in the turn-on and the turn-off of the semiconductors are assumed to be the same (cf. Fig
2.6). Thus, Eq. (2.28) can be simplified to:
1 v ( n)
( )
N
Psw = ⋅ ∑ sw ⋅ A ⋅ isw (n) 2 + B ⋅ isw (n) + C (2.29)
N ⋅ T n =1 V100 FIT
isw = ion = ioff (2.30)

vsw = von = voff (2.31)
A = Aon + Aoff (2.32)
B = Bon + Boff (2.33)
C = C on + C off (2.34)
Given that the commutated voltage is assumed to be the mean DC bus voltage (Vbus) and
the switched current is the phase current, the previous expression can be approached as:
T
⋅ ∫ (I max ⋅ sin (ωt ) ⋅ ( A ⋅ I max ⋅ sin (ωt ) + ⋅B ) + C )dt =
Vbus
Psw _ S1 =
V100 FIT ⋅ T ⋅ Tsw T
2
(2.35)
Vbus  A ⋅ I max 2 B ⋅ I max C 
= ⋅ + + 
V100 FIT ⋅ Tsw  4 π 2 

The switching losses of the D4 freewheel diode are also calculated with Eq. (2.35).
However, the turn-on energy loss coefficients (Aon, Bon and Con) of Eq. (2.32), Eq. (2.33)
and Eq. (2.34) are equal to zero due to the negligible turn-on losses of diodes.
1.3.1.3 Total power losses
Because of the symmetrical structure of the 2L-VSC, all transistors as well as all diodes
have the same power losses. Therefore, once the losses of S1 and D4 are calculated, the
estimation of the total converter power losses is straightforward:
22
1.4. Three-level neutral point clamped converter
(
Pcond = 6 ⋅ Pcond _ S1 + Pcond _ D 4 ) (2.36)
(
Psw = 6 ⋅ Psw _ S1 + Psw _ D 4 ) (2.37)
For the DC bus capacitance calculation, the next assumptions are made:
• The converter has an AC side filter with negligible energy storage.

• The DC bus voltage is constant and smooth.
• The switching frequency is very high.
• The power factor of the converter is unitary.
Under these considerations, the DC side current (ibus in Fig 2.4) can be expressed as:
3 ⋅ V max ⋅ I max
ibus = (2.39)
2 ⋅ Vbus
where Vmax and Imax are the peak phase voltage and current respectively.
Eq. (2.39) shows the DC side current ibus is constant [8]. In reality, this current is chopped
and hence, it has high frequency components. Nonetheless, the effect of these high
frequency components over the DC bus voltage ripple are negligible and in consequence,
the required Cbus value is small. Therefore, the energy stored by it is small too.
As discussed for the three-phase DFE rectifier, when the AC side voltage is lower than
the DC bus voltage, the DC bus capacitor must provide the load power guaranteeing a
minimum DC bus voltage. To do so, Cbus must store a certain amount of energy. If the
transient power variation (P) is limited to the 10% of the rated power the bus capacitance
is expressed as:
2 ⋅ P ⋅ ∆T 3 ⋅ Vmax ⋅ I max ⋅ ∆T
Cbus = 2 2
=
 ∆v   ∆v  20 ⋅ Vbus ⋅ ∆v (2.40)
Vbus +  − Vbus − 
 2   2 
where Δv is the desired voltage ripple and ΔT is the time interval in which the capacitor
Cbus is being discharged.
1.4 Three-level neutral point clamped converter
Multilevel converters apply more than two levels at their output phase terminals thereby
reducing the dv/dt and the total harmonic distortion (THD) in comparison to the 2L-VSC
[5]. Furthermore, the use of multilevel converters reduces the series connection
requirements of power semiconductors and therefore, auxiliary circuits for voltage
23
balancing are avoided, or at least, minimized. Amog the different multilevel converters,
the three-level neutral point clamped converter (3L-NPC) [9] illustrated in Fig 2.8 is a
widely used topology in medium-voltage applications, e.g. in wind power, where it is one
of the most popular multilevel converter for medium-voltage variable speed wind turbines
[10].
The DC bus of the 3L-NPC is composed of two series connected capacitors (Cbus1 and
Cbus2) and each converter leg has four controlled switches with their antiparallel diodes.
The neutral point N of the DC bus is connected to the phase terminal through the clamp
diodes. Thus, three different voltage levels are applied at phase terminals (Vbus/2, 0 and -
Vbus/2).
The differences between the extracted and the injected charges from/to the neutral point
terminal lead to voltage unbalances in the DC bus capacitors. Thus, modulation or control
level considerations must be taken into account to achieve a proper voltage balance [5]. In
addition, the power loss distribution among the power switches is not symmetrical.
Therefore, the thermal stress in some semiconductors is higher than in others. In
consequence, the junction temperature of the most stressed power devices limits the
output power of the converter (might lead to derated power capacity in practical cases).
ibus
+
D1a S1a D1b S1b D1c S1c

+ Vbus
Cbus1
- 2
D2a S2a Dc1a S2b Dc1b S2c Dc1c
D2b D2c
ia a
ib b -
ic N
c +
D3a S3a Dc2a S3b Dc2b S3c Dc2c

D3b D3c
+ Vbus
Cbus2 -
- 2
D4a S4a D4b S4b D4c S4c
Fig 2.8. Three-level neutral point clamped converter.
Fig 2.9 shows the allowed switching states of one leg of the converter that, independently
of the phase current polarity, define the output voltage. When transistors S1 and S2 are
turned-on, the converter applies a voltage of Vbus/2 at phase terminals (cf. Fig 2.9a). When
the transistors are S2 and S3 transistors are turned-on, see Fig 2.9b, the current circulates
through the clamp diodes and zero voltage is applied at phase terminals. Finally, when S3
and S4 are turned-on, a -Vbus/2 voltage is applied at phase terminals as shown by Fig 2.9c.
At each switching state, the phase current sense determines the switches that are
24
conducting that current, transistors or freewheel diodes. Additionally, all the

semiconductors have to withstand a voltage of Vbus/2. Compared with the 2L-VSC, if
same voltage rated switching devices are used, the DC bus voltage can be doubled and
therefore, higher power is transferred.
+ + +
ibus
D1 S1 D1 S1 D1 S1
+ Vbus + Vbus + Vbus

Cbus1 Cbus1 Cbus1
- 2 - 2 - 2
D2 S2 Dc1 D2 S2 Dc1 D2 S2 Dc1
ibus
ia a
N
ia a
N
ia a
N
D3 S3 Dc2 D3 S3 Dc2 D3 S3 Dc2

+ V + V + Vbus
Cbus2
- - bus Cbus2
- - bus Cbus2
- -
2 2 2
D4 S4 D4 S4 D4 S4
ibus
- - -
a) b) c)
Fig 2.9. Switching states of the single-phase NPC. a) Positive voltage applied at the
output. b) Zero voltage applied at the output. c) Negative voltage applied at the
output.
In Table 2.1, afore described switching states are summarized. It can be noticed that S1-S3
and S2-S4 switches are complementary. This way, phase short circuits are avoided.
Furthermore, an additional switching state where S1-S4 are turned-on and S2-S3 are turned-
off is shown. This operational state is known as the forbidden state since the output
voltage applied at this state is uncontrollable (depends on the current sense). Additionally,
the voltage blocked by S2-D2 or S3-D3 is Vbus, which is two times the voltage stress they
withstand with allowed switching states. All in all, this switching state must be avoided.
TABLE 2.1
SWITCHING STATES OF THE SINGLE-PHASE NPC
Voltage applied
S1 S2 S3 S4
at phase terminal
Vbus/2 1 1 0 0
0 0 1 1 0
-Vbus/2 0 0 1 1
Vbus/2 or -Vbus/2 1 0 0 1
The 3L-NPC can be modulated with level-shifted PWM, SVM or selective harmonic
elimination (SHE) techniques [9, 11]. Fig 2.10 shows the typical waveforms of a single-
phase NPC operating with a level-shifted PWM modulation technique. As it can be
noticed, this modulation technique requires two level-shifted carriers (one per each pair of
complementary semiconductors). When the reference phase voltage va* is higher than the
carrier vcr1, S1 is turned-on and S3 is turned-off. Conversely, when the reference voltage
25
va* is lower than the carrier vcr1, S1 is turned-off and S3 is turned-on. Similarly, transistors
S2 and S4 are commanded the carrier vcr2.
v vcr1 va*
vcr2
S1
on
S4 t
on
vaN t
Vbus
2
t
vaN1 T
Fig 2.10. Typical voltage waveforms of a single-phase NPC with a level-shifted

As it has been mentioned, the phase voltage has three voltage levels (cf. Fig 2.10). The
line to line voltage is obtained subtracting the phase voltages. This way, five voltage
levels are achieved.
Assuming an ideal DC bus capacitor with no losses, the converter power losses are given
by the conduction and switching power losses of the semiconductors. These power losses
can be modeled with analytical expressions, obtained assuming the converter operates
with a high frequency PWM modulation [12] (similarly to that discussed in section 2.3.1).
Furthermore, assuming an ideal AC supply grid without unbalances, the current
circulating through each leg has the same amplitude and frequency. Therefore, the power
losses in each leg are the same.
In Fig 2.11, the currents circulating through the first leg of the 3L-NPC are shown. The
outer transistors S1 and S4 conduct the same current value with a 180 degree phase
displacement. Thus, average power losses in both transistors are equal. As it can be
noticed, this is applicable to inner transistors S2-S3, freewheel diodes D1-D2-D3-D4 and
26
clamp diodes Dc1-Dc2. Thus, power losses expressions are calculated just for one
semiconductor in each group.
π/2 3π/2
v
va* ia vcr1
φ
t
vcr2
S1
S2 t
S3 Ton Ton Ton t

S4 t
D1 – D2 t
D3 – D4 t
Dc1 t
Dc2 t
T t
Fig 2.11. Typical current waveforms of a single-phase NPC with a level-shifted PWM
modulation strategy.
1.4.1.1 Conduction power losses
Conduction power losses in a fundamental period (T) can be estimated by the summation
of conduction power losses in each switching period (Tsw). So, in order to obtain an
analytical conduction losses expression, the pulsating current waveform is converted into
a continuous current with similar average and rms current values:
27
1 N
Pcond = ⋅ ∑ rd ⋅ I rms (n )2 + Vth ⋅ I ave (n ) =
N n =1
(2.41)
1 N T T
= ⋅ ∑ rd ⋅ i a (n )2 ⋅ on (n ) + Vth ⋅ i a (n ) ⋅ on (n )
N n =1 Tsw Tsw
T
N= (2.42)
Tsw
where Vth is the threshold voltage in the semiconductor, rd is the characteristic on-state
resistance and Ton is the conduction time interval of the semiconductor.
When the semiconductors are on, the current through the semiconductors is equal to the
phase current:
i a (t ) = I max ⋅ cos(ωt − ϕ ) (2.43)

where Imax is the maximum amplitude of the phase current and φ is the phase-shift
between the reference voltage va* and the phase current ia.
As depicted in Fig 2.11, this current flows through semiconductors when the latter have a
turn-on command and the current circulates in the natural conduction sense of the
semiconductors. This last depends on the the phase-shift φ. Thus, each semiconductor is
current conducting during a given interval of the phase output voltage. These conduction
intervals are summarized in Table 2.2.
The total conduction time of the semiconductors within a fundamental period (T) is given
by the summation of the different Ton conduction times of the semiconductors. This
summation is modelled with a modulation function. Within a switching period, the Ton
conduction time of each semiconductor is proportional to the reference voltage va*. Thus,
the modulation function of each semiconductor is derived from of Eq. (2.44) and Fig
2.11. For transistor S1, the Ton conduction time is directly proportional to the reference
voltage (the lower va*, the narrower Ton). Therefore, the modulation function of this
transistor is equal to Eq. (2.44). Conversely, in the first conduction period comprehended
from (π/2+φ) to 3π/2, the Ton conduction interval of the transistor S2 is inversely
proportional to the reference voltage. After 3π/2, S2 is always conducting. Therefore, the
modulation function of this second conduction period is equal to one (the modulation
function must be within 0 and 1). The modulation functions of the rest of the
semiconductors are derived in a similar way and summarized in Table 2.2.
va * (t ) = m ⋅ cos(ωt ) (2.44)
where m is the modulation index.
28
TABLE 2.2
CONDUCTION TIMES AND MODULATION FUNCTIONS OF SINGLE-PHASE NPC'S SEMICONDUCTORS
3⋅π 3⋅π
Conducting From to +ϕ
2 2
S1
(t ) = m ⋅ cos(ωt )
Ton
Modulation function
Tsw
3⋅π 5 ⋅π
Conducting From +ϕ to
2 2
D1
(t ) = m ⋅ cos(ωt )
Ton
Modulation function
Tsw
π 3⋅π 3⋅π 3⋅π
Conducting From +ϕ to From to +ϕ
2 2 2 2
S2
(t ) = 1 + m ⋅ cos(ωt ) (t ) = 1
Ton Ton
Modulation function
Tsw Tsw
π 3⋅π 3⋅π 3⋅π
Conducting From +ϕ to From to +ϕ
2 2 2 2
Dc1
(t ) = 1 + m ⋅ cos(ωt ) (t ) = 1 − m ⋅ cos(ωt )
Ton Ton
Modulation function
Tsw Tsw
From Eq. (2.43) and Table 2.2 the average and rms current expressions are obtained and
thereby, conduction power losses given by Eq. (2.41) can be calculated:
• Outer transistor S1:

3⋅π
+ϕ
2
1 m ⋅ I max
I ave =
2 ⋅π
⋅ ∫ (− I max ⋅ cos(ωt − ϕ )) ⋅ m ⋅ cos(ωt )dωt = 4 ⋅π
⋅ (sin (ϕ ) − ϕ ⋅ cos(ϕ )) (2.45)
3⋅π
2
3⋅π
+ϕ
m ⋅ I max 2
( )
2
1
I rms 2 ∫ I max ⋅ cos (ωt − ϕ ) ⋅ m ⋅ cos(ωt )dωt = ⋅ 1 − 2 ⋅ cos(ϕ ) + cos2 (ϕ )
2 2
= ⋅ (2.46)
2 ⋅π 3⋅π 6 ⋅π
2
m ⋅ I max 2
Pcond _ S1 = Vth ⋅
m ⋅ I max
4 ⋅π
⋅ (sin (ϕ ) − ϕ ⋅ cos(ϕ )) + rd ⋅
6 ⋅π
(
⋅ 1 − 2 ⋅ cos(ϕ ) + cos 2 (ϕ ) ) (2.47)
where rd and Vth are the output characteristics of the semiconductor.
• Freewheel diode D1:

5⋅π
2
1
I ave = ⋅ ∫ I max ⋅ cos(ωt − ϕ ) ⋅ m ⋅ cos(ωt )dωt =
2 ⋅ π 3⋅π
2
+ϕ (2.48)
m ⋅ I max
= ⋅ (π ⋅ cos(ϕ ) + sin (ϕ ) − ϕ ⋅ cos(ϕ ))
4 ⋅π
29
5⋅π
m ⋅ I max 2
( )
2
1
I rms 2
= ⋅ ∫ I max 2 ⋅ cos2 (ωt − ϕ ) ⋅ m ⋅ cos(ωt )dωt = ⋅ 1 + 2 ⋅ cos(ϕ ) + cos2 (ϕ ) (2.49)
2 ⋅ π 3⋅π 6 ⋅π
+ϕ
2
m ⋅ I max
Pcond _ D1 = Vth ⋅ ⋅ (π ⋅ cos(ϕ ) + sin (ϕ ) − ϕ ⋅ cos(ϕ )) +
4 ⋅π
(2.50)
m ⋅ I max 2
+ rd ⋅
6 ⋅π
(
⋅ 1 + 2 ⋅ cos(ϕ ) + cos 2 (ϕ ) )
• First conduction period (from π/2+φ to 3π/2) of inner transistor S2 and clamp
diode Dc1:
3⋅π
2
1
I ave = ⋅ ∫ (− I max ⋅ cos(ωt − ϕ )) ⋅ (1 + m ⋅ cos(ωt ))dωt =
2 ⋅π π
+ϕ
2 (2.51)
m ⋅ I max  2 + 2 ⋅ cos(ϕ ) 
= ⋅ + ϕ ⋅ cos(ϕ ) − sin (ϕ ) − π ⋅ cos(ϕ )
4 ⋅π  m 
3⋅π
2
1
I rms 2 = ⋅ ∫ I max 2 ⋅ cos 2 (ωt − ϕ ) ⋅ (1 + m ⋅ cos(ωt ))dωt =
2 ⋅π π
+ϕ
2 (2.52)
m ⋅ I max 2  3 ⋅ (π − ϕ ) + 3 ⋅ sin (ϕ ) ⋅ cos(ϕ ) 
= ⋅ − 1 − 2 ⋅ cos(ϕ ) − cos 2 (ϕ )
6 ⋅π  2 ⋅ m 
m ⋅ I max  2 + 2 ⋅ cos(ϕ ) 
Pcond _ S 2 / 1 = Pcond _ Dc1 / 1 = Vth ⋅ ⋅ + ϕ ⋅ cos(ϕ ) − sin (ϕ ) − π ⋅ cos(ϕ ) +
4 ⋅π  m 
(2.53)
m ⋅ I max 2  3 ⋅ (π − ϕ ) + 3 ⋅ sin (ϕ ) ⋅ cos(ϕ ) 
+ rd ⋅ ⋅ − 1 − 2 ⋅ cos(ϕ ) − cos 2 (ϕ )
6 ⋅π  2 ⋅ m 
• Second conduction period (from 3π/2 to 3π/2+φ) of inner transistor S2:

3⋅π
+ϕ
2
1 I max
I ave =
2 ⋅π
⋅ ∫ (− I max ⋅ cos(ωt − ϕ ))dωt = 2 ⋅π
⋅ (1 − cos(ϕ )) (2.54)
3⋅π
2
3⋅π
+ϕ
1 2
I max 2
I rms 2
= ⋅ ∫ I max
2
⋅ cos 2 (ωt − ϕ )dωt = ⋅ (ϕ − cos(ϕ ) ⋅ sin (ϕ )) (2.55)
2 ⋅π 3⋅π 4 ⋅π
2
I 2
⋅ (1 − cos(ϕ )) + rd ⋅ max ⋅ (ϕ − cos(ϕ ) ⋅ sin (ϕ ))
I max
Pcond _ S 2 / 2 = Vth ⋅ (2.56)
2 ⋅π 4 ⋅π
30
• Second conduction period (from 3π/2 to 3π/2+φ) of clamp diode Dc1:

3⋅π
+ϕ
2
1
I ave =
2 ⋅π
⋅ ∫ (− I max ⋅ cos(ωt − ϕ )) ⋅ (1 − m ⋅ cos(ωt ))dωt =
3⋅π
2 (2.57)
m ⋅ I max  2 − 2 ⋅ cos(ϕ ) 
= ⋅ + ϕ ⋅ cos(ϕ ) − sin (ϕ )
4 ⋅π  m 
3⋅π
+ϕ
2
1
I rms 2 = ⋅ ∫ I max
2
⋅ cos 2 (ωt − ϕ ) ⋅ (1 − m ⋅ cos(ωt ))dωt =
2 ⋅π 3⋅π
2 (2.58)
m ⋅ I max 2  3 ⋅ ϕ − 3 ⋅ sin (ϕ ) ⋅ cos(ϕ ) 
= ⋅ − 1 + 2 ⋅ cos(ϕ ) − cos 2 (ϕ )
6 ⋅π  2 ⋅ m 
m ⋅ I max  2 − 2 ⋅ cos(ϕ ) 
Pcond _ Dc1 / 2 = Vth ⋅ ⋅ + ϕ ⋅ cos(ϕ ) − sin (ϕ ) +
4 ⋅π  m 
(2.59)
m ⋅ I max 2  3 ⋅ ϕ − 3 ⋅ sin (ϕ ) ⋅ cos(ϕ ) 
+ rd ⋅ ⋅ − 1 + 2 ⋅ cos(ϕ ) − cos 2 (ϕ )
6 ⋅π  2 ⋅ m 
1.4.1.2 Switching power losses
Average switching losses in a fundamental period can be calculated by the summation of

all turn-on and turn-off losses:
 von (n)
V (
⋅ Aon ⋅ ion (n) 2 + Bon ⋅ ion (n) + Con + ) 

1 N
⋅ ∑ 
100 FIT
Psw = (2.60)
N ⋅ T n =1  voff (n)
+
 V100 FIT
(
⋅ Aoff ⋅ ioff (n) 2 + Boff ⋅ ioff (n) + Coff )


where von and voff are respectively the voltages commutated during turn-on and turn-off,
ion and ioff are respectively the currents commutated during turn-on and turn-off, V100FIT is
the 100FIT test voltage and Aon, Bon, Con and Aoff, Boff, Coff are respectively the turn-on and
the turn-off energy loss characteristic coefficients.
Under the assumption of a high switching frequency, the currents and voltages
commutated in the turn-on and the turn-off of the semiconductors are assumed to be the
same. Moreover, considering a sufficiently large DC bus capacitor, the DC bus voltage
ripple can be neglected and the switched voltage is assumed to be the average DC bus
voltage Vbus.
31
Thus, the overall expression of the average switching power losses of S1, D1, S2 and Dc1
are given respectively by:
3⋅π
+ϕ
2
Vbus ⋅ f sw
Psw _ S1 =
V100 FIT ⋅ 2 ⋅ π ∫ ((− I max ⋅ cos(ωt − ϕ )) ⋅ ( A ⋅ (− I max ⋅ cos(ωt − ϕ )) + ⋅B ) + C )dt =
3⋅π
2 (2.61)
=
Vbus ⋅ f sw
4 ⋅ π ⋅ V100 FIT
(
⋅ A ⋅ I max 2 ⋅ (ϕ − sin (ϕ ) ⋅ cos(ϕ )) + 2 ⋅ B ⋅ I max ⋅ (1 − cos(ϕ )) + 2 ⋅ C ⋅ ϕ )
5⋅π
2
∫ (I max ⋅ cos(ωt − ϕ ) ⋅ (Aoff ) )
Vbus ⋅ f sw
Psw _ D1 = ⋅ I max ⋅ cos(ωt − ϕ ) + ⋅Boff + Coff dt =
V100 FIT ⋅ 2 ⋅ π 3⋅π
+ϕ
2 (2.62)
=
Vbus ⋅ f sw
4 ⋅ π ⋅ V100 FIT
(
⋅ A ⋅ I max 2 ⋅ (π − ϕ + sin (ϕ ) ⋅ cos(ϕ )) + 2 ⋅ B ⋅ I max ⋅ (1 + cos(ϕ )) + 2 ⋅ C ⋅ (π − ϕ ) )
3⋅π
2
Vbus ⋅ f sw
Psw _ S 2 =
V100 FIT ⋅ 2 ⋅ π ∫ ((− I max ⋅ cos(ωt − ϕ )) ⋅ ( A ⋅ (− I max ⋅ cos(ωt − ϕ )) + ⋅B ) + C )dt =
π
+ϕ
2 (2.63)
=
Vbus ⋅ f sw
4 ⋅ π ⋅ V100 FIT
(
⋅ A ⋅ I max 2 ⋅ (π − ϕ + sin (ϕ ) ⋅ cos(ϕ )) + 2 ⋅ B ⋅ I max ⋅ (1 + cos(ϕ )) + 2 ⋅ C ⋅ (π − ϕ ) )
3⋅π
+ϕ
2
∫ ((− I max ⋅ cos(ωt − ϕ )) ⋅ (Aoff ⋅ (− I max ⋅ cos(ωt − ϕ )) + ⋅Boff ) + Coff )dt =
Vbus ⋅ f sw
Psw _ Dc1 =
V100 FIT ⋅ 2 ⋅ π π
2
+ϕ
(2.64)
=
Vbus ⋅ f sw
4 ⋅ π ⋅ V100 FIT
(
⋅ π ⋅ A ⋅ I max 2 + 4 ⋅ B ⋅ I max + 2 ⋅ C ⋅ π )
A = Aon + Aoff (2.65)
B = Bon + Boff (2.66)
C = C on + C off (2.67)
where fsw is the semiconductor switching frequency.
1.4.1.3 Total power losses
Once the switching power losses of selected switching devices are calculated, the total
conduction and switching losses can be described as:
(
Pcond = 6 ⋅ Pcond _ S1 + Pcond _ D1 + Pcond _ S 2 / 1 + Pcond _ S 2 / 2 + )
(2.68)
(
+ 6 ⋅ Pcond _ D1c / 1 + Pcond _ D1c / 2 )
(
Psw = 6 ⋅ Psw _ S1 + Psw _ D1 + Psw _ S 2 + Psw _ Dc1 ) (2.69)
32
The DC bus of the 3L-NPC is composed of two series connected capacitors. Ideally, both
absorb the same amount of charges and therefore, their capacitance is same. Thus, for the
sake of simplicity, the following analysis is focused on the upper capacitor Cbus1.
Assuming a constant DC bus voltage with no ripple (Vbus), the current circulating through
the positive bus terminal (ibus of Fig 2.8) depends on the instantaneous power p(t) and the
voltage of the upper capacitor (Vbus/2):
2 ⋅ p (t )
ibus = (2.71)
Vbus
If one leg is applying a positive voltage to the phase terminal, the phase current circulates
through the positive bus terminal.
v va vb vc
T/12 T/4 5T/12 7T/12 3T/4 11T/12 T
Fig 2.12. AC side voltage waveforms of the 3L-NPC.
Assuming a unitary power factor, Fig 2.12 shows the different time intervals to calculate
the ibus current circulating through the positive bus terminal. Phase a current circulates
from 0 to T/4 and from 3T/4 to T. Similarly, phase b current circulates through the
positive bus terminal from T/12 to 7T/12, while phase c current does it from 5T/12 to
11T/12. Thus, the instantaneous ibus current circulating through the positive bus terminal
are calculated as follows:
• From 0 to T/12:
2 ⋅ p (t ) 2
ibus = = ⋅ (v a (t ) ⋅ i a (t ) + 0 ⋅ ib (t ) + 0 ⋅ i c (t ) ) =
Vbus Vbus
(2.72)
2 ⋅I
⋅ V max ⋅ cos(ωt ) ⋅ I max ⋅ cos(ωt ) = max max ⋅ (1 + cos(2ωt ))
V
=
Vbus Vbus
where Vmax and Imax are the peak phase voltage and current respectively.
33
• From T/12 to T/4:

2 ⋅ p (t ) 2
ibus = = ⋅ (v a (t ) ⋅ i a (t ) + vb (t ) ⋅ ib (t ) + 0 ⋅ ic (t ) ) =
Vbus Vbus
2   2 ⋅π   2 ⋅π 
= ⋅ V max ⋅ cos(ωt ) ⋅ I max ⋅ cos(ωt ) + V max ⋅ cos ωt −  ⋅ I max ⋅ cos ωt −   = (2.73)
Vbus   3   3 
V max ⋅ I max   2 ⋅π 
= ⋅  2 − cos 2ωt −  
Vbus   3 
• From T/4 to 5T/12:

2 ⋅ p (t ) 2
ibus = = ⋅ (0 ⋅ i a (t ) + vb (t ) ⋅ ib (t ) + 0 ⋅ ic (t ) ) =
Vbus Vbus
(2.74)
2  2 ⋅π   2 ⋅ π  Vmax ⋅ I max   4 ⋅π 
= ⋅ Vmax ⋅ cos ωt −  ⋅ I max ⋅ cos ωt − = ⋅ 1 + cos 2ωt − 
Vbus  3   3  V bus   3  
• From 5T/12 to 7T/12:

2 ⋅ p (t ) 2
ibus = = ⋅ (0 ⋅ i a (t ) + vb (t ) ⋅ ib (t ) + v c (t ) ⋅ ic (t ) ) =
Vbus Vbus
2  2 ⋅π   2 ⋅π 
= ⋅ V max ⋅ cos ωt −  ⋅ I max ⋅ cos ωt − +
Vbus  3   3 
(2.75)
2  2 ⋅π   2 ⋅π 
+ ⋅ V max ⋅ cos ωt +  ⋅ I max ⋅ cos ωt + =
Vbus  3   3 
Vmax ⋅ I max
= ⋅ (2 − cos(2ωt ))
Vbus
• From 7T/12 to 3T/4:

2 ⋅ p (t ) 2
ibus = = ⋅ (0 ⋅ i a (t ) + 0 ⋅ ib (t ) + v c (t ) ⋅ ic (t ) ) =
Vbus Vbus
(2.76)
2  2 ⋅π   2 ⋅ π  Vmax ⋅ I max   4 ⋅π 
= ⋅ Vmax ⋅ cos ωt +  ⋅ I max ⋅ cos ωt + = ⋅ 1 + cos 2ωt +  
Vbus  3   3  Vbus   3 
34
• From 3T/4 to 11T/12:

2 ⋅ p (t ) 2
ibus = = ⋅ (v a (t ) ⋅ i a (t ) + 0 ⋅ ib (t ) + v c (t ) ⋅ ic (t ) ) =
Vbus Vbus
2   2 ⋅π   2 ⋅π 
= ⋅ V max ⋅ cos(ωt ) ⋅ I max ⋅ cos(ωt ) + V max ⋅ cos ωt +  ⋅ I max ⋅ cos ωt +   = (2.77)
Vbus   3   3 
V max ⋅ I max   2 ⋅π 
= ⋅  2 − cos 2ωt +  
Vbus   3 
• From 11T/12 to T:
2 ⋅ p (t ) 2
ibus = = ⋅ (v a (t ) ⋅ i a (t ) + 0 ⋅ ib (t ) + 0 ⋅ ic (t ) ) =
Vbus Vbus
(2.78)
2 ⋅I
⋅ V max ⋅ cos(ωt ) ⋅ I max ⋅ cos(ωt ) = max max ⋅ (1 + cos(2ωt ))
V
=
Vbus Vbus
The estimated current through positive bus terminal is shown in Fig 2.13. As it is noticed,
the current oscillates over a mean value, which is the average power provided by the AC
supply.
ibus
Q
3Vmax Imax
2Vbus
T/12 T/4 5T/12 7T/12 3T/4 11T/12 T t
Fig 2.13. Current circulating through the positive bus terminal of the 3L-NPC.
Assuming the mean current is drawn by the load connected to the DC bus, the current
circulating through the capacitor will be the oscillating term of ibus, which is given by the
third harmonic of the fundamental period (T). Thus, the Q charges illustrated in Fig 2.13
and circulating through Cbus1 can be expressed as:
5⋅T 5⋅T
12 12 V max ⋅ I max   4 ⋅π  3 
Q= ∫ iCbus (t )dt = ∫ ⋅ 1 + cos 2ωt −

 − dt =
3  2 
T T Vbus 
4 4
(2.79)
Vmax ⋅ I max ⋅ T  3 1  Vmax ⋅ I max ⋅ T
= ⋅ − ≈
4 ⋅ Vbus  π 3 6 ⋅ π ⋅ Vbus
 
35
Hence, the capacitance of Cbus1 is provided by Eq. (2.79) and the desired voltage ripple
(Δv):
Vmax ⋅ I max ⋅ T  3 1  Vmax ⋅ I max ⋅ T

Cbus1 = ⋅ − ≈ (2.80)
4 ⋅ Vbus ⋅ ∆v  π 3  6 ⋅ π ⋅ V ⋅ ∆v
  bus
As it has been assumed that capacitor Cbus2 absorb the same amount of charges as
capacitor Cbus1, it is considered that their capacitance is same.
Since the DC bus capacitors are series connected, the total capacitance required by the
DC bus (Cbus) can be approximated to:
Vmax ⋅ I max ⋅ T
Cbus ≈ (2.81)
12 ⋅ π ⋅ Vbus ⋅ ∆v
1.5 Cascaded H-bridge converter
The cascaded H-bridge (CHB) converter [13-14] has been used in real drive applications
[5] and static synchronous compensator (STATCOM) applications [15-17]. As illustrated
in Fig 2.14, the CHB converter is composed of series connected single-phase H-bridge
(HB) converters. Each HB converter comprises one DC bus capacitor and four
bidirectional switches. Generally speaking, the number chained HB converters depends
on the AC side voltage and the voltage blocking capability of the used switching devices.
For a given semiconductor device, a higher AC side voltage leads to a higher number of
chained HB converters. Thus, series connection of power semiconductor devices is not
required. The increase of HB modules increases the number of voltage levels at the AC
output terminals and hence, the output voltage quality is improved (less dv/dt and
harmonic distortion).
The modularity of this converter makes possible the use of simple and well known HB
modules, which brings economical and technical benefits [15]. In addition, redundant HB
modules can be included so as to increase the reliability of the converter. Thus, the failure
of one HB converter does not jeopardize the energy transmission capability of the
converter [18].
The main drawback resides in the need of independent DC power supplies for each HB
converter, especially, when active power is transferred. Additionally, the capacitance
required by the DC bus is higher than that required by three-phase rectifiers due to the
second harmonic current component. This will be discussed later on section 2.5.2.
36
1.5. Cascaded H-bridge converter
ia ib ic
a b c
ibus
+
S1 D1 S2 D2
ia +
ia
Cbus
-
Vbus
S3 D3 S4 D4
Fig 2.14. Cascaded H-bridge converter.
Table 2.3 shows the allowed switching states and the three different voltages synthesized
at the output of each HB (Vbus, 0 and -Vbus). When switches S1 and S4 are on, a Vbus voltage
is applied at the output terminals. Conversely, when switches S2 and S3 are on, a -Vbus
37
voltage is applied at the output terminals. Finally, two operational states can be used to
apply 0 volts at the phase terminals, S1=S2=1 or S3=S4=1. From Table 2.3 and Fig 2.14, it
can be deduced that switches S1 and S3 are complementary since their simultaneous
conduction leads to a DC bus short circuit. This is applied also to switches S2 and S4. The
used switching devices must withstand the DC bus voltage of the HB converter (Vbus).
TABLE 2.3
OPERATIONAL STATES OF THE SINGLE-PHASE HB CONVERTER
Voltage applied
S1 S2 S3 S4
at phase terminal
Vbus 1 0 0 1
0 1 1 0 0
0 0 0 1 1
-Vbus 0 1 1 0
Since switches S1 and S3 as well as S2 and S4 are complementary, the output voltage of a
HB converter can be expressed as a function of the switching states of S1 and S2:
Vout , HB = Vbus ⋅ ( S1 + S 2 − 1) (2.82)
Therefore, it can be deduced that the maximum voltage applied by a CHB converter
composed of nHB modules with the same DC bus voltage (Vbus) is:
V max,CHB = Vbus ⋅ n HB (2.83)
For that number of HB modules, the number of phase voltage levels (k) and the number
of line to line voltage levels (h) are:
k = 2 ⋅ nHB + 1 (2.84)
h = 2 ⋅ k −1 (2.85)
The preferred modulation techniques for the CHB converters are the phase-shifted PWM
and the SVM [19].
Fig 2.15 shows the typical voltage and command waveforms of a single-phase HB
converter modulated with a phase-shifted PWM technique. As it can be seen, there are
two triangular carriers (vcr1 and vcr2) phase-shifted 180 degrees each other and a reference
voltage (vHB*). The switching orders of S1 depends on the triangular carrier wave vcr1
while the orders of S4 depends on vcr2.
While the carriers of a HB are 180 degrees phase-shifted in order to synthesize a proper
voltage waveforms, the carriers of the different nHB HB modules must be phase-shifted in
PS degrees:
180º
PS = (2.86)
nHB
38
1.5. Cascaded H-bridge converter
Additionally, the modulation index mHB of each HB converter depends on its DC bus
voltage (Vbus) and the number of chained converters (nHB):
v*
m HB = (2.87)
Vbus ⋅ n HB
where v* is the maximum phase reference voltage.
v vcr1 vHB* vcr2
S1
on
S4 t
on
vout t
Vbus
t
vout1 T
Fig 2.15. Typical command and voltage waveforms of a single-phase HB converter.
As shown in Fig 2.15, the behaviour of each leg of the single-phase HB converter is
identical to that of each leg of the 2L-VSC (section 2.3). Hence, power losses can be
estimated with Eq. (2.25) and Eq. (2.27) for conduction losses and Eq. (2.35) for
switching losses. Therefore, total conduction and switching losses are:
(
Pcond = 12 ⋅ nHB ⋅ Pcond _ S1 + Pcond _ D 4 ) (2.88)
(
Psw = 12 ⋅ nHB ⋅ Psw _ S1 + Psw _ D 4 ) (2.89)
39
As discussed for the 2L-VSC, capacitance Cbus is defined by the charges (Q) circulating
through the capacitor and the desired voltage ripple (Δv). In turn, the circulating charges
are given by the current circulating through the capacitor (iCbus), which assuming a
constant DC bus with no ripple (Vbus), is given by the instantaneous DC side power p(t).
Assuming that the load will absorve the mean power, the 2ωt oscillating power is
continuously stored and transferred by the bus capacitor.
The DC side current (ibus current depicted in Fig 2.14) depends on the DC bus voltage
(Vbus) and the instantaneous power (p(t)):
p (t )
ibus = (2.91)
Vbus
In addition, the DC bus voltage of each HB converter is given by the peak phase voltage
(Vmax) and the number of phase modules (nHB):
V max
Vbus = (2.92)
n HB
Assuming a unitary power factor, the instantaneous power absorbed by each HB module
is:
Vmax HB ⋅ I max HB
p(t ) = v(t ) ⋅ i (t ) = Vmax HB ⋅ sin (ωt ) ⋅ I max HB ⋅ sin (ωt ) = ⋅ (1 − cos(2ωt )) (2.93)
2
where VmaxHB and ImaxHB are respectively the maximum output voltage and the maximum
current through each HB module.
As it can be observed in Eq. (2.93), the instantaneous power has two main components: a
constant term and an oscillating term. As the constant term is the average power
transferred by the converter, the power circulating through the capacitor is equal to the
oscillating term:
Vmax HB ⋅ I max HB
p (t ) = − ⋅ cos(2ωt ) (2.94)
2
Introducing Eq. (2.94) into Eq. (2.91), the current through the capacitor is expressed as:
V max HB ⋅ I max HB
iCbus (t ) = − ⋅ cos(2ωt ) (2.95)
2 ⋅ Vbus
As it is noticed in the current circulating through the Cbus capacitor illustrated in Fig 2.16,
the charges are absorbed between T/8 and 3T/8:
3⋅T
8 V max HB ⋅ I max HB ⋅ T
Q= ∫ iCbus (t )dt = 4 ⋅ π ⋅ Vbus
(2.96)
T
8
where T is the fundamental period of the AC side current.
40
1.6. Summary
iCbus
Q
T/8 3T/8 5T/8 7T/8 T
Fig 2.16. Current circulating through the DC bus capacitor of a HB module.
Therefore, the required DC bus capacitance to obtain a given voltage ripple (Δv) can be
expressed as:
V max HB ⋅ I max HB ⋅ T
C bus = (2.97)
4 ⋅ π ⋅ Vbus ⋅ ∆v
It must be highlighted that single-phase HB converters require larger capacitor values

than three-phase converters. This difference comes from the second current harmonic
component circulating in the DC bus capacitor of single phase converters shown by Eq.
(2.97).
1.6 Summary
Rectifiers convert AC side voltages and currents to DC side voltages and currents.
Depending on the rectifier type, the DC side voltage can be constant or AC input voltage
dependent. In this chapter, different rectifier topologies have been studied. For each
converter, analytical expressions for the estimation of the DC bus capacitor and power
losses have been presented.
The main characteristics of the analysed converters can be summarized as:
• The three-phase DFE rectifier is a unidirectional, cheap, simple and reliable

converter. As this converter does not provide any control over the output voltage,
the DC side voltage is dependent on the AC input voltage. Compared to VSC
type rectifiers, the AC side current waveform contains more harmonic
components, which provoke heating and torque issues to the generators in the AC
side.
• Compared with the DFE rectifier, 2L-VSC requires controlled switching devices
that increase its complexity. However, the DC bus voltage controllability and the
better AC side waveforms quality have become this converter in one of the most
used rectifiers in several industrial applications.
• Multilevel converters overtake the 2L-VSC in terms of switch power losses,
harmonic distortion, applied voltage derivatives to the AC side generator and
41
common mode voltage. The 3L-NPC has become the preferred multilevel
converter demonstrating a reliable and efficient performance. As each leg is
composed of four series connected switching devices, the total DC bus voltage
can be twice the DC bus voltage of the 2L-VSC. In consequence, this converter is
better suited for medium voltage than the 2L-VSC.
• The modular structure of the CHB makes possible the operation of the converter
at high voltages and the use of redundant modules leads to high reliability. Its
main drawback is the high number of capacitors it requires. Furthermore, as the
CHB converter is composed of single-phase HB converters, the second current
harmonic component circulating through their DC bus capacitors makes the
required DC bus capacitor larger than that required by three-phase converters.
.
42
Chapter 2
DC-DC converters
This chapter describes the main features of 17 different switch mode DC-DC converters
and 10 different resonant mode DC-DC converter topologies. It also discusses analytical
models required for their design and semiconductor power loss estimation.
2.1 Introduction
DC-DC converters are used to convert an input DC voltage level to another output DC
voltage level. Generally speaking, the converters that maintain the output voltage higher
than the input voltage are known as step-up converters or boost derived converters.
Conversely, step-down or buck derived converters maintain the output voltage lower than
the input voltage. The converters that allow the output voltage being either higher or
lower than the input voltage are known as step-up/down or buck/boost converters.
Depending on the switching conditions of the semiconductors, DC-DC converters can be
divided in two main groups: switch mode converters and resonant mode converters. On
the one hand, most of the switch mode converters operate under hard switching
conditions. In consequence, the semiconductors must withstand high switching stresses
making the switching power losses to increase linearly with the switching frequency. In
addition, the electromagnetic interferences (EMIs) produced by the high di/dt and dv/dt
are another drawback of this kind of converters. In order to reduce the problems derived
from the hard switching conditions, the converters operate with relatively low switching
frequencies and thereby, the volume, size and weight of these converters is high (low
power density). On the other hand, resonant mode converters provide soft switching
conditions to the semiconductors (zero voltage switching or zero current switching) and
43
Chapter 2. DC-DC converters
therefore, the aforementioned problems can be avoided or, at least, reduced. Thus,
operation at higher frequencies is possible. Main drawbacks of resonant converters reside
on the volume of the resonant tank and the voltage/current stress of the passive elements
of the resonant tank.
When an AC input voltage has a variable amplitude (for example an AC source regulated
through an autotransformer) and is rectified through a three-phase DFE rectifier, the input
DC bus voltage of the DC-DC converter completely depends on the AC input voltage
amplitude. This makes the DC-DC converter to operate with a non-constant input voltage,
which makes more challenging its design and control. These issues can be addressed if
the input DC voltage of the DC-DC converter is kept constant. To do so, AFE rectifiers
must be considered.
In this chapter, 17 different switch mode converters and 10 different resonant mode
converters are analysed. Converter design equations and power loss estimation methods
are discussed. Although most of the analyzed DC-DC converters require a medium
frequency transformer (MFT), its analysis is not discussed along this chapter. The
thorough analysis of the MFT will be discussed in Chapter 4.
2.2 Switch mode DC-DC converters
Generally speaking, switch mode DC-DC converter semiconductors are operated under
hard switching conditions. However, soft switching operation conditions can also be
achieved if specific converter topologies (e.g. single-active-bridge and dual-active-
bridge), modulation techniques (e.g. phase-shifting) or additional circuitry (e.g. snubbers)
are considered.
In this section, converter design and power loss estimation expressions are presented for
different converter topologies. On the one hand, it is assumed that main power losses of
the converter come from the power semiconductors. In consequence, power losses in the
passive elements are neglected. Therefore, total average power losses of the converters
are calculated by the sum of average conduction power losses (Eq. (3.1)) and average
switching power losses (Eq. (3.2)) of the semiconductors. Average conduction power
losses depend on rms and average currents (Irms, Iave) through the semiconductors and the
output characteristic of the semiconductor (rd, Vth). In turn, average switching power
losses depend on switched voltages (vsw) and currents (isw) and the switching loss
characteristic provided by the manufacturer (Asw, Bsw and Csw). Additionally, analytical
expressions of the maximum current circulating through the semiconductors (imax) and
their maximum reverse blocking voltage (vmax) are calculated. These calculations allow
selecting semiconductors with appropriate voltage and current ratings for each converter.
All the aforementioned expressions have been validated through simulations in
Synopsys/SABER platform as it is shown in Appendix A.
44
2.2. Switch mode DC-DC converters
Pcond = rd ⋅ I rms 2 + Vth ⋅ I ave (3.1)
Psw =
1 N vsw (n)
⋅∑
N n =1 V100 FIT
( )
⋅ Asw ⋅ isw (n) 2 + Bsw ⋅ isw (n) + Csw ⋅ f sw (3.2)
where rd is the semiconductor switch on-state resistance, Vth is the threshold voltage, fsw is
the switching frequency and Asw, Bsw, Csw are the energy loss characteristic provided by
the manufacturer for the 100FIT test voltage (V100FIT).
On the other hand, this section discusses the design expressions required for the sizing of
each converter. Moreover, in order to minimize the installed semiconductor power, the
semiconductor utilization factor [20] of each converter has been calculated. This factor
determines the relation between the installed semiconductor power and the rated power of
the converter:
PRated
Uf = (3.3)
∑all _ switches v max ⋅ I rms
where vmax is the maximum reverse blocking voltage of the semiconductors and Irms is the
rms current circulating through them.
In order to obtain easy to use expressions, the semiconductor utilization factor has been
calculated assuming a continuous current mode (CCM) operation of the converters and
neglecting the voltage ripple in vmax and current ripple in Irms.
In order to reduce the number of equations of the buck/boost type DC-DC converters,
only the expressions of the boost operation cases are discussed, i.e. it is assumed that the
output voltage is higher than the input voltage. The expressions of the buck operation
cases, when the output voltage is lower than the input voltage, could be easily deduced
from the waveforms shown in each section.
2.2.1 Boost
The boost converter is a well known unidirectional step-up converter used in applications
where no galvanic isolation is required [8]. Depicted in Fig 3.1, the converter has few
components, which makes its structure to be simple and reliable.
Iin +
L1
- D1 Iout
+ iL1 +
+ S1 +
Vin Cin Cout Vout
- -
iCin iCout
- -
Fig 3.1. Boost converter.
2.2.1.1 Converter design
The converter operates storing the energy coming from the input in L1 and then
transferring it to the output. As shown in Fig 3.2a, when transistor S1 is on (Ton time
45
interval), the energy coming from the input is stored in the inductor L1 and the output
power is supplied by the capacitor Cout. When transistor S1 is off (Toff time interval), the
energy coming from the input and the energy stored in L1 are transferred to Cout and the
output load (Fig 3.2b). If the current circulating through the inductor L1 is greater than
zero, the converter operates in a continuous current mode (CCM). In contrary, if the
inductor current reaches to be zero, the converter operates in a discontinuous current
mode (DCM).
L1 D1 L1 D1
+ Iout + + Iout +
S1 Vout Vin S1 Vout
Vin Cin Cout Cin Cout
Iin Iin
- - - -
a) b)
Fig 3.2. Currents circulating through the boost converter a) when S1 is on and b) when
S1 is off.
Therefore, considering a steady state CCM operation, the voltage and current waveforms
of the inductor L1 and the capacitor Cout are illustrated in Fig 3.3a and Fig 3.3b. Notice
that the voltage ripple in L1 and the current ripple in Cout have been neglected.
iL1 vCout
ΔiL1 ΔvCout
Iin Vout
Ton Toff
D1 Conducting
S1 Conducting Ton Toff
vL1
Tsw t iCout
Tsw t
Vin Iin-Iout
y=-sinx, x∊[0,2π] y=-sinx, x∊[0,2π]

t t
Vin-Vout -Iout
a) b)
Fig 3.3. Typical voltage and current waveforms in boost converter's a) inductor L1 and
b) capacitor Cout.
The relation between the input voltage and the output voltage (DC voltage transfer
function) can be obtained from Fig 3.3a. As the average current circulating through L1 is
constant, the mean voltage drop in the inductor (<vL1>) during a switching period Tsw is
equal to zero, Eq. (3.4). Developing Eq. (3.4), the DC voltage transfer function given by
Eq. (3.5) is obtained.
46
1  Ton Tsw 
vL1 = ⋅  ∫ vL1 dt + ∫ vL1 dt  = 0 (3.4)
Tsw  
 0 Ton 
Vin
Vout = (3.5)
1−δ
Ton
δ = (3.6)
Tsw
where Vin and Vout are the average input and output voltages respectively (cf. Fig 3.1), δ is
the transistor's duty cycle and Tsw is the switching period. Eq. (3.5) shows that the output
voltage is higher than the input voltage for any duty cycle. So, the step-up nature of this
converter is corroborated.
Similarly, the relation between the input current and the output current (DC current
transfer function) is obtained. From Fig 3.3b the average voltage of Cout is constant and in
consequence, the average current through the capacitor (<iCout>) during a switching
period Tsw is equal to zero, Eq. (3.7). Solving Eq. (3.7) for the currents in Fig 3.3b, the
DC current transfer function given by Eq. (3.8) is obtained.
1  Ton Tsw 
iCout = ⋅  ∫ iCout dt + ∫ iCout dt  = 0 (3.7)
Tsw  
 0 Ton 
I out = I in ⋅ (1 − δ ) (3.8)
where Iin and Iout are the average input and output currents respectively (cf. Fig 3.1).
As it can be concluded from Eq. (3.5) and Eq. (3.8), the duty cycle of the boost converter
must be lower than one. If the duty cycle is equal to one, the input current will
theoretically increase up to infinite while the load will discharge the output capacitance.
This undesired behaviour can be easily avoided limiting the maximum duty cycle of the
converter.
Fixing the desired current ripple ∆iL1 and voltage ripple ∆vCout, the values of L1 and Cout
are calculated from Fig 3.3a and Fig 3.3b respectively:
∆t Vin
L1 = vL1 ⋅ = ⋅ δ ⋅ Tsw (3.9)
∆i 2 ⋅ ∆iL1
∆t I out
Cout = iCout ⋅ = ⋅ δ ⋅ Tsw (3.10)
∆v 2 ⋅ ∆vCout
Assuming the input current Iin is constant and non-zero, Fig 3.4 shows that the current
circulating through the input capacitor (Cin) has a zero average value and the same current
ripple as that in the inductor (∆iL1).
47
iCin
QCin
ΔiL1
-ΔiL1 t
Ton Toff
Tsw
Fig 3.4. Current circulating through the input capacitor of the boost converter.
From Fig 3.4 the charges (QCin) circulating through Cin can be trigonometrically
calculated. Hence, as the capacitance is given by the charges circulating through the
capacitor and the desired voltage ripple (∆vCin), the capacitance of Cin is calculated as:
QCin ∆i L1
C in = = ⋅ Tsw (3.11)
∆v 8 ⋅ ∆vCin
Table 3.1 summarizes the expressions of the rms current circulating through passive
elements (determines the thermal stress), their maximum voltage stress (determines the
voltage rating) and the energy they store (it is an image of the volume), which are
calculated from Fig 3.3 and Fig 3.4.
Additionally, the semiconductor utilization factor is obtained introducing the Irms current
values and the vmax voltage values shown in Table 3.2 into Eq. (3.3):
PRated 1−δ
Uf = = (3.12)
∑all _ switches v max ⋅ I rms δ + 1−δ
TABLE 3.1
EXPRESSIONS OF THE RMS CURRENTS CIRCULATING THROUGH THE PASSIVE ELEMENTS, THEIR MAXIMUM VOLTAGE STRESS
AND THE ENERGY THEY STORE
Element Maximum stored rms current Maximum voltage

energy stress
1 ∆iL1
Cin ⋅ Cin ⋅ (Vin + ∆vCin )2 (Vin + ∆vCin )
2 3
≈ Vin
1 ∆i 2
L1 ⋅ L1 ⋅ (I in + ∆iL1 )2 I in 2
+ L1 or
2 3
≈ (Vout − Vin )
1
Cout ⋅ Cout ⋅ (Vout + ∆vCout )2 I out 2 ⋅ δ + (I in − I out )2 ⋅ (1 − δ ) (Vout + ∆vCout )
2
The utilization factor for different duty cycle values is plotted in Fig 3.5. As it can be
noticed, the utilization factor is maximized operating at low duty cycles. Although the
converter should be designed for operating with a low duty cycle and a high utilization
48
factor, the boost converter is commonly designed for duty cycles close to its maximum
value leading to a poor utilization of the semiconductors.
Utilization factor (Uf)

1
0.75
0.5
0.25
0
0 0.25 0.5 0.75 1
Duty cycle (δ)
Fig 3.5. Semiconductor utilization factor of the boost converter.
2.2.1.2 Power losses estimation
During the turn-on time interval, the transistor conducts the inductor (L1) current while
during the turn-off time interval, the inductor current circulates through the diode.
Therefore, the currents and voltages in the semiconductors are calculated from Fig 3.3a
and summarized in Table 3.2.
TABLE 3.2
EXPRESSIONS OF THE VOLTAGES/CURRENTS IN THE SEMICONDUCTORS
Current and voltage expressions Transistor S1 Diode D1
Average current (Iave) I in ⋅ δ I in ⋅ (1 − δ )
 ∆i L1 2   2 
rms current (Irms) δ ⋅  I in 2 +



(1 − δ ) ⋅  Iin 2 + ∆iL1 

 3   3 
Maximum current (imax) (Iin + ∆iL1 ) (I in + ∆i L1 )

Turn-on switched current (ion) (I in − ∆i L1 ) −
Turn-off switched current (ioff) (I in + ∆i L1 ) (I in − ∆iL1 )

Maximum voltage (vmax) (Vout + ∆vCout ) (Vout + ∆vCout )
Turn-on switched voltage (von) (Vout + ∆vCout ) −
Turn-off switched voltage (voff) (Vout − ∆vCout ) (Vout + ∆vCout )
49
As mentioned in the introduction (section 3.2), the semiconductor power losses are given
by the average conduction power losses of Eq. (3.1) and the average switching power
losses of Eq. (3.2). Therefore, from the currents summarized in Table 3.2, the average
conduction power losses of S1 and D1 are expressed respectively as:
 ∆i 2 
Pcond _ S1 = Vth ⋅ I in ⋅ δ + rd ⋅ δ ⋅  I in 2 + L1  (3.13)
 3 

 ∆i 2 
Pcond _ D1 = Vth ⋅ I in ⋅ (1 − δ ) + rd ⋅ (1 − δ ) ⋅  I in 2 + L1  (3.14)
 3 
 
where rd is the semiconductor switch on-state resistance and Vth is the semiconductor
threshold voltage.
Similarly, the average switching power losses of D1 are given as follows:
Psw _ D1 =
(Vout + ∆vCout ) ⋅ (A ⋅ (I in − ∆i L1 )2 + Boff , D1 ⋅ (I in − ∆i L1 ) + C off , D1 )
off , D1 (3.15)
Tsw ⋅ V100 FIT
where Aoff,D1, Boff,D1 and Coff,D1 are the turn-off energy loss characteristic provided by the
manufacturer for the 100FIT test voltage (V100FIT).
The average switching losses of S1 are obtained as below:
(Vout − ∆vCout )
Psw _ S1 =
Tsw ⋅ V100 FIT
(
⋅ Aoff , S1 ⋅ (I in + ∆i L1 )2 + Boff , S1 ⋅ (I in + ∆i L1 ) + C off , S1 + )
(3.16)
(Vout + ∆vCout )
+
Tsw ⋅ V100 FIT
(
⋅ Aon, S1 ⋅ (I in − ∆i L1 ) + Bon, S1 ⋅ (I in − ∆i L1 ) + C on, S1
2
)
where Aoff,S1, Boff,S1 and Coff,S1 are the turn-off energy loss characteristic provided by the
manufacturer for the 100FIT test voltage. Similarly, Aon,S1, Bon,S1 and Con,S1 are the turn-on
energy loss characteristic provided by the manufacturer.
2.2.2 Zeta
The zeta converter, illustrated in Fig 3.6, is a unidirectional step-up/down converter

suitable for applications where no galvanic isolation is required. The converter comprises
two semiconductors (a transistor and a diode) and five passive elements including the
input and output capacitors.
Iin -
C1
+ +
L2
-
Iout
+ iL2 +
+
iC1 +
+ S1
Vin Cin L1 D1 Cout Vout
- iCin iL1 - iCout
-
- -
Fig 3.6. Zeta converter.
50
The converter operates storing/transferring the energy coming from the input every
semiconductor switching period (Tsw). Thus, during the on-state of transistor S1 (Ton time
interval), the energy coming from the input and the energy stored in Cin is transferred to
L1 and the output load, while the energy stored in the capacitor C1 is transferred to L2 (Fig
3.7a). Fig 3.7b shows that when S1 is off (Toff time interval), the energy stored in L1 is
transferred to C1 and the energy stored in L2 is transferred to the output load. Meanwhile,
the energy coming from the input is stored in Cin.
C1 L2 C1 L2
+ + + Iin Iout +
S1
Iout S1
Vin Cin L1 D1 Cout Vout Vin Cin L1 D1 Cout Vout
Iin IL1
- - - -
a) b)
Fig 3.7. Currents circulating through the zeta converter a) when S1 is on and b) when
S1 is off.
In steady state, assuming a CCM operation, the voltages and currents in L1, L2 and C1 are
drawn as in Fig 3.8a, Fig 3.8b and Fig 3.8c respectively. Furthermore, the average voltage
of inductor L1 (<vL1>) and inductor L2 (<vL2>) in a switching period (Tsw) is zero:
1  Ton Tsw 
vL1 = ⋅  ∫ vL1dt + ∫ vL1dt  = 0 (3.17)
Tsw  
 0 Ton 
1  Ton Tsw 
vL 2 = ⋅  ∫ vL 2 dt + ∫ vL 2 dt  = 0 (3.18)
Tsw  
 0 Ton 
51
iL1
ΔiL1
Iin
Ton Toff
D1 Conducting
S1 Conducting
vL1
Tsw t
Vin
y=-sinx, x∊[0,2π]
π
π]
t
-VC1
a)
iL2 vC1
ΔiL2 VC1 ΔvC1
Iout
Ton Toff
D1 Conducting
Ton Toff
S1 Conducting
vL2
Tsw t iC1
Tsw t
Vin+VC1-Vout Iin
π
π] y=-sinx, x∊[0,2
[ π]
[0,2π
t t
-Vout -Iout
b) c)
Fig 3.8. Typical voltage and current waveforms in zeta converter's a) inductor L1,
b) inductor L2 and c) capacitor C1.
Thus, from Fig 3.8a and Eq. (3.17), Eq. (3.19) is obtained and similarly, from Fig 3.8b
and Eq. (3.18), Eq. (3.20) is obtained.
(1 − δ )
Vin VC1 ⋅
= (3.19)
δ
Vout (Vin + VC1 ) ⋅ δ
= (3.20)
where δ is the duty cycle of the converter (Ton/Tsw), Vin and Vout are the average input and
output voltages respectively (cf. Fig 3.6) and VC1 is the average voltage of C1.
52
The average voltage of C1 is obtained introducing Eq. (3.19) into Eq. (3.20):
VC1 = Vout (3.21)
And introducing Eq. (3.21) into Eq. (3.19), the DC voltage transfer function is obtained:
δ
Vout = Vin ⋅ (3.22)
(1 − δ )
From Eq. (3.22), the output voltage of the zeta converter can be either, higher or lower
than the input voltage (step-up/down converter).
In steady state, the average current circulating through C1 (<iC1>) in a switching period is
equal to zero, Eq. (3.23). Hence, the DC current transfer function given by Eq. (3.24) can
be obtained from Fig 3.8c and Eq. (3.23).
1  Ton Tsw 
iC1 = ⋅  ∫ iC1 dt + ∫ iC1 dt  = 0 (3.23)
Tsw  
 0 Ton 
(1 − δ )
I out = I in ⋅ (3.24)
δ
where Iin and Iout are respectively the average input and output currents (cf. Fig 3.6).
The inductances of L1 and L2 are obtained from Fig 3.8a and Fig 3.8b respectively:
∆t Vin
L1 = vL1 ⋅ = ⋅ δ ⋅ Tsw (3.25)
∆i 2 ⋅ ∆iL1
∆t Vin
L2 = vL 2 ⋅ = ⋅ δ ⋅ Tsw (3.26)
∆i 2 ⋅ ∆iL 2
where ∆iL1 and ∆iL2 are the current ripple of L1 and L2 inductors respectively.
Similarly, the capacitance of C1 is obtained from Fig 3.8c:
∆t I
C1 = iC1 ⋅ = out ⋅ δ ⋅ Tsw (3.27)
∆v 2 ⋅ ∆vC1
where ∆vC1 is the desired voltage ripple.
iCin
Iin
QCin
iCout
QCout
ΔiL2
-ΔiL2 t
Ton Toff -Iout +ΔiL1+ΔiL2 t
Tsw
-Iout -ΔiL1-ΔiL2
Ton Toff
Tsw
a) b)
Fig 3.9. Current circulating through a) the output capacitor and b) the input capacitor
of the zeta converter.
53
As illustrated in Fig 3.9a, the current ripple of the inductor L2 (∆iL2) circulates through the
output capacitor. Thus, the QCout charges circulating through Cout can be trigonometrically
calculated and therefore, the capacitance of Cout is given by :
QCout ∆i L 2
C out = = ⋅ Tsw (3.28)
∆v 8 ⋅ ∆v Cout
where ∆vCout is the half of the desired peak to peak output voltage ripple.
The current through the input capacitor (Cin) when the transistor S1 is opened (Toff time
interval) is equal to the input current (Iin). Assuming the input current is constant, the
current circulating through the input capacitor can be drawn as in Fig 3.9b. Therefore, the
input Cin capacitance is calculated from the QCin charges depicted in Fig 3.9b and the
desired input voltage ripple ∆vCin:
⋅ (1 − δ ) ⋅ Tsw
QCin I in
C in = = (3.29)
∆v 2 ⋅ ∆v Cin
From Fig 3.8 and Fig 3.9, the rms current circulating through the passive elements
(thermal stress), their maximum voltage stress (voltage rating) and the energy they store
(image of their volume) are obtained. Table 3.3 summarizes aforementioned expressions.
TABLE 3.3
Element Maximum stored rms current Maximum

energy voltage stress
1  (∆i + ∆iL 2 )2  (Vin + ∆vCin )

Cin ⋅ Cin ⋅ (Vin + ∆vCin )2 I in 2 ⋅ (1 − δ ) + δ ⋅  I out 2 + L1
 
2  3 
1 ∆iL12 (Vout + ∆vC1 )

L1 ⋅ L1 ⋅ (I in + ∆iL1 )2 I in 2 +
2 3
1
C1 ⋅ C1 ⋅ (Vout + ∆vC1 )2 δ ⋅ I out 2 + (1 − δ ) ⋅ I in 2 (Vout + ∆vC1 )
2
1 ∆iL 2 2 (Vout + ∆v Cout )
L2 ⋅ L2 ⋅ (I out + ∆iL 2 )2 I out 2 +
2 3
1 ∆iL 2
Cout ⋅ Cout ⋅ (Vout + ∆vCout )2 (Vout + ∆vCout )
2 3
Finally, from the maximum voltages (vmax) and the rms currents (Irms) shown in Table 3.4,
the semiconductor utilization factor is calculated as follows:
Uf =
PRated
=
(1 − δ ) ⋅ δ
(3.30)
54
Fig 3.10 illustrates the Eq. (3.30) for different duty cycle values. As noticed, the
maximum utilization factor is obtained when the duty cycle is equal to 0.5. Hence, from
the DC voltage transfer function of Eq. (3.22), it is concluded that the converter is
optimally designed when it operates with an input voltage equal to the output voltage.

0.18
0.13
0.09
0.04
0
0 0.25 0.5 0.75 1
Duty cycle (δ)
Fig 3.10. Semiconductor utilization factor of the zeta converter.
The semiconductors of zeta converter conduct the sum of the input current and the output
current (greyish areas of Fig 3.8a and Fig 3.8b). Thus, from Fig 3.8a and Fig 3.8b, the
currents and voltages in the semiconductors required for the power loss estimation are
obtained and summarized in Table 3.4.
Average conduction power losses of S1 and D1 are expressed respectively as:
I 2 (∆i + ∆i L 2 )2 
Pcond _ S1 = Vth ⋅ I in + rd ⋅  in + δ ⋅ L1  (3.31)
 δ 3 
 
 I  (∆i L1 + ∆i L 2 ) 
2 2
Pcond _ D1 = Vth ⋅ I out + rd ⋅ (1 − δ ) ⋅   in  +  (3.32)
 δ  3 
 
threshold voltage.
Additionally, the average switching power losses of D1 are given by:
 Vin 
 + ∆v Cin + ∆v C1 
( )   Aoff , D1 ⋅ (I in + I out − ∆i L1 − ∆i L 2 ) + 
2
 1 − δ  (3.33)
Psw _ D1 = ⋅
Tsw ⋅ V100 FIT  + B ⋅ (
 off , D1 in out I + I − ∆ i L1 − ∆i L2 ) + C 
off , D1 
55
TABLE 3.4
Current and voltage

Transistor S1 Diode D1
expressions
Average current (Iave) I in I out
rms current (Irms)

I in 2 (∆i + ∆i L 2 )2
+ δ ⋅ L1
 I  2 (∆i + ∆i )2
(1 − δ ) ⋅  in
 + L1 L2


δ 3  δ  3 
 
Maximum current (imax) (I in + I out + ∆iL1 + ∆iL 2 ) (I in + I out + ∆iL1 + ∆iL 2 )

Turn-on switched current (ion) (I in + I out − ∆i L1 − ∆i L 2 ) −
Turn-off switched current (ioff) (I in + I out + ∆i L1 + ∆i L 2 ) (I in + I out − ∆i L1 − ∆i L 2 )
 Vin   Vin 
Maximum voltage (vmax)  + ∆v C1 + ∆v Cin   + ∆v C1 + ∆v Cin 
 (1 − δ )   (1 − δ ) 
 Vin 
Turn-on switched voltage (von)  (1 − δ ) + ∆v C1 + ∆v Cin  −
 
Turn-off switched voltage (voff)  − ∆v C1 − ∆v Cin   + ∆v C1 + ∆v Cin 
 (1 − δ )   (1 − δ ) 
The average switching losses of S1 are:
 Vin 
 − ∆v C1 − ∆v Cin 
( )   Aoff , S1 ⋅ (I in + I out + ∆i L1 + ∆i L 2 ) + 
2
 1− δ +
Psw _ S1 = ⋅
Tsw ⋅ V100 FIT + B
 off , S 1 ⋅ ( I in + I out + ∆i L1 + ∆i L 2 ) + C off , S 1


(3.34)
 Vin 
 + ∆v C1 + ∆v Cin 
( )   Aon, S1 ⋅ (I in + I out − ∆i L1 − ∆i L 2 ) + 
2
 1 − δ 
+ ⋅
Tsw ⋅ V100 FIT 
 + B on , S 1 ⋅ ( I in + I out − ∆i L1 − ∆i L 2 ) + C on , S 1


manufacturer for V100FIT. Similarly, Aon,S1, Bon,S1 and Con,S1 are the turn-on energy loss
characteristic.
2.2.3 Sepic
In Fig 3.11 the sepic converter is depicted. It is a unidirectional step-up/down converter

with no galvanic isolation. The converter comprises two inductors and three capacitors.
Moreover, two semiconductors are required, a transistor and a diode.
56
Iin +
L1
-
C1
-
D1 Iout
+
+ iL1 iC1 - +
+ +
Vin Cin S1 L2 Cout Vout
- iCin - iCout
- iL2 -
+
Fig 3.11. Sepic converter.
In Fig 3.12a, when the transistor S1 is on (Ton time interval), the energy coming from the
input is stored in the inductor L1. At the same time, the energy stored in capacitor C1 is
transferred to L2 and the load is supplied by the output capacitor Cout. During the off-state
of S1 (Toff time interval), the energy coming from the input and the energy stored in L1 are
transferred to C1 and Cout (Fig 3.12b). In addition, L2 supplies the output load.
L1 C1 D1 L1 C1 D1
+ + + +
Iout Iout
Vin Cin S1 L2 Cout Vout Vin Cin S1 L2 Cout Vout
IL2
Iin Iin
- - - -
a) b)
Fig 3.12. Currents circulating through the sepic converter a) when S1 is on and b)
when S1 is off.
As a consequence, the steady state voltages and currents in L1, L2, C1 and Cout are drawn
respectively as in Fig 3.13a, Fig 3.13b, Fig 3.13c and Fig 3.13d if a CCM operation is
assumed.
As discussed for previous converters, the DC voltage/current transfer functions are
obtained from the analysis of the voltage/current waveforms in the passive elements. On
the one hand, the average voltage drop in the inductors L1 and L2 is zero. Therefore, from
Fig 3.13a and Eq. (3.17), Eq. (3.35) is obtained. Similarly, from Fig 3.13b and Eq. (3.18),
Eq. (3.36) is obtained.
Vin = (Vout + VC1 ) ⋅ (1 − δ ) (3.35)
δ
Vout = VC1 ⋅ (3.36)
(1 − δ )
57
iL1 iL2
ΔiL1 ΔiL2
Iin IL2
Ton Toff Ton Toff

D1 Conducting D1 Conducting
S1 Conducting S1 Conducting
vL1
Tsw t vL2 Tsw t
Vin VC1
π
π] y=-sinx, x∊[0,2π]
π
π]
t t
Vin-VC1-Vout -Vout
a) b)
vC1 vCout
ΔvC1 ΔvCout
VC1 Vout
Ton Toff Ton Toff
iC1
Tsw t iCout
Tsw t
Iin Iin+IL2-Iout
π
π] [ π]
y=-sinx, x∊[0,2
[0,2π
t t
-IL2 -Iout
c) d)
Fig 3.13. Typical voltage and current waveforms in sepic converter's a) inductor L1, b)
inductor L2, c) capacitor C1 and d) capacitor Cout.
The average voltage of C1 is obtained introducing Eq. (3.36) into Eq. (3.35):
VC1 = Vin (3.37)
Thus, the DC voltage transfer function is obtained introducing Eq. (3.37) into Eq. (3.36):
δ
V= Vin ⋅ (3.38)
out
(1 − δ )
From Eq. (3.38), if the duty cycle is lower than 0.5, Vout is greater than Vin. Conversely, if
the duty cycle is higher than 0.5, Vout is lower than Vin. Thus, sepic converter is considered
a step-up/down converter.
58
On the other hand, the current expressions given by Eq. (3.39) and Eq. (3.40) are obtained
respectively from Fig 3.13c and Fig 3.13d considering the average current circulating
through C1 in a switching period is equal to zero:
δ
I in = I L 2 ⋅ (3.39)
(1 − δ )
I out = (I in + I L 2 ) ⋅ (1 − δ ) (3.40)
where Iin and Iout are the average input and output currents respectively (cf. Fig 3.11) and
IL2 is the average current circulating through L2. Introducing Eq. (3.39) into Eq. (3.40) the
average current circulating through L2 is equal to the output current:
I L 2 = I out (3.41)
From Eq. (3.39) and Eq. (3.41), the DC current transfer function is given as follows:
(1 − δ )
I out = I in ⋅ (3.42)
δ
The inductance values of L1 and L2 are obtained from the analysis of the voltage and
currents of Fig 3.13a and Fig 3.13b during Ton time interval:
∆t Vin
L1 = vL1 ⋅ = ⋅ δ ⋅ Tsw (3.43)
∆i 2 ⋅ ∆iL1
∆t Vin
L2 = vL 2 ⋅ = ⋅ δ ⋅ Tsw (3.44)
∆i 2 ⋅ ∆iL 2
where ∆iL1 and ∆iL2 are respectively the ripple of the currents circulating through L1 and
L2.
Similarly, C1 and Cout capacitances are obtained from Fig 3.13c and Fig 3.13d:
∆t I out
C1 = iC1 ⋅ = ⋅ δ ⋅ Tsw (3.45)
∆v 2 ⋅ ∆vC1
∆t I out
Cout = iCout ⋅ = ⋅ δ ⋅ Tsw (3.46)
∆v 2 ⋅ ∆vCout
where ∆vCout and ∆vC1 are respectively the desired voltage ripple in the output and C1
capacitors.
iCin
QCin
ΔiL1
-ΔiL1 t
Ton Toff
Tsw
Fig 3.14. Current circulating through the input capacitor of the sepic converter.
59
In order to calculate the input DC bus capacitance, the current coming from the input is
considered constant (Iin). As a consequence, the current circulating through Cin is equal to
the current ripple ∆iL1 and therefore, the QCin charges circulating through the input
capacitor can be trigonometrically calculated from Fig 3.14. So, the capacitance of Cin is
given by:
QCin ∆i L1
C in = = ⋅ Tsw (3.47)
∆v 8 ⋅ ∆v Cin
where ∆vCin is the half of the desired peak to peak input voltage ripple.
Table 3.5 summarizes the expressions of the rms current circulating through the passive
elements, their maximum voltage and the energy they store. The expressions are obtained
from Fig 3.13 and Fig 3.14.
TABLE 3.5

energy stress
1 ∆i L1
2 3
1 ∆iL12 ≈ (Vout + ∆vCout + ∆vC1 )

L1 ⋅ L1 ⋅ (I in + ∆iL1 )2 I in 2 +
2 3
C1
1
⋅ C1 ⋅ (Vin + ∆vC1 )2 I in ⋅
(1 − δ ) (Vin + ∆vC1 )
2 δ
1 ∆iL 2 2 (Vout + ∆v Cout )
L2 ⋅ L2 ⋅ (I out + ∆iL 2 )2 I out 2 +
2 3
1 δ
Cout ⋅ Cout ⋅ (Vout + ∆vCout )2 I out ⋅ (Vout + ∆vCout )
2 (1 − δ )
The semiconductor utilization factor is given as:
Uf =
PRated
=
(1 − δ ) ⋅ δ
(3.48)
As this semiconductor utilization factor is equal to that presented in Eq. (3.30) and Fig
3.10 for zeta converter, same conclusions are obtained. The maximum utilization factor
and in consequence, its optimal design, is given by an operation with a duty cycle value
of 0.5. In other words, if the input voltage is equal to the output voltage, the
semiconductor utilization factor is optimum.
60
For the semiconductor power loss estimation, the currents and voltages in the
semiconductors must be obtained. As the semiconductors conduct the input as well as the
output current, the expressions are obtained from the sum of the currents depicted in Fig
3.13a and Fig 3.13b. Table 3.6 summarizes the current and voltage expressions required
for the power loss estimation.
TABLE 3.6
Current and voltage

expressions
 I  2 (∆i + ∆i )2
rms current (Irms)
I in 2 (∆i + ∆iL 2 )2
+ δ ⋅ L1 (1 − δ ) ⋅  in
 + L1 L2


δ 3  δ  3 
 

Turn-on switched current (ion) (I in + I out − ∆iL1 − ∆iL 2 ) −
Turn-off switched current (ioff) (I in + I out + ∆iL1 + ∆iL 2 ) (I in + I out − ∆iL1 − ∆iL 2 )
Maximum voltage (vmax)  + ∆v C1 + ∆v Cout   + ∆vC1 + ∆vCout 
 (1 − δ )   (1 − δ ) 
 Vin 
Turn-on switched voltage (von)  + ∆vC1 + ∆vCout  −
 (1 − δ ) 
Turn-off switched voltage (voff)  − ∆vC1 − ∆vCout   + ∆vC1 + ∆vCout 
 (1 − δ )   (1 − δ ) 
Therefore, average conduction power losses of S1 and D1 are given respectively as:
I 2 (∆i + ∆i L 2 )2 
 δ 3 
 
 I  (∆i L1 + ∆i L 2 ) 
2 2
 δ  3 
 
threshold voltage.
Additionally, the average switching power losses of D1 are expressed as:
 Vin 
 + ∆v C1 + ∆v Cout 
( )   Aoff , D1 ⋅ (I in + I out − ∆i L1 − ∆i L 2 ) + 
2
 1 − δ  (3.51)
Psw _ D1 = ⋅
 off , D1 ⋅ (I in + I out − ∆i L1 − ∆i L 2 ) + C off , D1 
Tsw ⋅ V100 FIT + B 
61
Finally, the average switching losses of S1 are obtained as below:
 Vin 
 − ∆v C1 − ∆v Cout 
( )   Aoff , S1 ⋅ (I in + I out + ∆i L1 + ∆i L 2 ) + 
2
 1 − δ +
Psw _ S1 = ⋅
Tsw ⋅ V100 FIT + B ⋅ (
 off , S1 in out I + I + ∆ i L1 + ∆i L2 ) + C 
off , S1 
(3.52)
 Vin 
 + ∆v C1 + ∆v Cout 
 (1 − δ )   Aon, S1 ⋅ (I in + I out − ∆i L1 − ∆i L 2 ) + 
2
+ ⋅ 
Tsw ⋅ V100 FIT  + Bon, S1 ⋅ (I in + I out − ∆i L1 − ∆i L 2 ) + C on, S1 
 
manufacturer for V100FIT and Aon,S1, Bon,S1 and Con,S1 are the turn-on energy loss
characteristic.
2.2.4 Isolated-sepic
If the output side inductor (L2) of the sepic converter is substituted by a medium
frequency transformer, the isolated-sepic converter is obtained, cf. Fig 3.15. The power
transference in this step-up/down converter is unidirectional. The leakage inductance of
the MFT has been neglected in the analysis presented hereafter.
Iin L1 C1 D1 Iout
+ - -
+
+ iL1 n1 : n2 +
iC1 -
+ +
Vin Cin S1 Lm Cout Vout
- iCin - iCout
- iLm -
+
Fig 3.15. Isolated-sepic converter.
When transistor S1 is on (Ton time interval), the energy coming from the input is stored in
L1 inductor while the energy stored in the capacitor C1 is transferred to the magnetizing
inductance of the transformer (Lm). Additionally, Fig 3.16a shows that during this time
interval, the output capacitor Cout supplies the output load. When S1 is off (Toff time
interval), the energy coming from the input and the energy stored in L1 are transferred to
C1 and Cout as illustrated in Fig 3.16b. At the same time, Lm supplies the output load.
Assuming a CCM operation, Fig 3.17 illustrates the steady state voltage and current
waveforms in the passive elements of the converter. From the voltage waveforms
depicted in Fig 3.17a and Fig 3.17b, the voltage relations of the converter are obtained:
 
Vin = Vout ⋅ 1 + VC1  ⋅ (1 − δ )
n
(3.53)
 n2 
62
δ n
Vout = VC1 ⋅ ⋅ 2 (3.54)
(1 − δ ) n1
where n1 and n2 are respectively primary and secondary windings' number of turns, δ is
the duty cycle of the converter (Ton/Tsw), Vin and Vout are the average input and output
voltages respectively (cf. Fig 3.15) and VC1 is the mean voltage value of C1.
L1 C1 D1
+ n1 : n2 +
Iout
Iin ILm
- -
a)
L1 C1 D1
+ n1 : n2 +
Iout
Iin
- -
ILm
b)
Fig 3.16. Currents circulating through the isolated-sepic converter a) when S1 is on
and b) when S1 is off.
From the voltage relations of Eq. (3.53) and Eq. (3.54), the average voltage of C1 is equal
to the input voltage:
VC1 = Vin (3.55)
Hence, the DC voltage transfer function is obtained rewriting Eq. (3.54):
δ n2
Vout = Vin ⋅ ⋅ (3.56)
(1 − δ ) n1
The DC voltage transfer function of the previously discussed step-up/down converters

depends only on the duty cycle, while that of the isolated-sepic depends also on the turn
ratio of the MFT. This fact adds a degree of freedom for the design of the isolated-sepic
(the voltage elevation can be fixed by the transformer or by the duty cycle).
The relations between the currents in the converter are obtained from the steady state
analysis of the waveforms of Fig 3.17c and Fig 3.17d:
δ
I in = I Lm ⋅ (3.57)
(1 − δ )
I out = (I in + I Lm ) ⋅ (1 − δ ) ⋅
n1
(3.58)
n2
where Iin and Iout are the average input and output currents respectively (cf. Fig 3.15) and
ILm is the average current circulating through Lm.
63
iL1 iLm
ΔiL1 ΔiLm
Iin ILm
Ton Toff Ton Toff
vL1
Tsw t Tsw t
vLm
Vin
VC1
π
π]
t y=-sinx, x∊[0,2π]
π
π]
t
n1
Vin-VC1- V
n2 out n1
- V
n2 out
a) b)
vC1 vCout
ΔvC1 ΔvCout
VC1 Vout
Ton Toff Ton Toff
iC1
Tsw t iCout
Tsw t
n1
Iin (I +I )-I
n2 in Lm out
π
π
π]
t t
-ILm -Iout
c) d)
Fig 3.17. Typical voltage and current waveforms in isolated-sepic converter's a)
inductor L1, b) magnetizing inductance Lm, c) capacitor C1 and d) output capacitor
Cout.
Introducing Eq. (3.57) into Eq. (3.58) the average current circulating through Lm is
obtained:
n2
I Lm I out ⋅
= (3.59)
n1
From Fig 3.17b and Eq. (3.59), the magnetization of the MFT is unidirectional leading to
a poor utilization of the transformer.
64
The transfer function of the DC current is obtained introducing Eq. (3.59) into Eq. (3.57):
I out = I in ⋅
(1 − δ ) ⋅ n1
(3.60)
δ n2
Furthermore, the values of L1 and Lm are obtained from the analysis of the waveforms of
Fig 3.17a and Fig 3.17b during Ton time interval:
∆t Vin
L1 = vL1 ⋅ = ⋅ δ ⋅ Tsw (3.61)
∆i 2 ⋅ ∆iL1
∆t Vin
Lm = vLm ⋅ = ⋅ δ ⋅ Tsw (3.62)
∆i 2 ⋅ ∆iLm
where ∆iL1 and ∆iLm are respectively the current ripple in L1 and Lm.
Similarly, the capacitive values of C1 and Cout are obtained from Fig 3.17c and Fig 3.17d:
∆t I n
C1 = iC1 ⋅ = out ⋅ 2 ⋅ δ ⋅ Tsw (3.63)
∆v 2 ⋅ ∆vC1 n1
∆t I out
Cout = iCout ⋅ = ⋅ δ ⋅ Tsw (3.64)
∆v 2 ⋅ ∆vCout
where ∆vCout and ∆vC1 are the desired voltage ripple in Cout and C1 capacitors.
The input DC bus capacitance is calculated following the same criterion than for the sepic
converter (assuming a constant input current Iin, Fig 3.14). Hence, it is given as:
QCin ∆i L1
C in = = ⋅ Tsw (3.65)
∆v 8 ⋅ ∆v Cin
where QCin are the charges circulating through the input capacitor and ∆vCin is the half of
the desired peak to peak input voltage ripple.
From Fig 3.17, Table 3.7 summarizes the expressions of the rms current circulating
through passive elements, their maximum voltage stress and the energy they store.
Comparing Table 3.7 and Table 3.5, it can be observed that the voltage stress of the
inductances of isolated-sepic converter is smaller than that of the inductances of the sepic
converter if n2>n1 is considered. However, the semiconductor utilization factor is equal
for both converters:
Uf =
PRated
=
(1 − δ ) ⋅ δ
(3.66)
Thus, similarly to zeta and sepic converters, the maximum utilization factor is given by a
duty cycle value of 0.5 (Fig 3.10). Hence, the converter must be designed to operate with
duty cycles close to 0.5 (optimal n2/n1 turn ratio must be chosen for each application, Eq.
(3.56)).
65
TABLE 3.7
Element Maximum stored energy rms current Maximum voltage

stress
1 ∆i L1
2 3
1 ∆iL12 (Vout + ∆vCout ) ⋅ n1

L1 ⋅ L1 ⋅ (I in + ∆iL1 )2 I in 2 +
2 3 n2
C1
1
⋅ C1 ⋅ (Vin + ∆vC1 )2 I in ⋅
(1 − δ ) (Vin + ∆vC1 )
2 δ
2 2
1  n   n2  ∆i 2 (Vout + ∆vCout ) ⋅ n1
Lm ⋅ Lm ⋅  I out ⋅ 2 + ∆iLm   ⋅ I out  + Lm
2 n  3 n2
 n1   1 
1 δ
2 (1 − δ )
The semiconductors of the isolated-sepic converter conduct the sum of the input and
output currents as depicted in Fig 3.17a and Fig 3.17b. Therefore, from those figures, the
currents circulating through S1 and D1, and their voltage drop are calculated and
summarized in Table 3.8.
The average conduction power losses of S1 and D1 are obtained from Table 3.8 and Eq.
(3.1):
I 2 (∆i + ∆i Lm )2 
 δ 3 
 
 (∆i L1 + ∆i Lm )
2
n   I 2 2 
Pcond _ D1 = Vth ⋅ I out + rd ⋅ (1 − δ ) ⋅  1  ⋅   in  +  (3.68)
 n2   δ  3 
 
threshold voltage.
66
TABLE 3.8
Current and
voltage Transistor S1 Diode D1
expressions
Average current
I in I out
(Iave)
(∆i + ∆i Lm )2
2
I in 2     I  2 (∆i + ∆i )2 
rms current (Irms) + δ ⋅ L1 (1 − δ ) ⋅  n1 ⋅   in  + L1 Lm 
δ 3  n 2    δ  3 

Maximum current    
 (I in + ∆i L1 + ∆i Lm ) ⋅ 1 + I out 
n n
 I in + I out ⋅ 2 + ∆i L1 + ∆i Lm 
(imax)  n 1   n 2 
Turn-on switched  n 
 I in + I out ⋅ 2 − ∆i L1 − ∆i Lm  −
current (ion)  n 1 
Turn-off switched    
 (I in − ∆i L1 − ∆i Lm ) ⋅ 1 + I out 
n n
 I in + I out ⋅ 2 + ∆i L1 + ∆i Lm 
current (ioff)  n 1   n 2 
Maximum voltage  Vin n    Vin  n2 
 + ∆v C1 + 1 ⋅ ∆v Cout  
  (1 − δ ) + ∆v C1  ⋅ n + ∆v Cout

(vmax)  (1 − δ ) n 2    1


Turn-on switched  Vin n 
 + ∆v C1 + 1 ⋅ ∆v Cout  −
voltage (von)  (1 − δ ) n 2 
Turn-off switched  Vin n    Vin  n2 
 − ∆v C1 − 1 ⋅ ∆v Cout  
  (1 − δ ) + ∆v C1  ⋅ n + ∆v Cout

voltage (voff)  (1 − δ ) n 2    1


From the currents and voltages given by Table 3.8 and Eq. (3.2), the average switching
power losses of D1 are calculated:
  Vin  n2 
 
  (1 − δ ) + ∆v C1  ⋅ n + ∆v Cout   
2
   
⋅ Aoff , D1 ⋅  (I in − ∆i L1 − ∆i Lm ) ⋅ + I out  +
1 n1
Psw _ D1 =
Tsw ⋅ V100 FIT  n2 
(3.69)
  Vin  n2 
     
  (1 − δ ) + ∆vC1  ⋅ n + ∆vCout   B 
(Iin − ∆iL1 − ∆iLm ) ⋅ n1 + I out  + 
   1  off , D1 ⋅ 

+ ⋅  n2  
Tsw ⋅ V100 FIT  
 + Coff , D1 
67
Moreover, the average switching losses of S1 are obtained as below:
 Vin n 
 − ∆v C1 − 1 ⋅ ∆v Cout 
 (1 − δ )
2
n2   n 
Psw _ S1 = ⋅ Aoff , S1 ⋅  I in + I out ⋅ 2 + ∆i L1 + ∆i Lm  +
Tsw ⋅ V100 FIT  n1 
 Vin n 
 − ∆v C1 − 1 ⋅ ∆v Cout 
 (1 − δ ) n2    n  
+ ⋅ Boff , S1 ⋅  I in + I out ⋅ 2 + ∆i L1 + ∆i Lm  + C off , S1  +
Tsw ⋅ V100 FIT  
  n1  
(3.70)
 Vin n 
 + ∆v C1 + 1 ⋅ ∆v Cout 
 (1 − δ ) n 2   n 
2
+ ⋅ Aon, S1 ⋅  I in + I out ⋅ 2 − ∆i L1 − ∆i Lm  +
Tsw ⋅ V100 FIT  n1 
 Vin n 
 + ∆v C1 + 1 ⋅ ∆v Cout 
 (1 − δ ) n 2    n  
+ ⋅ Bon, S1 ⋅  I in + I out ⋅ 2 − ∆i L1 − ∆i Lm  + C on, S1 
Tsw ⋅ V100 FIT  
  n1  
characteristic.
Finally, comparing Table 3.6 to Table 3.8, it is noticed that considering n2 greater than n1,
the voltages switched by S1 in the isolated-sepic converter are slightly smaller than that in
the sepic converter. Additionally, the diode of the isolated-sepic converter switches less
current than the diode of the sepic converter. Conversely, the transistor S1 of the latter
switches less current than that transistor in the isolated-sepic converter.
2.2.5 Ćuk
The ćuk converter shown in Fig 3.18 is a unidirectional step-up/down converter with no
galvanic isolation capability. The converter is composed of a transistor (S1), a diode (D1),
two inductors (L1, L2) and three capacitors (Cin, C1, Cout). As it can be observed, the
polarities of the input and output voltages are inverted.
Iin +
L1
-
C1
-
L2
+
-
+
+ iL1 iC1 iL2 -

+ - iCout
Vin Cin S1 D1 Cout Vout
- iCin +
- Iout +
Fig 3.18. Ćuk converter.
The converter operates transferring the energy coming from the input to L1, C1, L2 and to
the output. Thus, when transistor S1 is on (Ton time interval), the energy coming from the
68
input is stored in the inductor L1 while the energy stored in the capacitor C1 is transferred
to L2 and the load (Fig 3.19a). As shown in Fig 3.19b, when S1 is off (Toff time interval),
the energy coming from the input and the energy stored in L1 are transferred to C1. The
output load is supplied by the inductor L2.
L1 C1 L2 L1 C1 L2
+ - + -
Vin Cin S1 D1 Cout Vout Vin Cin S1 D1 Cout Vout

Iin Iout Iin Iout
- + - +
a) b)
Fig 3.19. Currents circulating through the ćuk converter a) when S1 is on and b) when
S1 is off.
Fig 3.20 shows the steady state voltage and current waveforms in L1, L2 and C1 and Cout
under a CCM operation. The voltage relations between the input, C1 and the output are
obtained from Fig 3.20a and Fig 3.20b assuming the average voltage drop in the inductors
is zero (Eq. (3.17), Eq. (3.18)):
Vin = VC1 ⋅ (1 − δ ) (3.71)
Vout = VC1 ⋅ δ (3.72)
Thus, the DC voltage transfer function is obtained from above voltage relations:
δ
Vout = Vin ⋅ (3.73)
(1 − δ )
The step-up/down nature of the ćuk converter is observed in the DC transfer function
equation, if δ is greater than 0.5, Vout is greater than Vin, while if δ is lower than 0.5, Vout is
lower than Vin.
Introducing the DC voltage transfer function into Eq. (3.71), the average voltage of C1 is:
Vin
VC1 = = Vin + Vout (3.74)
(1 − δ )
Similarly, the DC current transfer function is obtained from Fig 3.20c considering the
average current circulating through C1 is equal to zero (Eq. (3.23)):
(1 − δ )
I out = I in ⋅ (3.75)
δ
Moreover, from Fig 3.20a and Fig 3.20b, the expressions to calculate the inductances of
L1 and L2 are obtained:
∆t Vin
L1 = vL1 ⋅ = ⋅ δ ⋅ Tsw (3.76)
∆i 2 ⋅ ∆iL1
69
∆t Vin
L2 vL 2 ⋅
= = ⋅ δ ⋅ Tsw (3.77)
∆i 2 ⋅ ∆iL 2
where ∆iL1 is the current ripple through L1 and ∆iL2 is the current ripple through L2.
iL1
ΔiL1
Iin
Ton Toff
D1 Conducting
S1 Conducting
vL1
Tsw t
Vin
π
π]
t
Vin-VC1
a)
iL2 vC1
ΔiL2 ΔvC1
Iout VC1
Ton Toff
D1 Conducting
vL2
Tsw t iC1
Tsw t
VC1-Vout Iin
π
π
π]
t t
-Vout - Iout
b) c)
Fig 3.20. Typical voltage and current waveforms in ćuk converter's a) inductor L1, b)
inductor L2 and c) capacitor C1.
The expression to calculate the capacitance of C1 is obtained from Fig 3.20c:
∆t I
C1 iC1 ⋅
= = out ⋅ δ ⋅ Tsw (3.78)
∆v 2 ⋅ ∆vC1
where ∆vC1 is the desired voltage ripple in C1.
70
iCin iCout
QCin QCout
ΔiL1 ΔiL2
-ΔiL1 t -ΔiL2 t
Ton Toff Ton Toff
Tsw Tsw
a) b)
Fig 3.21. Currents circulating through a) the input capacitor and b) the output
capacitor of the ćuk converter.
For calculating the capacitance values of Cin and Cout, the input current Iin and the output
current Iout are assumed to be constant. Thus, the currents circulating through them can be
drawn as in Fig 3.21. As a consequence, Cin and Cout capacitances are obtained by
calculating the charges circulating through them (grey coloured in Fig 3.21a and Fig
3.21b):
QCin ∆i L1
C in = = ⋅ Tsw (3.79)
∆v 8 ⋅ ∆v Cin
QCout ∆i L 2
C out = = ⋅ Tsw (3.80)
where ∆vCin and ∆vCout are the half of the desired peak to peak voltage ripple in the input
capacitor and the output capacitor respectively.
In addition, from Fig 3.20 and Fig 3.21, Table 3.9 summarizes the main characteristics of
the passive elements.
TABLE 3.9

energy stress
1 ∆i L1
2 3
1 ∆iL12 (Vout + ∆v C1 )
L1 ⋅ L1 ⋅ (I in + ∆iL1 )2 I in 2 +
2 3
C1
1
⋅ C1 ⋅ (Vin + Vout + ∆vC1 )2 I in ⋅
(1 − δ ) (Vin + Vout + ∆vC1 )
2 δ
1 ∆iL 2 2 (Vout + ∆vCout )
L2 ⋅ L2 ⋅ (I out + ∆iL 2 )2 I out 2 +
2 3
1 ∆iL 2
2 3
71
Finally, the semiconductor utilization factor is calculated from the rms current and vmax
voltage expressions in Table 3.10 and Eq. (3.3):
Uf =
PRated
=
(1 − δ ) ⋅ δ
(3.81)
Again, the semiconductor utilization factor of this converter is the same as that of the zeta
converter (which is drawn in Fig 3.10) and in consequence, same conclusions are
obtained. The converter must be designed to operate with duty cycles close to 0.5 if the
maximum semiconductor utilization is desired.
The semiconductor power losses are given by Eq. (3.1) and Eq. (3.2). Therefore, the
currents and voltages in the semiconductors must be calculated. Obtained from the grey
coloured areas of Fig 3.20a and Fig 3.20b, Table 3.10 summarizes the required current
and voltage expressions for the power losses estimation.
TABLE 3.10
Current and voltage

expressions
 I  2 (∆i + ∆i )2
rms current (Irms)
I in 2 (∆i + ∆iL 2 )2
+ δ ⋅ L1 (1 − δ ) ⋅  in
 + L1 L2


δ 3  δ  3 
 

Turn-on switched current (ion) (I in + I out − ∆iL1 − ∆iL 2 ) −
Turn-off switched current (ioff) (I in + I out + ∆iL1 + ∆iL 2 ) (I in + I out − ∆iL1 − ∆iL 2 )
Maximum voltage (vmax)  + ∆v C1   + ∆v C1 
 (1 − δ )   (1 − δ ) 
 Vin 
Turn-on switched voltage (von)  + ∆vC1  −
 (1 − δ ) 
Turn-off switched voltage (voff)  − ∆vC1   + ∆vC1 
 (1 − δ )   (1 − δ ) 
Therefore, introducing into Eq. (3.1) the current expressions of Table 3.10, average
conduction power losses of S1 and D1 are given respectively as:
I 2 (∆i + ∆i L 2 )2 
 δ 3 
 
72
 I  (∆i L1 + ∆i L 2 ) 
2 2
 δ  3 
 
threshold voltage.
In addition, introducing into Eq. (3.2) the current and voltage expressions of Table 3.10,
the average switching power losses of D1 are expressed as:
 Vin 
 + ∆vC1  
( )  ⋅  Aoff , D1 ⋅ (I in + I out − ∆iL1 − ∆iL 2 ) +
1 − δ
2  (3.84)
Psw _ D1 =  
Tsw ⋅ V100 FIT + B ⋅
 off , D1 in out( I + I − ∆iL1 − ∆ iL2 ) + C 
off , D1 
Similarly, the average switching losses of S1 are obtained:
 Vin 
 − ∆vC1  
(1 − δ )  ⋅  Aoff , S1 ⋅ (I in + I out + ∆iL1 + ∆iL 2 ) +
2 
Psw _ S1 =  +
Tsw ⋅ V100 FIT + B ⋅
 off , S1 in out( I + I + ∆iL1 + ∆ iL2 ) + C 
off , S1 
(3.85)
 Vin 
 (1 − δ ) + ∆vC1   A
 ⋅  on, S1 ⋅ (I in + I out − ∆iL1 − ∆iL 2 ) + 
2
+ 
Tsw ⋅ V100 FIT 
 + Bon , S 1 ⋅ ( I in + I out − ∆iL1 − ∆iL2 ) + C 
on , S 1 
characteristic.
2.2.6 Isolated-ćuk
Substituting ćuk converter's L2 inductor by a medium frequency transformer, the isolated-

ćuk converter shown in Fig 3.22 is obtained, thereby providing galvanic isolation. As
noticed in Fig 3.22, the converter is unidirectional and comprises two inductors (L1, L2),
four capacitors (Cin, C1, C2, Cout), a medium frequency transformer (the leakage
inductance has been neglected in this analysis), a transistor (S1) and a diode (D1). Unlike
the ćuk converter, the output voltage is not inverted.
Iin +
L1
-
C1
-
C2
+
L2
-
Iout
-
+
+
n1 : n2 +
iL1 iC1 - iC2 iL2
+ iLm +
Vin Cin S1 Lm D1 Cout Vout
- -
iCin iCout
+
- -
Fig 3.22. Isolated-ćuk converter.
73
The operation of the converter is dependent to the transistor state. Thus, during S1
transistor's on-state illustrated in Fig 3.23a (Ton time interval), the energy coming from the
input is stored in the inductor L1 while the energy stored in the capacitors C1 and C2 is
transferred to L2 and the load (Fig 3.19a). When S1 is off (Toff time interval), the energy
coming from the input and the energy stored in L1 are transferred to C1 and C2 while L2
supplies the load (Fig 3.23b).
L1 C1 C2 L2
+
n1 : n2 +
Iout
Vin Cin S1 Lm D1 Cout Vout
Iin
- n2 -
n1 Iout
a)
L1 C1 C2 L2
+
n1 : n2 +
Iout
Vin Cin S1 Lm n1 D1 Cout Vout
Iin n2 Iin
- -
b)
Fig 3.23. Currents circulating through the isolated-ćuk converter a) when S1 is on and
b) when S1 is off.
Under a CCM operation, the steady state voltage and current waveforms are drawn as in
Fig 3.24. The relation between the input/output voltages and the voltages of C1 and C2 are
obtained from the steady state analysis of the inductors. Thus, from Fig 3.24a, Fig 3.24b
and Fig 3.24c, the following voltage relations are obtained:
 
Vin = VC 2 ⋅ 1 + VC1  ⋅ (1 − δ )
n
(3.86)
 n2 
n1 (1 − δ )
VC1 = VC 2 ⋅ ⋅ (3.87)
n2 δ
 n 
Vout = VC1 ⋅ 2 + VC 2  ⋅ δ (3.88)
 n1 
where n1 and n2 are the number of turns of primary and secondary windings respectively,
δ is the duty cycle (Ton/Tsw), Vin and Vout are the average input and output voltages
respectively (cf. Fig 3.22), VC1 is the average voltage of C1 and VC2 is the average voltage
of C2.
74
iL1 iL2
ΔiL1 ΔiL2
Iin Iout
Ton Toff Ton Toff

Tsw t vL2
Tsw t
vL1
n2
V +V -V
Vin n1 C1 C2 out
π
π
π]
t t
n1 -Vout
Vin-VC1- V
n2 C2
a) b)
iLm S1 Conducting
D1 Conducting
ΔiLm
Tsw
t
Ton Toff
vLm
VC1
π
π]
t
n1
- V
n2 C2
c)
vC1 vC2
ΔvC1 ΔvC2
VC1 VC2
Ton Toff Ton Toff
iC1
Tsw t iC2
Tsw t
n1
Iin I
n2 in
π
π] y=-sinx, x∊[0,2
[ π]
[0,2π
t t
n2
- I - Iout
n1 out
d) e)
Fig 3.24. Typical voltage and current waveforms in isolated-ćuk converter's a) inductor
L1, b) inductor L2, c) magnetizing inductance Lm, d) capacitor C1 and e) capacitor C2.
75
From the latter equations, VC1 and VC2 voltages and the DC voltage transfer function are
calculated. The DC transfer function shows that isolated-ćuk converter's step-up/down
nature depends on two terms, the duty cycle and the turn ratio of the MFT (n2/n1), which
adds a degree of freedom for the design (the voltage elevation can be fixed by the
transformer or by the duty cycle).
VC1 = Vin (3.89)
VC 2 = Vout (3.90)
δ n2
Vout = Vin ⋅ ⋅ (3.91)
(1 − δ ) n1
The DC current transfer function is obtained from the steady state analysis of the
waveforms in the capacitors shown in Fig 3.24d and Fig 3.24e:
I out = I in ⋅
(1 − δ ) ⋅ n1
(3.92)
δ n2
Additionally, Fig 3.24c shows the current circulating through the magnetizing inductance
of the MFT is alternating, which means the magnetization of the transformer is
bidirectional and in consequence, its utilization is good.
For calculating L1 and L2 inductances, the Ton time interval shown in Fig 3.24a, Fig 3.24b
and Fig 3.24c has been analyzed:
∆t Vin
L1 = vL1 ⋅ = ⋅ δ ⋅ Tsw (3.93)
∆i 2 ⋅ ∆iL1
∆t Vin n
L2 = vL 2 ⋅ = ⋅ 2 ⋅ δ ⋅ Tsw (3.94)
∆i 2 ⋅ ∆iL 2 n1
∆t Vin
Lm = vLm ⋅ = ⋅ δ ⋅ Tsw (3.95)
∆i 2 ⋅ ∆iLm
where ∆iL1, ∆iL2 and ∆iLm are the current ripple through L1 , L2 and Lm respectively.
Similarly, the capacitances of C1 and C2 are obtained from the waveforms of Fig 3.24d
and Fig 3.24e:
∆t I n
C1 = iC1 ⋅ = out ⋅ 2 ⋅ δ ⋅ Tsw (3.96)
∆v 2 ⋅ ∆vC1 n1
∆t I out
C2 = iC 2 ⋅ = ⋅ δ ⋅ Tsw (3.97)
∆v 2 ⋅ ∆vC 2
where ∆vC1 and ∆vC2 are the desired voltage ripple in C1 and C2 respectively.
Cin and Cout capacitances have been calculated assuming the input current Iin and the
output current Iout constant, Eq. (3.98) and (3.99). In consequence, the currents circulating
through the capacitors are given by the ripple in L1 and L2 as depicted in Fig 3.21.
76
QCin ∆i L1
C in = = ⋅ Tsw (3.98)
∆v 8 ⋅ ∆v Cin
QCout ∆i L 2
C out = = ⋅ Tsw (3.99)
capacitor and the output capacitor respectively.
The main characteristics of the passive elements previously discussed are summarized in
Table 3.11.
TABLE 3.11

energy stress
1 ∆i L1
2 3
1 ∆iL12 ∆v C1 + (Vout + ∆v C 2 ) ⋅
n1
L1 ⋅ L1 ⋅ (I in + ∆iL1 )2 I in 2 +
2 3 n2
C1
1
⋅ C1 ⋅ (Vin + ∆v C1 )2 I in ⋅
(1 − δ ) (Vin + ∆vC1 )
2 δ
1 ∆i Lm
Lm ⋅ Lm ⋅ ∆i Lm 2 (Vout + ∆v C 2 ) ⋅
n1
2 3 n2
1 δ
C2 ⋅ C 2 ⋅ (Vout + ∆vC 2 )2 I out ⋅ (Vout + ∆v C 2 )
2 (1 − δ )
1 ∆iL 2 2 (Vout + ∆vCout )
L2 ⋅ L2 ⋅ (I out + ∆iL 2 )2 I out 2 +
2 3
1 ∆iL 2
2 3
At last, the semiconductor utilization factor Uf has been calculated:
Uf =
PRated
=
(1 − δ ) ⋅ δ
(3.100)
As this utilization factor is equal to those of previously discussed step-up/down type

converters, the optimal design point is given by δ=0.5 (graphically represented in Fig 3.10
for the zeta converter).
If the power losses are estimated by Eq. (3.1) and Eq. (3.2), the currents circulating
through the semiconductors and the voltages they commutate must be calculated. The
77
currents conducted by transistor S1 and diode D1 are illustrated in Fig 3.24a, Fig 3.24b
and Fig 3.24c. From those figures, the expressions summarized in Table 3.12 are
obtained.
TABLE 3.12
Current and
voltage Transistor S1 Diode D1
expressions
Average current
I in I out
(Iave)
   
2
2   (∆iL1 + ∆iLm ) ⋅ 1 + ∆iL 2  
n
 n  2
 ∆iL1 + ∆iLm + ∆iL 2 ⋅ 2    
(1 − δ ) ⋅   I in ⋅ n1  +   
n2
rms current (Irms) I in 2  n1 
+δ ⋅    δ n2  3 
δ 3  
 
Maximum    
 I in + ∆i L1 + ∆i Lm + (I out + ∆i L 2 ) ⋅ 2  (I in + ∆iL1 + ∆iLm ) ⋅ 1 + I out + ∆iL 2 
n n
  
current (imax)  n1   n2 
Turn-on
 n 
switched current  I in − ∆iL1 − ∆iLm + (I out − ∆iL 2 ) ⋅ 2  −
 n1 
(ion) 
Turn-off
 n   
 I in + ∆iL1 + ∆iLm + (I out + ∆iL 2 ) ⋅ 2   (I in − ∆iL1 − ∆iLm ) ⋅ 1 + I out − ∆iL 2 
n
switched current 
 n1  
 n2


(ioff)
Maximum  Vin n    Vin  n2 

 + ∆v C1 + ∆v C 2 ⋅ 1   
  (1 − δ ) + ∆v C1  ⋅ n + ∆v C 2 
voltage (vmax)  (1 − δ ) n2    1 
Turn-on
 Vin n 
switched voltage  + ∆v C1 + ∆v C 2 ⋅ 1  −
(von)  (1 − δ ) n 2 
Turn-off
 Vin n    Vin  n2 
switched voltage  − ∆v C1 − ∆v C 2 ⋅ 1   
  (1 − δ ) + ∆v C1  ⋅ n + ∆v C 2 
(voff)  (1 − δ ) n2    1 
Therefore, from the rms and average current expressions in Table 3.12 and Eq. (3.1), the
average conduction power losses of S1 (Pcond_S1) and D1 (Pcond_D1) are obtained:
  
2 
 n
 ∆i L1 + ∆i Lm + ∆i L 2 ⋅ 2  
I 2 
 n1 
Pcond _ S1 = Vth ⋅ I in + rd ⋅  in + δ ⋅  (3.101)
 δ 3 
 
 
 
  
2 
  (∆i + ∆i Lm )⋅ + ∆i L 2 
n1
 
  I n  2  L1 
 n2 
Pcond _ D1 = Vth ⋅ I out + rd ⋅ (1 − δ ) ⋅   in ⋅ 1  +  (3.102)
 δ n 2  3 
 
 
 
threshold voltage.
78
From the expressions of the current/voltage switched by D1 in Table 3.12 and Eq. (3.2),
the average switching power losses of D1 are expressed as:
   
2
A ⋅  ( − ∆ − ∆ ) ⋅
n1
+ − ∆ 
off , D1  in I i i I i L2  + 
 
L1 Lm out
  Vin  n2  n2  
  
  (1 − δ ) + ∆v C1  ⋅ n + ∆v C 2     
    n
⋅  + Boff , D1 ⋅  (I in − ∆i L1 − ∆i Lm ) ⋅ 1 + I out − ∆i L 2  + 
1
Psw _ D1 = (3.103)
Tsw ⋅ V100 FIT   n2  
+ C 
 off , D1 
 
 
Similarly, the average switching losses of S1 are obtained:
  n 
2 
A ⋅  I in + ∆iL1 + ∆iLm + (I out + ∆iL 2 ) ⋅ 2  + 
 off , S 1 
 Vin n   n1 
 − ∆vC1 − ∆vC 2 ⋅ 1   
 (1 − δ ) n2    n2  
Psw _ S1 = ⋅  + Boff , S1 ⋅  I in + ∆iL1 + ∆iLm + (I out + ∆iL 2 ) ⋅  +  +
Tsw ⋅ V100 FIT   n1  
+ C 
 off , S1 
  (3.104)
 
n   
2
 Vin  n 
 + ∆vC1 + ∆vC 2 ⋅ 1   Aon, S1 ⋅  I in − ∆iL1 − ∆iLm + (I out − ∆iL 2 ) ⋅ 2  + 
(1 − δ )  
+ 2  1
n n
⋅ 
Tsw ⋅ V100 FIT   n2  
 + Bon, S1 ⋅  I in − ∆iL1 − ∆iLm + (I out − ∆iL 2 ) ⋅  + Con, S1 
  n1  
characteristic.
2.2.7 Flyback
The unidirectional flyback converter illustrated in Fig 3.25 is formed by two switches
(transistor S1 and diode D1), a medium frequency transformer (the leakage inductance has
been neglected in this analysis) and two filter capacitors at the input (Cin) and the output
(Cout) sides of the converter. Hence, its few components make it a simple, cheap and a
reliable converter. The flyback converter is a step-up/down converter.
79
Iin n1 : n2 D1 Iout
+ iCin + iLm +
Lm
+ - +
Vin Cin Cout Vout
- - iCout
S1
-
-
Fig 3.25. Flyback converter.
The converter operates shifting the energy coming from the input between the
magnetizing inductance of the MFT (Lm) and the output capacitor Cout. When transistor S1
is on (Ton time interval), the energy coming from input and capacitor Cin is stored in Lm
while the output is supplied by the output capacitor (Fig 3.26a). In turn, during the off-
state of S1 depicted in Fig 3.26b (Toff time interval), the input current flows through the
input capacitor Cin and the energy stored by the magnetizing inductance is transferred to
Cout and the load.
n1 : n2 D1 n1 : n2 D1
+ + + +
Lm Lm
ILm ILm n1
Iout n2 Iout
Vin Cin ILm Cout Vout Vin Cin Cout Vout
Iin S1 Iin S1
- -
- -
a) b)
Fig 3.26. Currents circulating through the flyback converter a) when S1 is on and b)
when S1 is off.
Thus, considering a continuous current mode operation, the average input current Iin can
be expressed as shown by Eq. (3.105). However, as in steady state the average current
circulating through the input capacitor Cin is equal to zero, Eq. (3.105) can be simplified
to Eq. (3.106). So, the input current is directly related to the average current through the
magnetizing inductance ILm, which is always greater than Iin. In turn, this means the
current through the transformer is DC and hence, the transformer utilization is poor as it
is only positively magnetized.
(I Lm − iCin ) ⋅ Ton + iCin ⋅ Toff
I in = (3.105)
Tsw
I Lm ⋅ Ton
I in = = I Lm ⋅ δ (3.106)
Tsw
where Tsw is the switching period, iCin is the current through the input capacitor and δ is
the duty cycle of the transistor S1.
Moreover, neglecting the input and output voltage and current ripple, the steady state
voltage and current waveforms in the converter are drawn as in Fig 3.27. From Fig 3.27a,
80
the DC voltage transfer function of Eq. (3.108) is obtained assuming the average voltage
drop over the magnetizing inductance in a switching period (Tsw) is zero as given by Eq.
(3.107). As noticed, with a unitary turn ratio n2/n1, Vout is lower than Vin when δ<0.5 and
Vout is higher lower than Vin when δ>0.5. Hence, it can be considered that the flyback
converter is a step-up/down converter.
1  Ton Tsw 
v Lm
= ⋅  ∫ v Lm dt + ∫ v Lm dt  = 0 (3.107)
Tsw  
 0 Ton 
δ n
V
= Vin ⋅ ⋅ 2 (3.108)
out
(1 − δ ) n1
where n1 and n2 are the number of turns of primary and secondary windings respectively,
and Vin and Vout are the average input and output voltages respectively (cf. Fig 3.25).
iLm vCout
ΔiLm ΔvCout
ILm Vout
Ton Toff
D1 Conducting
vLm
Tsw t iCout
Tsw t
n1
Vin I -I
n2 Lm out
π
π
π]
t t
n1
- V - Iout
n2 out
a) b)
Fig 3.27. Typical voltage and current waveforms in flyback converter's a) Lm

magnetizing inductance and b) output capacitor Cout.
Moreover, the DC current transfer function is obtained from the steady state analysis (i.e.
assuming the average current through the capacitor is equal to zero) of the current
waveforms illustrated in Fig 3.27b:
I out I in ⋅
=
(1 − δ ) ⋅ n1
(3.109)
δ n2
The magnetizing inductance Lm required by the transformer is calculated from the
analysis of the waveforms of Fig 3.27a during the Ton period of time:
∆t Vin
Lm vLm ⋅
= = ⋅ δ ⋅ Tsw (3.110)
∆i 2 ⋅ ∆iLm
81
where ∆iLm is the current ripple in the magnetizing inductance Lm.

Similarly, Cout capacitance is obtained from the waveforms of Fig 3.27b:
∆t I out
Cout = iCout ⋅ = ⋅ δ ⋅ Tsw (3.111)
∆v 2 ⋅ ∆vCout
where ∆vCout is the desired output voltage ripple.
iCin
Iin
QCin
Iin-ILm +ΔiLm t
Iin-ILm -ΔiLm
Ton Toff
Tsw
Fig 3.28. Current circulating through the input capacitor of the flyback converter.
Assuming a constant input current Iin, the current circulating through Cin can be illustrated
as in Fig 3.28. Thus, the capacitance of Cin is obtained by calculating the QCin charges
depicted in Fig 3.28:
QCin I in
C in = = ⋅ Toff (3.112)
∆v 2 ⋅ ∆v Cin
where ∆vCin is the half of the desired peak to peak voltage ripple in the input capacitor.
The main characteristics of the passive elements previously discussed are summarized in
Table 3.13.
TABLE 3.13

energy stress
Cin
1
⋅ Cin ⋅ (Vin + ∆vCin )2 I in 2 ⋅
(1 − δ ) + δ ⋅ ∆iLm 2 (Vin + ∆vCin )
2 δ 3
2 2
1  I in  ∆iLm
Lm ⋅ Lm ⋅ (I Lm + ∆i Lm )2   + (Vout + ∆vCout ) ⋅ n1
2 δ  3 n2
1 δ
2 (1 − δ )
82
The semiconductor utilization factor (Uf) has been calculated from the voltage and current
expressions of Table 3.14 and neglecting all the current and voltage ripple:
Uf =
PRated
=
(1 − δ ) ⋅ δ
(3.113)
If Eq. (3.113) is illustrated for different duty cycle values Fig 3.29 is obtained. From the
figure, same conclusion as for previously discussed step-up/down type converters is
obtained: the optimal design point with maximum semiconductor utilization is provided
with δ=0.5. Thus, according to this criteria, the converter must be designed to operate
with duty cycles close to 0.5.
0.18
0.13
0.09
0.04
0
0 0.25 0.5 0.75 1
Duty cycle (δ)
Fig 3.29. Semiconductor utilization factor of the flyback converter.
Obtained from Fig 3.27a, Table 3.14 summarizes switched currents and voltages as well
as rms and average currents circulating through the different semiconductors. Therefore,
average conduction power losses of transistor S1 (Pcond_S1) and diode D1 (Pcond_D1) are
obtained from Eq. (3.1) and Table 3.14:
I 2 ∆i 2 
Pcond _ S1 = Vth ⋅ I in + rd ⋅  in + δ ⋅ Lm  (3.114)
 δ 3 
 
  
2 
 n
 ∆i ⋅ 1  
  I n  2  Lm n 
 
+ rd ⋅ (1 − δ ) ⋅   in ⋅ 1  +
2
Pcond _ D1 = Vth ⋅ I out  (3.115)
 δ n 2  3 
 
 
 
threshold voltage.
83
From Eq. (3.2) and Table 3.14, the average switching power losses of D1 are expressed
as:
 Vout 
 + ∆vCout   2 
 δ  ⋅ A   I in  n1  I  n (3.116)
Psw _ D1 = ⋅
off , D1   − ∆i  ⋅ 
 + Boff , D1 ⋅  in − ∆iLm  ⋅ 1 + Coff , D1 
 
 δ δ
Lm
Tsw ⋅ V100 FIT  n2   n2
 
TABLE 3.14
Current and voltage expressions Transistor S1 Diode D1

  n  
2
  ∆iLm ⋅ 1  
2 2 2
∆i   n2  
rms current (Irms)
I in
+ δ ⋅ Lm (1 − δ ) ⋅   Iin ⋅ n1  +  
δ 3  δ n2  3 
 
 
 I in   I in  n1
Maximum current (imax)  δ + ∆i Lm   δ + ∆i Lm  ⋅ n
    2
 I in 
Turn-on switched current (ion)  δ − ∆i Lm  −
 
 I in   I in  n1
Turn-off switched current (ioff)  δ + ∆i Lm   δ − ∆i Lm  ⋅ n
    2
 Vin n   Vout 
Maximum voltage (vmax)  + ∆v Cout ⋅ 1   + ∆v Cout 
 (1 − δ ) n2   δ 
 Vin n 
Turn-on switched voltage (von)  + ∆v Cout ⋅ 1  −
 (1 − δ ) n2 
 Vin n   Vout 
Turn-off switched voltage (voff)  − ∆v Cout ⋅ 1   + ∆v Cout 
 (1 − δ ) n2   δ 
Similarly, the average switching losses of S1 are provided by:
 Vin n 
 − ∆vCout ⋅ 1 
(1 − δ )  I 
2
I  
Psw _ S1 =  2 
n
⋅ Aoff , S1 ⋅  in + ∆iLm  + Boff , S1 ⋅  in + ∆iLm  + Coff , S1  +
Tsw ⋅ V100 FIT  δ  δ  
 
(3.117)
 Vin n 
 + ∆vCout ⋅ 1 
(1 − δ ) n2   I 
2
I  
+ ⋅ Aon, S1 ⋅  in − ∆iLm  + Bon, S1 ⋅  in − ∆iLm  + Con, S1 
Tsw ⋅ V100 FIT  δ  δ  
 
84
characteristic.
2.2.8 Forward
The forward converter is a unidirectional converter as shown in Fig 3.30. Although it is a

step-down converter it can step-up the input voltage depending on the turn ratio of the
transformer. The converter comprises four switches (transistor S1 and D1-D2-D3 diodes), a
medium frequency transformer (the leakage inductance has been neglected in this
analysis), an input capacitor (Cin) and a LC filter at the output (L1 inductor and Cout
capacitor). As it will be explained later, the MFT of the forward converter has three
windings, two for the energy transference and one for the demagnetization of the
transformer.
Iin n1 : n2 : n3 D2 +
L1
- Iout
+ + +
Lm iLm iL1
+ - +
Vin Cin D3 Cout Vout
- -
S1 iCout
-
iCin D1
-
Fig 3.30. Forward converter.
The converter operates storing the energy coming from the input into its inner passive
elements and then transferring it to the output. This way, Fig 3.31a shows that during S1 is
on (Ton time interval), the energy coming from input and capacitor Cin is transferred to L1
and the load. At the same time, the MFT is magnetized positively. When S1 is off (Toff
time interval), the energy coming from the input is stored in Cin and the load is supplied
by the output inductor L1 (Fig 3.31c). It must be highlighted that during the initial period
at which S1 is off (toff time interval), the transformer is demagnetized through the
demagnetization coil (n2). Thus, the energy stored in the magnetizing inductance Lm is
returned to the input as depicted in Fig 3.31b. Therefore, the transformer is only
magnetized positively leading to a poor utilization of it.
85
n1 : n2 : n3 D2 L1
+ +
Lm Iout
Iin S1
D1
- -
a)
n1 : n2 : n3 D2 L1
+ +
Lm iLm
Iout
Iin S1
D1
- -
b)
n1 : n2 : n3 D2 L1
+ +
Lm Iout
Iin S1
D1
- -
c)
Fig 3.31. Currents circulating through the forward converter a) when S1 is on, b) when
S1 is off and the energy stored in Lm is drawn by the input, and c) when S1 is off and
Lm has no energy stored.
Aforementioned operational behaviour is illustrated in the voltage and current waveforms

of Fig 3.32, where a CCM operation has been considered and the input and output voltage
ripple have been neglected.
iLm S1 & D2 Conducting

iL1 S1 & D2 Conducting
2 ΔiLm ΔiL1
D1 Iout
Conducting
Ton Toff
Ton toff
Tsw t
D3 Conducting
Toff
vL1
Tsw t
n3
V -V
n1 in out
vLm
Vin
t
t
n1 - Vout
- V
n2 in
a) b)
Fig 3.32. Typical voltage and current waveforms in forward converter's a) Lm

magnetizing inductance and b) inductor L1.
86
As shown by Fig 3.32a, the transformer demagnetization time interval (toff) is not
necessarily equal to the transistor's off-state period of time (Toff). Analyzing the
waveforms of Fig 3.32a, it can be seen that the demagnetization period is dependant to
the n2/n1 turn ratio as shown below:
2 ⋅ ∆i Lm 
Vin = 
Ton  n2
 → t off = Ton ⋅ (3.118)
n1 2 ⋅ ∆i Lm  n1
− Vin ⋅ =−
n2 t off 
where Vin is the average input voltage (cf. Fig 3.30) and ∆iLm is the current ripple in the
magnetizing inductance Lm.
However, when the maximum energy is transferred, the demagnetization time is equal to
the off-state time (toff =Toff). From this fact, the maximum time at which the transistor S1
can be on (Ton,max) can be calculated, Eq. (3.119). As noticed, the transformer turn ratio
n2/n1 limits the maximum duty cycle of the converter, which means this turn ratio must be
carefully selected so as to optimize the design of the converter. The turn ratio that
maximizes the utilization of the semiconductors is calculated later in this section.
n2 
t off = Ton ⋅ 1
n1  → Ton,max = sw → δ max =
T
n n (3.119)
t off = Tsw − Ton  1+ 2 1+ 2
n1 n1
where Tsw is the switching period of S1 and average input voltage and δmax is the
maximum duty cycle of the converter.
The DC voltage transfer function of Eq. (3.120) is calculated from Fig 3.32b under the
assumption of zero average voltage drop in the output inductor L1 during a switching
period (steady state analysis). Eq. (3.120) shows that the forward converter is a step-down
converter as mentioned in the beginning of this section. Notice that with a unitary n3/n1
turn ratio the output voltage can never be greater than the input voltage.
n3
Vout = Vin ⋅ δ ⋅ (3.120)
n1
where Vout is the average output voltage (cf. Fig 3.30) and δ is the duty cycle of the
converter (Ton/Tsw).
In order to obtain the DC current transfer function it has been assumed that the average
input power is equal to the average output power (ideal case with no losses):
Vin ⋅ I in = Vout ⋅ I out 

 I n
n  → I out = in ⋅ 1 (3.121)
Vout = Vin ⋅ δ ⋅ 3  δ n3
n1 
87
The inductive value of L1 is calculated analyzing the Toff time interval of Fig 3.32b:
∆t
= out ⋅ (1 − δ ) ⋅ Tsw
V
L1 = vL1 ⋅ (3.122)
∆i 2 ⋅ ∆iL1
where ∆iL1 is the current ripple in L1. As expected, the lower the current ripple the higher
will be the required inductance.
Similarly, the magnetizing inductance required by the MFT is calculated from Fig 3.32a:
∆t Vin
Lm = v Lm ⋅ = ⋅ δ ⋅ Tsw (3.123)
∆i 2 ⋅ ∆i Lm
where ∆iLm is the current ripple in the magnetizing inductance.

For the calculation of the input DC bus capacitance (Cin) a constant input current has been
assumed. Therefore, considering δmax is lower than 0.5 (as it will be discussed later, the
maximum utilization of the semiconductors is achieved with δmax=0.4435, for which,
n2/n1 is about 1.2547 and toff is equal to Toff), the current circulating through Cin can be
drawn as in Fig 3.33a. In consequence, Cin capacitance is obtained from calculating the
QCin charges circulating through it and the desired voltage ripple ∆vCin, Eq. (3.124).
QCin (I in + ∆i Lm ) ⋅ Toff
C in = = (3.124)
∆v 2 ⋅ ∆v Cin
Moreover, as the output current Iout is assumed to be constant, it can be deduced from Fig
3.32b that the current through the output capacitor (iCout) is given by the current ripple in
L1. Thus, iCout can be illustrated as in Fig 3.33b and its capacitance calculated as follows:
QCout ∆i L1
C out = = ⋅ Tsw (3.125)
∆v 8 ⋅ ∆vCout
iCin
Iin+2ΔiLm QCin
Iin
iCout
QCout
t ΔiL1
n3 t
Iin-(Iout-ΔiL1) -ΔiL1
n1 Ton Toff
n3
Iin-2ΔiLm-(Iout+ΔiL1) Tsw
n1
Ton Toff
Tsw
a) b)
capacitor of the forward converter.
The main characteristics of the passive elements are summarized in Table 3.15.
88
TABLE 3.15
Element Maximum stored energy rms current

Maximum voltage stress
1 δ
Cin ⋅ C in ⋅ (Vin + ∆v Cin )2 ⋅χ (Vin + ∆vCin )
2 3
1 δ  n2 
Lm ⋅ Lm ⋅ (2 ⋅ ∆i Lm )2 2 ⋅ ∆iLm ⋅ ⋅ 1 +  (Vin + ∆vCin )
2 3  n1 
1
⋅ L1 ⋅ (I out + ∆i L1 )2 ∆iL12 
≈  (Vin + ∆v Cin ) ⋅ 3 − Vout
n 

L1 I out 2 +
2 3  n1 
1 ∆i L1
2 3
 −1
  
3
 n2 ⋅ (I in + 2 ⋅ ∆iLm )2 − 1 ⋅  ∆iL1 ⋅ n3 + ∆iLm  ⋅  I in − (I out + ∆iL1 ) ⋅ n3 − 2 ⋅  ∆iL1 ⋅ n3 + ∆iLm   + 
 n1 2      
n1   n1  n1 
χ= 
 1  −1 3 
 2
n3   n3  n2
(
+ ⋅  ∆iL1 ⋅ + ∆iLm  ⋅  I in − (I out + ∆iL1 ) ⋅  + 2 ⋅ ⋅ I in + I in ⋅ ∆iLm
2
) 
 n1   n1 n 1 
The semiconductor utilization factor (Uf) of Eq. (3.126) is calculated from the voltages
and currents of Table 3.16 and Table 3.17. Current and voltage ripple of those
expressions have been neglected so as to simplify the Uf expression.
PRated (1 − δ max ) ⋅ δ
Uf = = (3.126)
∑all _ switches max rms
v ⋅ I (1 + δ max ) ⋅ δ + (1 − δ max ) ⋅ 1 − δ
As noticed, the utilization factor is dependant to the maximum duty cycle (δmax), which in
turn depends on the transformer turn ratio n2/n1. This means, n2/n1 must be carefully
chosen for maximizing the semiconductor utilization (hence, for optimizing the converter
design). In Fig 3.34 the utilization factor is plotted for different δmax values in order to
determine the optimal n2/n1 turn ratio. As noticed, the maximum utilization factor is given
by δmax≈0.4435 and in consequence, the optimal n2/n1 turn ratio is n2/n1≈1.2547, cf. Eq.
(3.126). In turn, this makes the n3/n1 turn ratio must be chosen so as to ensure the
converter operates with a duty cycle close to δmax (Eq. (3.120)).
89
δmax=0.2

δmax=0.3
0.18 δmax=0.4
δmax=0.4435
0.13 δmax=0.5
δmax=0.6
δmax=0.7
0.09 δmax=0.8
δmax=0.9
0.04
0
0 0.25 0.5 0.75 1
0.4435
Duty cycle (δ)
Fig 3.34. Semiconductor utilization factor of the forward converter.
The semiconductor power losses are calculated analytically by estimating average

conduction power losses of Eq. (3.1) and average switching power losses of Eq. (3.2).
The voltage and current expressions required for estimating those power losses are
obtained from the waveforms of Fig 3.32 (note that the conduction time interval of each
semiconductor is identified) and summarized in Table 3.16 and Table 3.17. Thus, the
average conduction power losses of transistor S1 (Pcond_S1), diode D1 (Pcond_D1), diode D2
(Pcond_D2) and diode D3 (Pcond_D3) are given as follows:
  n  
2
 2  ∆i Lm + ∆i L1 ⋅ 3  
 n   n1  
Pcond _ S1 = Vth ⋅ (I in + ∆i Lm ⋅ δ ) + rd ⋅  I out ⋅ 3 + ∆i Lm  +  ⋅δ (3.127)
 n 1  3 
 
 
n1 δ
Pcond _ D1 = Vth ⋅ ∆i Lm ⋅ δ + rd ⋅ (2 ⋅ ∆i Lm )2 ⋅ ⋅ (3.128)
n2 3
 ∆i 2 
Pcond _ D 2 = Vth ⋅ I out ⋅ δ + rd ⋅ δ ⋅  I out 2 + L1  (3.129)
 3 
 
 ∆i 2 
Pcond _ D 3 = Vth ⋅ I out ⋅ (1 − δ ) + rd ⋅ (1 − δ ) ⋅  I out 2 + L1  (3.130)
 3 
 
where rd is the on-state resistance and Vth is the threshold voltage.
90
TABLE 3.16
EXPRESSIONS OF THE VOLTAGES/CURRENTS IN THE INPUT SIDE SEMICONDUCTORS
Current and voltage

expressions
Average current (Iave) I in + ∆iLm ⋅ δ ∆iLm ⋅ δ

  n  
2
  ∆i Lm + ∆i L1 ⋅ 3  
 
2    n1 δ
n3  n1  ⋅δ 2 ⋅ ∆iLm ⋅ ⋅
rms current (Irms)  I out ⋅ + ∆i Lm  + 
  n1  3  n2 3
 
 
 
 (I out + ∆i L1 ) ⋅ 3 + 2 ⋅ ∆i Lm 
n n1
Maximum current (imax) 2⋅ ⋅ ∆i Lm
 n1  n2
n3
Turn-on switched current (ion) (I out − ∆i L1 )⋅ −
n1
 n 
Turn-off switched current (ioff)  (I out + ∆i L1 ) ⋅ 3 + 2 ⋅ ∆i Lm  0
 n1 
 n   n 
Maximum voltage (vmax) 1 + 1  ⋅ (Vin − ∆v Cin ) 1 + 2  ⋅ (Vin + ∆v Cin )
 n 2   n1 
 n 
Turn-on switched voltage (von) 1 + 1  ⋅ (Vin + ∆v Cin ) −
 n 2 
 n   n 
Turn-off switched voltage (voff) 1 + 1  ⋅ (Vin − ∆vCin ) 1 + 2  ⋅ (Vin − ∆v Cin )
 n2  n1 
Furthermore, the average switching power losses of transistor S1 (Psw_S1), diode D2

(Psw_D2) and diode D3 (Psw_D3) are given as follows:
 n1    
2 
1 +  ⋅ (Vin − ∆vCin )  Aoff , S1 ⋅  (I out + ∆iL1 ) ⋅ 3 + 2 ⋅ ∆iLm  + 
n
 
Psw _ S1 =  n2 
⋅  n1  +
Tsw ⋅ V100 FIT    
 + Boff , S1 ⋅  (I out + ∆iL1 ) ⋅ + 2 ⋅ ∆iLm  + Coff , S1 
n3
  n1   (3.131)
 n1 
1 +  ⋅ (Vin + ∆vCin )
  n 
2 
+
n2 
⋅  Aon, S1 ⋅  (I out − ∆iL1 ) ⋅ 3  + Bon, S1 ⋅ (I out − ∆iL1 ) ⋅ 3 + Con, S1 
n
Tsw ⋅ V100 FIT  
  n1  n1

⋅ (Vin − ∆vCin )
n3
Psw _ D 2 =
n2
Tsw ⋅ V100 FIT
(
⋅ Aoff , D 2 ⋅ (I out + ∆iL1 )2 + Boff , D 2 ⋅ (I out + ∆iL1 ) + Coff , D 2 ) (3.132)
⋅ (Vin + ∆vCin )
n3
Psw _ D 3
n
= 1
Tsw ⋅ V100 FIT
(
⋅ Aoff , D 3 ⋅ (I out − ∆iL1 )2 + Boff , D 3 ⋅ (I out − ∆iL1 ) + Coff , D 3 ) (3.133)
where AXX, BXX and CXX are the switching energy loss characteristic coefficients provided
by the manufacturer for the 100FIT test voltage (V100FIT) of each semiconductor switch.
91
TABLE 3.17
EXPRESSIONS OF THE VOLTAGES/CURRENTS IN THE OUTPUT SIDE SEMICONDUCTORS
Current and voltage expressions Diode D2 Diode D3
Average current (Iave) I out ⋅ δ I out ⋅ (1 − δ )
 ∆i 2    2
rms current (Irms) δ ⋅  I out 2 + L1  (1 − δ ) ⋅  I out 2 + ∆iL1 

 3   3 
Maximum current (imax) (I out + ∆i L1 ) (I out + ∆i L1 )
Turn-off switched current (ioff) (I out + ∆i L1 ) (I out − ∆i L1 )

⋅ (Vin + ∆v Cin ) ⋅ (Vin + ∆v Cin )
n3 n3
Maximum voltage (vmax)
n2 n1
⋅ (Vin − ∆vCin ) ⋅ (Vin + ∆vCin )

n3 n3
Turn-off switched voltage (voff)
n2 n1
The switching power losses of D1 are considered negligible (Psw_D1=0) since it is turned-
off when the current through it reaches zero (noticeable in Fig 3.32a and Table 3.16).
2.2.9 Two-transistor forward
The two-transistor forward converter of Fig 3.35 is a unidirectional converter derived

from the previously discussed forward converter. Therefore, the two-transistor forward
converter is also a step-down converter. The main difference between the two converters
is that the two-transistor forward does not have a third winding for the demagnetization of
the medium frequency transformer. Hence, the design of its MFT is easier than that of the
forward converter. However, the two-transistor forward converter requires one more
semiconductor than that required by the forward converter. As depicted in Fig 3.35, two-
transistor forward converter is composed of four diodes (D1-D2-D3-D4), two transistors
(S1-S2), a medium frequency transformer (its leakage inductance has been neglected in
this analysis), an input capacitor (Cin) and a LC filter at the output (inductor L1 and
capacitor Cout).
92
Iin
+ D3 +
L1 I
- out
D1 S1 +
iL1
n1 : n2
iLm + +
Vin + Lm D4 Vout
Cin Cout
- - -
iCin iCout
D2 S2 -
-
Fig 3.35. Two-transistor forward converter.
The operation of the converter is based on the storage and subsequent transference of the
energy coming from the input. The transistors of the converter are operated
simultaneously. Thus, when transistors S1 and S2 are on (Ton time interval), the energy
coming from input and Cin capacitor is transferred to the output inductor L1 and the load
while the MFT is magnetized positively (Fig 3.36a). On the other hand, when S1 and S2
transistors are off (Toff time interval), the Cin capacitor stores the energy coming from
input and L1 supplies the output load (Fig 3.36c). During the initial period in which S1 and
S2 are off (toff time interval) the transformer is demagnetized through the demagnetization
diodes D1 and D2. As a consequence, the energy stored in the magnetizing inductance Lm
is returned to the input (Fig 3.36b). This way, the transformer is only magnetized
positively (cf. Fig 3.37a) and in consequence, its utilization is poor. Fig 3.37 illustrates
the current and voltage waveforms resulting from afore described operation considering a
CCM and neglecting the ripple of the input and output voltages.
From Fig 3.37a, the time toff at which the transformer is demagnetized is equal to Ton as
given by Eq. (3.134). To avoid transformer's core saturation, the most critical case at
which the demagnetization is guaranteed is when toff =Toff. Therefore, the maximum duty
cycle of the converter is equal to 0.5 as provided by Eq. (3.135).
2 ⋅ ∆i Lm 
Vin = 
Ton 
 → t off = Ton (3.134)
2 ⋅ ∆i Lm 
− Vin = −
t off 
t off = Ton  1
 → δ max = (3.135)
t off = Tsw − Ton  2
where Vin is the average input voltage (cf. Fig 3.35), ∆iLm is the current ripple in the
magnetizing inductance Lm, Tsw is the switching period and δmax is the maximum duty
cycle of the converter (Ton/Tsw).
93
+ D3 L1
D1 S1 +
Iout
n1 : n2
Vin Cin Lm D4 Cout Vout
Iin -
D2 S2
-
a)
+ D3 L1
D1 S1 +
Iout
n1 : n2
iLm
Iin D2 S2 -
-
b)
+ D3 L1
D1 S1 +
Iout
n1 : n2
Iin D2 S2 -
-
c)
Fig 3.36. Currents circulating through the two-transistor forward converter a) when
S1-S2 are on, b) when S1-S2 are off and the energy stored in Lm is drawn by the input,
and c) when S1-S2 are off and Lm has no energy stored.
iLm S1-S2 & D3 Conducting

iL1 S1-S2 & D3 Conducting
2 ΔiLm ΔiL1
D1-D2 Iout
Conducting
Ton Toff
Ton toff
Tsw t
D4 Conducting
Toff
vL1
Tsw t
n2
V -V
n1 in out
vLm
Vin
t
t
- Vout
-Vin
a) b)
Fig 3.37. Typical voltage and current waveforms in two-transistor forward converter's
a) magnetizing inductance Lm and b) inductor L1.
94
In turn, the DC voltage transfer function is obtained from the steady state analysis of the
waveforms of Fig 3.37b:
n2
Vout = Vin ⋅ δ ⋅ (3.136)
n1
where Vout is the average output voltage (cf. Fig 3.35) and δ is the duty cycle of the
converter.
Assuming an ideal operation with no losses, the average input power is equal to the
average output power. Thus, the DC current transfer function is given as below:

 I n
n  → I out = in ⋅ 1 (3.137)
Vout = Vin ⋅ δ ⋅ 2  δ n2
n1 
Furthermore, analyzing the waveforms of Fig 3.37b, the inductive value of L1 is obtained
as follows:
∆t
= out ⋅ (1 − δ ) ⋅ Tsw
V
L1 = vL1 ⋅ (3.138)
∆i 2 ⋅ ∆iL1
where ∆iL1 is the current ripple in L1. As expected, the lower the current ripple the higher
will be the required inductance.
Similarly, the magnetizing inductance Lm is calculated from the waveforms of Fig 3.37a:
∆t Vin
Lm = v Lm ⋅ = ⋅ δ ⋅ Tsw (3.139)
∆i 2 ⋅ ∆i Lm
where ∆iLm is the current ripple in Lm.

The capacitances of Cin and Cout can be calculated from Fig 3.38, where the currents
though them are drawn assuming the average input and output currents (Iin and Iout) are
constant. In Fig 3.38a, the duty cycle is slightly lower than 0.5 since due to the practical
operational limitations of the semiconductors, in real conditions, the converter cannot be
operated with the maximum ideal duty cycle δmax=0.5. Thus, Cin capacitance is given by
Eq. (3.140). Nonetheless, Cout capacitance is given by the charge circulation caused by the
current ripple in L1 as shown in Fig 3.38b, Eq. (3.141).
QCin I in ⋅ Toff + ∆i Lm ⋅ t off

C in = = (3.140)
∆v 2 ⋅ ∆v Cin
QCout ∆i L1
C out = = ⋅ Tsw (3.141)
∆v 8 ⋅ ∆v Cin
where ∆vCin and ∆vCout are the half of the desired peak to peak input and output voltage
ripple respectively.
95
iCin
Iin+2ΔiLm QCin
Iin
iCout
QCout
ΔiL1
n2 t -ΔiL1 t
Iin-(Iout-ΔiL1)
n1 Ton Toff
toff
n2
Iin-2ΔiLm-(Iout+ΔiL1) Tsw
n1 Ton Toff
Tsw
a) b)
capacitor of the two-transistor forward converter.
Table 3.18 summarizes the equations regarding to the maximum stored energy, the
maximum voltage stress and the rms currents circulating through the passive elements of
the converter.
TABLE 3.18
Maximum stored
Element rms current
energy Maximum voltage stress
1 δ
Cin ⋅ C in ⋅ (Vin + ∆v Cin )2 I in 2 ⋅ (1 − 2 ⋅ δ ) + ⋅χ (Vin + ∆vCin )
2 3
1 2 ⋅δ
Lm ⋅ Lm ⋅ (2 ⋅ ∆i Lm )2 2 ⋅ ∆iLm ⋅ (Vin + ∆vCin )
2 3
1
⋅ L1 ⋅ (I out + ∆i L1 )2 ∆iL12  
≈  (Vin + ∆vCin ) ⋅ 2 − Vout 
n
L1 I out 2 +
2 3  n1 
1 ∆i L1
2 3
 −1
  
3
(I in + 2 ⋅ ∆iLm )2 − 1 ⋅  ∆iL1 ⋅ n2 + ∆iLm  ⋅  I in − (I out + ∆iL1 ) ⋅ n2 − 2 ⋅  ∆iL1 ⋅ n2 + ∆iLm   + 
 2      
n1   n1  n1 
χ= 
 1  −1 3 
 2 
n2   n2 
(
+ ⋅  ∆iL1 ⋅ + ∆iLm  ⋅  I in − (I out + ∆iL1 ) ⋅  + 2 ⋅ I in + I in ⋅ ∆iLm
2
) 

n1   n1 
The semiconductor utilization factor (Uf) of Eq. (3.142) is calculated from the maximum
voltages and rms currents of Table 3.19 and Table 3.20. It must be highlighted that the
current and voltage ripple of those expressions have been neglected for the Uf expression
calculation.
PRated δ
Uf = = (3.142)
∑all _ switches max rms 3 ⋅ δ + 1 − δ
v ⋅ I
For different duty cycle values, Eq. (3.142) is illustrated in Fig 3.39. As noticed, the
semiconductor utilization increases along with the increase of the duty cycle. Therefore,
given that the DC voltage transfer function of Eq. (3.136) depends on the duty cycle and
96
the transformer turn ratio, n2/n1 turn ratio must be carefully chosen to guarantee the
converter's operation with duty cycles close to the maximum value of 0.5.

0.18
0.13
0.09
0.04
0
0 0.125 0.25 0.375 0.5
Duty cycle (δ)

Fig 3.39. Semiconductor utilization factor of the two-transistor forward converter.
Semiconductor power losses are calculated analytically by estimating average conduction

power losses, Eq. (3.1), and average switching power losses, Eq. (3.2). Obtained from Fig
3.37, the voltage and current expressions required for estimating those power losses are
summarized in Table 3.19 and Table 3.20. It must be highlighted that due to the
simultaneous operation of the two transistors of the converter, the currents through them
and their blocking voltages are the same. Similarly, the current circulating through D1 and
D2 diodes as well as their reverse blocking voltages are also same.
From Table 3.19 and Eq. (3.1), the average conduction power losses of the input side
semiconductors are given as follows (Pcond_S1 for transistors S1-S2 and Pcond_D1 for diodes
D1-D2):
  n2  
2
 2  ∆i Lm + ∆i L1 ⋅  
 n   n1  
Pcond _ S1 = Vth ⋅ (I in + ∆i Lm ⋅ δ ) + rd ⋅  I out ⋅ 2 + ∆i Lm  +  ⋅δ (3.143)
 n1  3 
 
 
δ
Pcond _ D1 = Vth ⋅ ∆i Lm ⋅ δ + rd ⋅ (2 ⋅ ∆i Lm )2 ⋅ (3.144)
3
where rd and Vth are each semiconductor's on-state resistance and threshold voltage
respectively.
97
TABLE 3.19
Current and voltage expressions Transistors S1-S2 Diodes D1-D2
Average current (Iave) I in + ∆iLm ⋅ δ ∆iLm ⋅ δ

  n  
2
  ∆iLm + ∆iL1 ⋅ 2  
 
2  n1   δ
+ ∆iLm  + 
n2
rms current (Irms)  I out ⋅  ⋅δ 2 ⋅ ∆i Lm ⋅
 n1  3  3
 
 
 
 (I out + ∆i L1 ) ⋅ 2 + 2 ⋅ ∆i Lm 
n
Maximum current (imax) 2 ⋅ ∆i Lm
 n1 
Turn-on switched current (ion) (I out − ∆i L1 ) ⋅

n2
−
n1
 
 (I out + ∆i L1 ) ⋅ 2 + 2 ⋅ ∆i Lm 
n
Turn-off switched current (ioff) 0
 n1 
Maximum voltage (vmax) (Vin − ∆vCin ) (Vin + ∆vCin )
Turn-on switched voltage (von)

(Vin + ∆vCin )
−
2
Turn-off switched voltage (voff) (Vin − ∆vCin ) (Vin + ∆vCin )

2
TABLE 3.20
Current and voltage expressions Diode D3 Diode D4
Average current (Iave) I out ⋅ δ I out ⋅ (1 − δ )
 ∆i 2    2
rms current (Irms) δ ⋅  I out 2 + L1  (1 − δ ) ⋅  I out 2 + ∆iL1 

 3   3 
Maximum current (imax) (I out + ∆i L1 ) (I out + ∆i L1 )
Turn-off switched current (ioff) (I out + ∆i L1 ) (I out − ∆i L1 )

⋅ (Vin + ∆v Cin ) ⋅ (Vin + ∆v Cin )
n2 n2
Maximum voltage (vmax)
n1 n1
⋅ (Vin − ∆v Cin ) ⋅ (Vin + ∆v Cin )

n2 n2
Turn-off switched voltage (voff)
n1 n1
98
Similarly, from Table 3.20 and Eq. (3.1), average conduction power losses of the output
side D3 diode (Pcond_D3) and D4 diode (Pcond_D4) are obtained:
 ∆i 2 
Pcond _ D 3 = Vth ⋅ I out ⋅ δ + rd ⋅ δ ⋅  I out 2 + L1  (3.145)
 3 
 
 ∆i 2 
Pcond _ D 4 = Vth ⋅ I out ⋅ (1 − δ ) + rd ⋅ (1 − δ ) ⋅  I out 2 + L1  (3.146)
 3 
 
The switching power losses of D1 and D2 are negligible as they are turned-off when the
current through them is equal to zero (Table 3.19 and Fig 3.37a). Conversely, average
switching power losses of the transistors (Psw_S1), diode D3 (Psw_D3) and diode D4 (Psw_D4)
are given as follows:
  
2 
A ⋅  ( I + ∆i ) ⋅
n2
+ 2 ⋅ ∆i  + 
(Vin − ∆vCin ) 
off , S 1  out L1 Lm  
Psw _ S1 = ⋅  n1  +
Tsw ⋅ V100 FIT    
 + Boff , S1 ⋅  (I out + ∆iL1 ) ⋅ + 2 ⋅ ∆iLm  + Coff , S1 
n2
  n1  
(3.147)
(Vin + ∆vCin )   n 
2 
⋅  Aon, S1 ⋅  (I out − ∆iL1 ) ⋅ 2  + Bon, S1 ⋅ (I out − ∆iL1 ) ⋅ 2 + Con, S1 
n
+
2 ⋅ Tsw ⋅ V100 FIT  
  n1  n1

⋅ (Vin − ∆vCin )
n2
Psw _ D 3
n
= 1
Tsw ⋅ V100 FIT
(
⋅ Aoff , D 3 ⋅ (I out + ∆iL1 )2 + Boff , D 3 ⋅ (I out + ∆iL1 ) + Coff , D 3 ) (3.148)
⋅ (Vin + ∆vCin )
n2
Psw _ D 4
n
= 1
Tsw ⋅ V100 FIT
(
⋅ Aoff , D 4 ⋅ (I out − ∆iL1 )2 + Boff , D 4 ⋅ (I out − ∆iL1 ) + Coff , D 4 ) (3.149)
where Aoff,XX, Boff,XX and Coff,XX are the turn-off energy loss characteristic coefficients
provided by the manufacturer for the 100FIT test voltage (V100FIT) of each semiconductor
switch and Aon,S1, Bon,S1 and Con,S1 are the turn-on energy loss characteristic coefficients of
the transistors.
2.2.10 Push-pull
The push-pull converter of Fig 3.40 is a unidirectional converter derived from buck
converter. The converter is composed of an input capacitor (Cin), two transistors at the
input side (S1-S2), a medium frequency transformer with three windings (the leakage
inductances have been neglected for the analysis), a diode rectifier (D1-D2-D3-D4) and an
output side LC filter (inductor L1 and capacitor Cout).
99
Iin +
L1
- Iout
+ +
iCin iL1
D1 D3
n1 : n2 : n3
+ + iLm +
Vin Cin Lm Cout
- Vout
-
-
iCout
S1 S2 D4 D2
- -
Fig 3.40. Push-pull converter.
The converter operates alternating the switching orders of the transistors. Thus, when
transistor S1 is on, transistor S2 is off and vice versa. During the on-state of transistor S1
shown in Fig 3.41a (Ton time interval), the energy coming from the input and the
capacitor Cin is transferred to the inductor L1 and the load. At the same time, the
magnetizing inductance Lm is magnetized positively.
L1
+ +
D1 D3 Iout
n1 : n2 : n3
Vin Cin Lm Cout Vout
Iin S1 S2 D4 D2
- -
a)
L1
+ +
D1 D3 Iout
n1 : n2 : n3
Iin S1 S2 D4 D2
- -
b)
L1
+ +
D1 D3 Iout
n1 : n2 : n3
iLm
Iin S1 S2 D4 D2
- -
c)
Fig 3.41. Currents circulating through the push-pull converter a) when S1 is on and S2
is off, b) when S1 is off and S2 is on, and c) when S1-S2 are off and the current in Lm
flows through the output rectifier diodes.
100
When transistor S2 is on, the converter operates similarly with the only difference that the
magnetizing inductance is magnetized negatively (cf. Fig 3.41b). Conversely, when both
transistors are off (Toff time interval), inductor L1 supplies the load and the magnetizing
current flows through the output diodes (cf. Fig 3.41c).
Assuming the number of turns of the primary windings n1 and n2 are equal, a continuous
current mode operation and neglecting the ripple of the input and output voltages, Fig
3.42 shows the current and voltage waveforms resulting from the afore described
operation.
D1-D2-D3-D4 D1-D2-D3-D4
iLm S1 & D1-D2 Conducting iL1 Conducting
Conducting
ΔiLm ΔiL1
Tsw Iout
-ΔiLm t
Ton Toff Ton Toff Ton Toff Ton Toff
S2 & D3-D4
Conducting S1 & D1-D2 S2 & D3-D4
vLm Conducting Conducting
vL1
Tsw Tsw t
Vin 2
n3
V -V
n1 in out
x π
π]
t
π
π]
- Vin t
- Vout
a) b)
Fig 3.42. Typical voltage and current waveforms in push-pull converter's a)

magnetizing inductance Lm and b) inductor L1.
As it can be noticed in Fig 3.42a, the transformer is magnetized bidirectionally leading to

a good utilization of it. In turn, it can be deduced that each transistor cannot be on more
than half of the switching period (Tsw/2), otherwise, the transformer core will be saturated
inevitably, cf. Eq. (3.150). In fact, even respecting this limit, the control scheme must
guarantee the average voltage applied to the transformer is zero in order to avoid
transformer saturation (no DC injection).
T 1
Ton,max = sw → δ max = (3.150)
2 2
where δmax is the maximum duty cycle of the converter (Ton,max/Tsw).
The DC voltage transfer function is derived from steady state analysis of the waveforms
of Fig 3.42b:
n3
V=
out 2 ⋅ Vin ⋅ δ ⋅ (3.151)
n1
101
where Vin and Vout are the average input and output voltages respectively, δ is the duty
cycle of the converter and n3 represents the number of turns of the secondary winding of
the MFT (cf. Fig 3.40).
Assuming that the average input power is equal to the average output power, the DC
current transfer function is given by:

 I n
n  → I out = in ⋅ 1 (3.152)
Vout = 2 ⋅ Vin ⋅ δ ⋅ 3  2 ⋅ δ n3
n1 
The values of the magnetizing inductance Lm and the output side inductor L1 are obtained
from the steady state analysis of the waveforms in Fig 3.42a and Fig 3.42b respectively:
∆t Vin
Lm = v Lm ⋅ = ⋅ δ ⋅ Tsw (3.153)
∆i 2 ⋅ ∆i Lm
∆t
= out ⋅ (1 − 2 ⋅ δ ) ⋅ Tsw
V
L1 = vL1 ⋅ (3.154)
∆i 4 ⋅ ∆iL1
where ∆iLm is the current ripple in Lm and ∆iL1 is the current ripple in L1.
The currents through input and output capacitors are depicted in Fig 3.43, where it has
been assumed that the average input and output currents (Iin and Iout) are constant.
iCin
Iin
QCin iCout
QCout
ΔiL1
Iin+ΔiLm-(Iout-ΔiL1)
n3 -ΔiL1 t
n1
t Ton Toff
n3 Tsw
Iin-ΔiLm-(Iout+ΔiL1) 2
n1
Ton Toff
Tsw
2
a) b)
capacitor of the push-pull converter.
Therefore, Cin capacitance is calculated from Fig 3.43a, where the charges variation in the
capacitor is illustrated (QCin):
T 
I in ⋅  sw − Ton 
QCin  2  (3.155)
C in = =
∆v 2 ⋅ ∆v Cin
102
Similarly, Cout capacitance can be obtained from Fig 3.43b:

QCout ∆i L1
C out = = ⋅ Tsw (3.156)
∆v 16 ⋅ ∆vCout
Additionally, the expressions of the maximum energy stored by the passive elements,
their maximum voltage stress and the rms currents circulating through them are derived
from the waveforms of Fig 3.42 and Fig 3.43. These expressions are summarized Table
3.21.
TABLE 3.21
Maximum stored Maximum voltage

Element rms current
energy stress
1
Cin ⋅ C in ⋅ (Vin + ∆v Cin )2 2 ⋅ δ ⋅ χ + (1 − 2 ⋅ δ ) ⋅ I in 2 (Vin + ∆vCin )
2
1 4 ⋅δ
Lm ⋅ Lm ⋅ ∆i Lm 2 ∆i Lm ⋅ 1 − (Vin + ∆vCin )
2 3
1
⋅ L1 ⋅ (I out + ∆i L1 )2 ∆iL12 (Vout + ∆vCout )
L1 I out 2 +
2 3
1 ∆i L1
2 3
  
2 
  ∆i ⋅
n3
+ ∆i  
 n 
2  L1 n Lm  
χ =   I in − I out ⋅ 3  +  
1

 n1  3 
 
 
 
The semiconductor utilization factor (Uf) is calculated from the voltage and current
expressions of Table 3.22:
PRated δ
Uf = = (3.157)
∑all _ switches max rms 2 ⋅ δ + 1 − 2 ⋅ δ
v ⋅ I
This semiconductor utilization factor is plotted in Fig 3.44 for different duty cycle values.
As it can be noticed, the higher the duty cycle the better the semiconductor utilization.
Therefore, in order to minimize the semiconductor installed power in the converter, n2/n1
turn ratio must be carefully chosen to guarantee that the converter operates with duty
cycles close to 0.5.
103

0.35
0.27
0.18
0.09
0
0 0.125 0.25 0.375 0.5
Duty cycle (δ)

Fig 3.44. Semiconductor utilization factor of the push-pull converter.
The transistors S1 and S2 conduct the same current. Thus, average power losses in both
transistors are equal. As it can be noticed in Fig 3.42, this is applicable to output side
rectifier diodes D1-D2-D3-D4. Thus, power losses expressions are calculated just for one
semiconductor in each group. Table 3.22 summarizes the expressions of the currents
through the semiconductors as well as of the voltages they block.
TABLE 3.22
Current and voltage Diodes

Transistors S1-S2
expressions D1-D2-D3-D4
I in I out
Average current (Iave)
2 2
  2 2
n  
2
1  ∆iL1 


 ∆iLm + ∆iL1 ⋅ 3   (1 + 2 ⋅ δ ) ⋅  I out  + ⋅  +
 n3 
2  n1    2  3  2  

rms current (Irms)  I out ⋅  +  ⋅δ
 n1  3 
2
 ∆i n 
  + (1 − 2 ⋅ δ ) ⋅  Lm ⋅ 1 
   2 n3 
 
Maximum current (imax)  (I out + ∆i L1 ) ⋅ 3 + ∆i Lm 
n
(I out + ∆i L1 )
 n1 
 
 (I out − ∆i L1 ) ⋅ 3 − ∆i Lm 
n
Turn-on switched current (ion) −
 n1 
Turn-off switched current (ioff)

 n 
 (I out + ∆i L1 ) ⋅ 3 + ∆i Lm 
(I out − ∆i L1 )
 n1  2
(Vin + ∆vCin ) ⋅
n3
Maximum voltage (vmax) 2 ⋅ (Vin + ∆v Cin )
n1
Turn-on switched voltage (von) (Vin + ∆vCin ) −
Turn-off switched voltage (voff) (Vin − ∆vCin ) (Vin + ∆vCin ) ⋅ n3

n1
104
Thus, average conduction power losses of transistor S1 (Pcond_S1) and diode D1 (Pcond_D1)
are derived from Table 3.22 and Eq. (3.1):
  n3  
2
  ∆i + ∆ i ⋅  
n3   n1  
2 Lm L1
I in 
Pcond _ S1 = Vth ⋅ + rd ⋅  I out ⋅  +  ⋅δ (3.158)
2  n1  3 
 
 
I out
Pcond _ D1 = Vth ⋅ +
2
 (3.159)
 ∆i Lm n1  
2
 I 2
 1  ∆i L1 
2
+ rd ⋅ (1 + 2 ⋅ δ ) ⋅  out  + ⋅    + (1 − 2 ⋅ δ ) ⋅ 
 ⋅  

  2  3  2    2 n3  

where rd and Vth are respectively each semiconductor's on-state resistance and threshold
voltage.
On the other hand, average switching power losses of the transistor S1 (Psw_S1) and diode
D1 (Psw_D1) are derived from Table 3.22 and Eq. (3.2):
  
2 
A ⋅  ( I + ∆i ) ⋅
n3
+ ∆i  + 
off , S1  out Lm 
Psw _ S1 =
(Vin − ∆vCin ) 
⋅ 
L1
n1 

+
Tsw ⋅ V100 FIT    
 + Boff , S1 ⋅  (I out + ∆iL1 ) ⋅ + ∆iLm  + Coff , S1 
n3
  n1  
(3.160)
  
2 
A  ( ) n3
 
⋅
on , S1  outI − ∆i ⋅ − ∆i Lm  +
+
(Vin + ∆vCin ) 
⋅ 
L1
n1 


Tsw ⋅ V100 FIT    
 + Bon, S1 ⋅  (I out − ∆iL1 ) ⋅ − ∆iLm  + Con, S1 
n3
  n1  
(Vin + ∆vCin ) ⋅ n3
Psw _ D1 =
n1  (I − ∆iL1 )2 + B ⋅ (I out − ∆iL1 ) + C 
⋅ Aoff , D1 ⋅ out (3.161)
Tsw ⋅ V100 FIT  4
off , D1
2
off , D1 
 
the transistors.
2.2.11 Push-pull isolated-boost
The push-pull isolated-boost converter is a unidirectional step-up converter. As it can be

noticed in Fig 3.45, the converter is formed of two transistors at the input side (S1-S2) and
a diode bridge at the output side (D1-D2-D3-D4). In turn, it requires a DC bus capacitor
(Cin) and an inductor (L1) in the input side, a medium frequency transformer with three
windings and an output filter capacitor (Cout).
105
Iin +
L1
-
Iout
+ +
iL1 D1 D3
n1 : n2 : n3
+ + iLm +
Vin Cin Lm Cout
- Vout
- iCin -
iCout
S1 S2 D4 D2
- -
Fig 3.45. Push-pull isolated-boost converter.
The operation of the converter is similar to that of a boost converter. The energy coming
from the input is stored in the inductor L1 and then, transferred to the output. This way,
when transistors S1 and S2 are on (Ton time interval), the energy coming from the input is
stored in the inductor L1 and the current through the magnetizing inductance remains
constant (cf. Fig 3.46a). Meanwhile, the output capacitor Cout supplies the load. Next,
transistor S2 is turned-off and, during the Toff time interval (cf. Fig 3.46b), the energy
coming from the input as well as the energy stored in L1 are transferred to the output
capacitor and the load. In turn, the transformer is magnetized positively.
L1
+ +
D1 D3 Iout
n1 : n2 : n3
Iin S1 S2 D4 D2
- -
a)
L1
+ +
D1 D3 Iout
n1 : n2 : n3
Iin S1 S2 D4 D2
- -
b)
L1
+ +
D1 D3 Iout
n1 : n2 : n3
Iin S1 S2 D4 D2
- -
c)
Fig 3.46. Currents circulating through the push-pull isolated-boost converter a) when
S1 and S2 are on, b) when S1 is on and S2 is off, and c) when S1 is off and S2 is on.
106
Subsequently, transistor S2 is turned-on and a new Ton time interval begins (cf. Fig 3.46a)
until transistor S1 is turned-off. Then, a second Toff time interval begins and the
transformer is magnetized negatively (cf. Fig 3.46c). As the transformer is magnetized
bidirectionally, its utilization is good. However, it requires to control the average voltage
applied to it so as to avoid the saturation of the core.
Although the leakage inductance of the MFT has been neglected in this analysis, this
parasitic inductance has to be considered in real cases. With the described operation, the
current circulating through it is interrupted and in consequence, the voltage drop over it
will increase suddenly. This voltage will appear over transistors increasing their voltage
stress. Therefore, in real cases, snubber circuits must be considered in order to protect the
transistors.
Assuming the number of turns of the windings n1 and n2 are equal, the currents and
voltages in a push-pull isolated-boost converter with a CCM operation are depicted in Fig
3.47. For simplicity, the voltage ripple have been neglected in Fig 3.47a and Fig 3.47b.
For the same reason, the current ripple have been neglected in Fig 3.47c.
As it can be deduced from Fig 3.47a, the maximum period of time in which both
transistors are on is Tsw/2. If this limit is exceeded, the transformer is not magnetized
equally in both senses and in consequence, the core is saturated. Therefore, the maximum
duty cycle of the converter is given by:
Tsw 1
Ton,max = → δ max = (3.162)
2 2
The DC voltage transfer function is derived from the steady state analysis of the
waveforms of Fig 3.47b:
Vin n
Vout = ⋅ 3 (3.163)
1 − 2 ⋅ δ n1
cycle of the converter and n3 represents the number of turns of the secondary winding of
the MFT (cf. Fig 3.45).
In turn, from the steady state analysis of the waveforms in Fig 3.47c, the DC current
transfer function is given by:
I out = (1 − 2 ⋅ δ ) ⋅ I in ⋅
n1
(3.164)
n3
The values of the magnetizing inductance Lm, Eq. (3.165), and the output side inductor L1,
Eq. (3.166), are obtained from the steady state analysis of the waveforms of Fig 3.47a and
Fig 3.47b respectively.
107
∆t Vout n
Lm vLm ⋅
= = ⋅ 1 ⋅ (1 − 2 ⋅ δ ) ⋅ Tsw (3.165)
∆i 4 ⋅ ∆iLm n3
∆t Vin
L1 vL1 ⋅
= = ⋅ δ ⋅ Tsw (3.166)
∆i 2 ⋅ ∆iL1
Similarly, the capacitance value of Cout is derived from the steady state analysis of the
waveforms in Fig 3.47c:
∆t I out
Cout iCout ⋅
= = ⋅ δ ⋅ Tsw (3.167)
∆v 2 ⋅ ∆vC1
where ∆vCout is the desired output voltage ripple.

S1-S2
Conducting
iLm S1 & D1-D2 S2 & D3-D4

Conducting
Conducting
ΔiLm
Tsw
- ΔiLm t
Ton Toff Ton Toff
vLm
n1
V
n3 out
y=-sinx, x∊[0,2
x [0,2
[0,2π]
π
t
n1
- V
n3 out
a)
iL1 S1 & D1-D2

Conducting
S2 & D3-D4
Conducting vCout
ΔiL1 ΔvCout
Iin Vout
Ton Toff Ton Toff
S1-S2 S1-S2 Ton Toff Ton Toff

Conducting Conducting
vL1
Tsw Tsw t iCout Tsw Tsw t
2 2
Vin n1
I -I
n3 in out
π
π
π]
t t
n1
Vin - V
n3 out - Iout
b) c)
Fig 3.47. Typical voltage and current waveforms in push-pull isolated-boost

converter's a) magnetizing inductance Lm, b) inductor L1 and c) capacitor Cout.
108
The input DC bus capacitance can be derived from Fig 3.48. As it can be noticed,
assuming the input current Iin is constant, the current through the input capacitor is
dependent to the ripple in L1. Therefore, Cin capacitance is given by:
QCin ∆i L1
C in = = ⋅ Tsw (3.168)
∆v 16 ⋅ ∆v Cin
iCin
QCin
ΔiL1
-ΔiL1 t
Ton Toff T
sw
2
Fig 3.48. Current through the input capacitor of the push-pull isolated-boost
converter.
The equations of the maximum energy stored by the passive elements, their maximum
voltage stress and the rms currents circulating through them are derived from the
waveforms of Fig 3.47 and Fig 3.48. These expressions are outlined in Table 3.23.
TABLE 3.23
Maximum stored Maximum

Element rms current
1 ∆i L1
Cin ⋅ C in ⋅ (Vin + ∆v Cin )2 (Vin + ∆vCin )
2 3
1 1+ 4 ⋅δ (Vout + ∆vCout ) ⋅ n1
Lm ⋅ Lm ⋅ ∆i Lm 2 ∆iLm ⋅ n3
2 3
1
⋅ L1 ⋅ (I in + ∆iL1 )2
∆iL12 (Vin + ∆vCin )
L1 I in 2 +
2 3
2
1  
⋅ Cout ⋅ (Vout + ∆vCout )2
n
2 ⋅ δ ⋅ I out 2
+ (1 − 2 ⋅ δ ) ⋅  I in ⋅ 1 − I out  (Vout + ∆vCout )
Cout 2  n3 
Last, in order to select the appropriate operational point for the design, the semiconductor
utilization factor (Uf) is calculated from the voltage and current expressions of Table
3.24:
PRated 1− 2 ⋅δ
Uf = =
∑all _ switches vmax ⋅ I rms  1−δ
4⋅ +
1− 2 ⋅δ 
 (3.169)
 2 2 
 
109
As illustrated in Fig 3.49, the lower the duty cycle the better the semiconductor
utilization. Hence, n2/n1 turn ratio must be chosen to make sure the converter operates
with low duty cycle values.

0.18
0.13
0.09
0.04
0
0 0.125 0.25 0.375 0.5
Duty cycle (δ)

Fig 3.49. Semiconductor utilization factor of the push-pull isolated-boost converter.
As transistors S1 and S2 conduct the same current, their average power losses are the
same. This is also applicable to output side rectifier diodes D1-D2-D3-D4. Therefore,
power losses expressions are calculated just for one semiconductor in each group. The
semiconductor power losses depend on conduction power losses of Eq. (3.1) and
switching power losses of Eq. (3.2). Table 3.24 summarizes the current expressions
(average, rms and switched currents) as well as the switched voltage expressions required
to calculate the mentioned power losses.
Thus, average conduction power losses of transistor S1 (Pcond_S1) and diode D1 (Pcond_D1)
are given by:
I in 
+ rd ⋅  I in 2 ⋅
(1 − δ ) + δ ⋅  ∆iLm 2 + ∆iL12  +  1 − δ  ⋅ ∆iL12 
 2
  (3.170)
2  2  6   2  3 
 n1 
2
 n  (∆i + ∆i L1 )2   1
2
 ⋅  − δ 
I out
Pcond _ D1 = Vth ⋅ + rd ⋅  I in ⋅  +  1  ⋅ Lm (3.171)
2  n3   n3  3  2 
 
where rd and Vth are each semiconductor's on-state resistance and threshold voltage.
110
TABLE 3.24
Current and
Diodes
voltage Transistors S1-S2
D1-D2-D3-D4
expressions
Average current I in I out

(Iave) 2 2
 2 (1 − δ )  ∆i 2 ∆i 2  
 I in ⋅ + δ ⋅  Lm + L1  +
 n   n  (∆iLm + ∆iL1 )2   1
2 2
 2  2 6  
rms current (Irms)    I in ⋅ 1  +  1  ⋅  ⋅  − δ 
  
    3  2
 1  ∆iL1
2

n3   n3  
 
+  2 − δ  ⋅ 3 
   
Maximum current
(imax)
(I in + ∆iL1 ) (I in + ∆i L1 + ∆i Lm ) ⋅ n1
n3
Turn-on switched (I in − ∆i L1 − ∆i Lm )
current (ion) −
2
Turn-off switched (I in + ∆i L1 + ∆i Lm ) (I in − ∆i L1 − ∆i Lm ) ⋅ n1
current (ioff) 2 n3
2 ⋅ (Vout + ∆v Cout ) ⋅
Maximum voltage n1
(vmax)
(Vout + ∆vCout )
n3
2 ⋅ (Vout + ∆v Cout ) ⋅
Turn-on switched n1
voltage (von) −
n3
Turn-off switched
2 ⋅ (Vout − ∆v Cout ) ⋅
n1 (Vout + ∆v Cout )
voltage (voff) n3 2
In turn, average switching power losses of the transistor S1 (Psw_S1) and diode D1 (Psw_D1)
are provided by:
n1   (I + ∆iL1 + ∆iLm )  
2
2 ⋅ (Vout − ∆vCout ) ⋅ A
, 1 ⋅  in  + 
n3  off S
 2  
Psw _ S1 = ⋅ +
Tsw ⋅ V100 FIT
+ B ( I in + ∆iL1 + ∆iLm )
+ Coff , S1 
 off , S1 ⋅
 2 
(3.172)
  (I in − ∆iL1 − ∆iLm )  
2
2 ⋅ (Vout + ∆vCout ) ⋅ 1
n
A  + 
on, S1 ⋅ 
n3   2  
+ ⋅
Tsw ⋅ V100 FIT
+ B ⋅
(Iin − ∆iL1 − ∆iLm ) + C 
 on, S1 on, S1 
 2 
  n1 
2 
A ⋅  (I in − ∆iL1 − ∆iLm ) ⋅  +
  
(Vout + ∆vCout )  off , D1
 n3  
Psw _ D1 = ⋅  (3.173)
2 ⋅ Tsw ⋅ V100 FIT  
 + Boff , D1 ⋅ (I in − ∆iL1 − ∆iLm ) ⋅ n + Coff , D1 
n1
 3 
111
switch and Aon,S1, Bon,S1 and Con,S1 are transistors' turn-on energy loss characteristic
coefficients.
2.2.12 Half-bridge
The half-bridge converter is a unidirectional converter derived from buck converter. As it

can be noticed in Fig 3.50, the converter is composed of two series connected input
capacitors (Cin1 and Cin2), two transistors (S1-S2), a medium frequency transformer (in
which the leakage inductances have been neglected), a diode bridge (D1-D2-D3-D4) and a
LC filter at the output (inductor L1 and capacitor Cout).
Iin
+ +
L1 I
- out
+ iCin1 +
Cin1 S2 iL1
- n1 : n2 D1 D3
iLm + +
Vin Lm Cout Vout
iCin2 - - iCout
+ D4 D2
Cin2 S1
- -
-
Fig 3.50. Half-bridge converter.
As it can be noticed in Fig 3.51, the half-bridge converter operates alternating the
switching orders of the transistors S1 and S2. Thus, when transistor S1 is on (Ton time
interval), transistor S2 is off (cf. Fig 3.51a). During this time interval, the input current
(Iin) flows through the upper capacitor Cin1 and the energy coming from input as well as
the energy stored in the lower capacitor Cin2 are transferred to the output and the inductor
L1. At the same time, the inductance Lm is magnetized positively. After this Ton time
interval, transistor S1 is turned-off and the input current circulates through the two input
side capacitors while the load is supplied by the output side inductor L1 (Toff time interval
illustrated in Fig 3.51b). During this time interval, the current through the magnetizing
inductance remain constant and circulates through the diodes of the output side rectifier.
When transistor S2 is turned-on (cf. Fig 3.51c) a second Ton time interval begins. Thus, the
input current circulates through the lower capacitor Cin2 and the energy coming from the
input as well as the energy stored in the upper capacitor Cin1 are transferred to the load
and the inductor L1.
The voltage of each input capacitor is half of the DC bus voltage. Thus, the voltage
applied to the MFT is half of the DC bus voltage (cf. Fig 3.52a). As a consequence, the
current through the input side of the converter is higher than that of the converters where
the entire DC bus voltage is applied to the transformer.
112
It must be highlighted that the leakage and magnetizing inductances of the MFT and the
input capacitors of the converter conform a resonant circuit. So, in order to avoid
undesired current and voltage oscillations, this phenomena must be taken into account in
the design and the selection of the switching frequency of the converter.
+ L1
+
Cin1 S2
n1 : n2 D1 D3 Iout
Vin Lm Cout Vout
Cin2 S1 D4 D2
I- in -
a)
+ L1
+
Cin1 S2
n1 : n2 D1 D3 Iout
Vin Lm iLm Cout Vout
Cin2 S1 D4 D2
Iin -
-
b)
+ L1 Iout
+
Cin1 S2
n1 : n2 D1 D3 Iout
Vin Lm Cout Vout
Cin2 S1 D4 D2
Iin -
-
c)
Fig 3.51. Currents circulating through the half-bridge converter a) when S1 is on and
S2 is off, b) when S1-S2 are off and c)when S1 is off and S2 is on.
Considering a continuous current mode operation and neglecting input and output voltage
ripple, the waveforms in the converter derived from this operation are illustrated in Fig
3.52. Fig 3.52a shows, the utilization of the transformer is good as it is magnetized
bidirectionally. However, the Ton time interval cannot be higher than half of the switching
period (Tsw/2), otherwise, the transformer core will be saturated, Eq. (3.174). Thus, the
control scheme in the converter must avoid the transformer's core saturation.
Tsw 1
Ton,max = → δ max = (3.174)
2 2
Assuming the average voltage applied to inductor L1 within a switching period is zero, the
DC voltage transfer function can be derived from the waveforms of Fig 3.52b:
n2
Vout = Vin ⋅ δ ⋅ (3.175)
n1
cycle of the converter and n2/n1 is the turn ratio of the MFT (cf. Fig 3.50).
113
D1-D2-D3-D4 D1-D2-D3-D4
iLm S1 & D1-D2 Conducting iL1 Conducting
Conducting
ΔiLm ΔiL1
Tsw Iout
-ΔiLm t
Ton Toff Ton Toff S2 & D3-D4 Ton Toff Ton Toff
Conducting
S1 & D1-D2 S2 & D3-D4
vLm Conducting Conducting
vL1
Tsw Tsw t
Vin 2
2
n2 Vin
-Vout
n1 2
x π
π]
t
π
π]
-
Vin t
2
- Vout
a) b)
Fig 3.52. Typical voltage and current waveforms in half-bridge converter's a) Lm

magnetizing inductance and b) inductor L1.
Moreover, assuming ideal operation with no losses, the DC current transfer function is
given by:

 I n
n 2  → I out =in ⋅ 1 (3.176)
V
= Vin ⋅ δ ⋅ δ n2
n1 
out

On the other hand, the inductances of Lm and L1 can be derived from the waveforms in
Fig 3.52:
∆t Vin
Lm v Lm ⋅
= = ⋅ δ ⋅ Tsw (3.177)
∆i 4 ⋅ ∆i Lm
∆t V
L1 vL1 ⋅
= = out ⋅ (1 − 2 ⋅ δ ) ⋅ Tsw (3.178)
∆i 4 ⋅ ∆iL1
iCin2
QCin iCout
Iin QCout
ΔiL1
Iin+ΔiLm-(Iout-ΔiL1)
n2 t -ΔiL1 t
n1
Ton Toff
n2 Tsw
Iin-ΔiLm-(Iout+ΔiL1)
n1 2
Ton 2·Toff +Ton
Tsw
a) b)
capacitor of the half-bridge converter.
114
The current flowing in each input DC bus capacitor is the same and in consequence, their
capacitance is equal. Under the assumption of constant input and output currents (Iin and
Iout), the currents through input and output capacitors can be depicted as in Fig 3.53.
Thus, from Fig 3.53a, the capacitance of the lower capacitor Cin2 is derived:
QCin 2 I in ⋅ (Tsw − Ton )
C in 2 = = (3.179)
∆v 2 ⋅ ∆v Cin 2
where ∆vCin2 is the half of the desired peak to peak voltage ripple in the capacitor Cin2.
The capacitance of Cout is obtained similarly from Fig 3.53b:
QCout ∆i L1
C out = = ⋅ Tsw (3.180)
where ∆vCout is the half of the desired peak to peak voltage ripple in the output.
Table 3.25 summarizes the expressions of the maximum energy stored by the passive
elements, their maximum voltage stress and the rms currents circulating through them.
These expressions are derived from the waveforms of Fig 3.52 and Fig 3.53.
TABLE 3.25

Element rms current
energy stress
2
1 V   Vin 
Cin2 ⋅ C in ⋅  in + ∆vCin 2  δ ⋅ χ + (1 − δ ) ⋅ I in 2  + ∆vCin 2 
2  2   2 
1 4 ⋅δ  Vin 
Lm ⋅ Lm ⋅ ∆i Lm 2 ∆i Lm ⋅ 1 −  + ∆vCin 2 
2 3  2 
1
⋅ L1 ⋅ (I out + ∆i L1 )2 ∆iL12 (Vout + ∆vCout )
L1 I out 2 +
2 3
1 ∆i L1
2 3
  
2 
 n
 ∆i L1 ⋅ 2 + ∆i Lm  
 2 
n 
χ =   I in − I out ⋅ 2  +  
n1

 n1  3 
 
 
 
At last, derived from the maximum voltage and rms current expressions of Table 3.26, the
semiconductor utilization factor (Uf) is given by:
PRated δ
Uf = = (3.181)
∑all _ switches v max ⋅ I rms 2 ⋅ δ + 1− 2 ⋅δ
115
As it can be noticed, this semiconductor utilization factor is same as that presented for the
push-pull converter (section 3.2.10). Therefore, the higher the duty cycle the better the
semiconductor utilization (cf. Fig 3.44). Hence, the chosen turn ratio of the transformer
must ensure that the converter operates with high duty cycles close to 0.5.
As mentioned in the beginning of section 3.2, semiconductor power losses are estimated
by Eq. (3.1) and Eq. (3.2). In order to estimate these losses, the expressions of the
currents and voltages in the semiconductors are outlined in Table 3.26. Provided that the
currents circulating through the transistors are the same and that the currents circulating
through the output diodes are the same, power losses are calculated only for one
semiconductor in each group.
TABLE 3.26

Transistors S1-S2
I out
Average current (Iave) I in
2
 2   2
1  ∆iL1 
2
 2
 n 
 ∆iLm + ∆iL1 ⋅ 2   (1 + 2 ⋅ δ ) ⋅  I out  + ⋅  +
 n2   n1    2  3  2  
rms current (Irms)  I out ⋅  +  ⋅δ
 n1  3 
2
 ∆i n 
  + (1 − 2 ⋅ δ ) ⋅  Lm ⋅ 1 
   2 n2 
 
Maximum current (imax)  (I out + ∆i L1 ) ⋅ 2 + ∆i Lm 
n
(I out + ∆i L1 )
 n 1 
 
 (I out − ∆i L1 ) ⋅ 2 − ∆i Lm 
n
Turn-on switched current (ion) −
 n1 
Turn-off switched current (ioff)

 
 (I out + ∆i L1 ) ⋅ 3 + ∆i Lm 
n (I out − ∆i L1 )
 n1  2
 Vin  n
Maximum voltage (vmax) ≈ (Vin + ∆v Cin 2 )  + ∆v Cin 2  ⋅ 2
 2  n1
 Vin 
Turn-on switched voltage (von)  + ∆v Cin 2  −
 2 
 Vin   Vin  n2
Turn-off switched voltage (voff)  2 − ∆v Cin 2   2 + ∆v Cin 2  ⋅ n
    1
116
Consequently, average conduction power losses of transistor S1 (Pcond_S1) and diode D1

(Pcond_D1) are given by:
  n  
2
  ∆i Lm + ∆i L1 ⋅ 2  
n 2  
2
 n1  
Pcond _ S1 = Vth ⋅ I in + rd ⋅  I out ⋅  +  ⋅δ (3.182)
 n1  3 
 
 
I out
Pcond _ D1 = Vth ⋅ +
2
 (3.183)
 ∆i Lm n1  
2
 I  2 1  ∆i  2 
+ rd ⋅ (1 + 2 ⋅ δ ) ⋅ 
 out
 + 3 ⋅  2   + (1 − 2 ⋅ δ ) ⋅  2 ⋅ n  
L1
 
  2      2 
 
where rd is the on-state resistance and Vth is the threshold voltage.
Moreover, average switching power losses of the transistor S1 (Psw_S1) and diode D1
(Psw_D1) are given by:
  
2 
 Vin  A  ( ) n2
 
 − ∆v ⋅
Cin 2   off , S1  out
I + ∆i L1 ⋅ + ∆i Lm  + 
2
Psw _ S1 =   ⋅  
n1
+
Tsw ⋅ V100 FIT    
 + Boff , S1 ⋅  (I out + ∆iL1 ) ⋅ + ∆iLm  + Coff , S1 
n2
  n1  
(3.184)
  
2 
 Vin  A  ( ) n2
 
 ⋅
+ ∆vCin 2   on, S1  out I − ∆i L1 ⋅ − ∆i Lm  + 
2
+  ⋅  
n1

Tsw ⋅ V100 FIT    
 + Bon, S1 ⋅  (I out − ∆iL1 ) ⋅ − ∆iLm  + Con, S1 
n2
  n1  
 Vin  n
 + ∆vCin 2  ⋅ 2
Psw _ D1 =  2  n1  (I − ∆iL1 )2 + B ⋅ (I out − ∆iL1 ) + C 
⋅  Aoff , D1 ⋅ out (3.185)
Tsw ⋅ V100 FIT  4
off , D1
2
off , D1 
 
the transistors.
2.2.13 Half-bridge isolated-boost
The half-bridge isolated-boost converter is a unidirectional converter derived from boost

type converters (cf. Fig 3.54). The converter is formed of two transistors (S1-S2) and a DC
bus capacitor (Cin) at the input side, a medium frequency transformer (MFT) and a diode
rectifier (D1-D2-D3-D4) as well as a capacitor (Cout) at the output side.
117
Iin
+ Iout
iL1 + iL2 + +
L1 L2
- - n1 : n2 D1 D3
+ iLm + +
- - - iCout
iCin
D4 D2
S1 S2 -
-
Fig 3.54. Half-bridge isolated-boost converter.
The operation of the converter is based on alternating the transistors commands as

illustrated in Fig 3.55. When transistors S1 and S2 are on (ton time interval), the energy
coming from the input is stored in the inductors L1 and L2 (cf. Fig 3.55a). In turn, zero
voltage is applied to the MFT and in consequence, the current through the magnetizing
inductance is constant. This current circulates through the transistors. During this ton time
interval, the load is supplied by the output capacitor Cout.
+
+
L1 L2
n1 : n2 D1 D3 Iout
D4 D2
Iin S1 S2 -
-
a)
+
+
L1 L2
n1 : n2 D1 D3 Iout
D4 D2
Iin S1 S2 -
-
b)
+
+
L1 L2
n1 : n2 D1 D3 Iout
D4 D2
Iin S1 S2 -
-
c)
Fig 3.55. Currents circulating through the half-bridge isolated-boost converter a)
when S1 and S2 are on, b) when S1 is off and S2 is on, and c) when S1 is on and S2 is
off.
Then, transistor S1 is turned-off and Toff time interval begins (cf. Fig 3.55b), where the
energy stored in L1 is transferred to the output while the transformer is magnetized
118
positively. Inductor L2 continues storing energy. When transistor S1 is turned-on the

second ton period of time begins (cf. Fig 3.55a). This time interval finishes when transistor
S2 is turned-off and the second Toff time interval begins (cf. Fig 3.55c). During the second
Toff, the energy stored by inductor L2 is transferred to the output and L1 continues storing
the energy coming from the input. Meanwhile, the transformer is magnetized negatively.
From this operational behaviour, it can be deduced that the on-state time interval (Ton) of
each transistor is given by Eq. (3.186). Furthermore, this time interval must be always
higher than Tsw/2, which leads to the minimum duty cycle value given by Eq. (3.187).
Ton = 2 ⋅ t on + Toff = Tsw − Toff (3.186)
Tsw 1
Ton, min = → δ min = (3.187)
2 2
where Tsw is the switching period of the transistors and δmin is the minimum duty cycle of
the converter (Ton,min/Tsw).
The leakage inductance of the MFT has been neglected in this analysis (cf. Fig 3.54 and
Fig 3.55). Nevertheless, this leakage inductance has to be considered in real cases. The
described operation interrupts the current circulating through the leakage inductance and
in consequence, in real cases, the voltage in the leakage inductance will raise leading to
overvoltages in the transistors. To avoid these overvoltages, the use of snubber circuits
must be taken under consideration.
The waveforms derived from the afore described operational behaviour are depicted in
Fig 3.56. For simplicity, voltage ripple have been neglected in the waveforms related to
the magnetic elements while current ripple have been neglected in the waveforms related
to the output capacitor. As it can be deduced from Fig 3.56a, the transformer is
magnetized bidirectionally, thereby leading to a good utilization of it. Moreover, even
though the waveform shows no DC current is injected, a control scheme is required in
order to avoid transformer saturation.
On the other hand, the DC voltage transfer function is obtained from the waveforms of
Fig 3.56b:
Vin n2
Vout = ⋅ (3.188)
1 − δ n1
cycle of the converter and n1 and n2 are the number of turns of the primary and secondary
windings of the MFT respectively (cf. Fig 3.54).
The DC current transfer function is derived from the steady state analysis of the
waveforms in Fig 3.56d:
n1
I out = (1 − δ ) ⋅ I in ⋅ (3.189)
n2
119
S2 & D1-D2 S1 & D3-D4 S2 & D1-D2 S1 & D3-D4

Conducting Conducting iL1 Conducting Conducting
iLm S1-S2
Conducting
S1-S2
Conducting
Iin ΔiL1
ΔiLm
Tsw 2
Ton
- ΔiLm t ton Toff ton Toff ton
ton Toff ton Toff S1-S2 S1-S2 S1-S2
Conducting Conducting Conducting
vLm vL1
Tsw (Tsw+ ton) t
2
n1 Vin
V
n2 out
π
π]
t
t
n1
- V
n2 out n1
Vin - V
n2 out
a) b)
S2 & D1-D2 S1 & D3-D4 vCout

iL2 Conducting Conducting
ΔvC1
Iin ΔiL2 Vout
2
Ton
Toff
ton Toff ton
ton Toff ton Toff
S1-S2 S1-S2
Tsw Tsw t iCout Tsw Tsw t
vL2 2 2
n1 Iin
Vin - Iout
n2 2
π
π]
t t
n1
Vin - V - Iout
n2 out
c) d)
Fig 3.56. Typical voltage and current waveforms in half-bridge isolated-boost

converter's a) magnetizing inductance Lm, b) inductor L1, b) inductor L2 and c)
capacitor Cout.
The inductances of the input side inductors L1 and L2 are derived from the steady state
analysis of their respective waveforms of Fig 3.56b and Fig 3.56c, while the value of the
magnetizing inductance is obtained from Fig 3.56a:
∆t Vin
L1 vL1 ⋅
= = ⋅ δ ⋅ Tsw (3.190)
∆i 2 ⋅ ∆iL1
∆t Vin
L2 v L 2 ⋅
= = ⋅ δ ⋅ Tsw (3.191)
∆i 2 ⋅ ∆i L 2
∆t Vout n
L m v Lm ⋅
= = ⋅ 1 ⋅ (1 − δ ) ⋅ Tsw (3.192)
∆i 2 ⋅ ∆i Lm n 2
where ∆iL1, ∆iL2 and ∆iLm are respectively the current ripple in L1, L2 and Lm.
120
Similarly, Cout capacitance is derived from Fig 3.56d:
∆t
= out ⋅ (2 ⋅ δ − 1) ⋅ Tsw
I
Cout = iCout ⋅ (3.193)
∆v 4 ⋅ ∆vC1
where ∆vCout is the output voltage ripple.

The current through the input capacitor Cin is determined by the current ripple in L1 and
L2. Assuming the current ripple ∆iL1 and ∆iL2 are equal and considering the input current
Iin is constant, the maximum current through the input capacitor is:
 1  1
∆iin = ∆iL1 ⋅  2 −  = ∆iL 2 ⋅  2 −  (3.194)
 δ   δ 
Therefore, the input DC bus capacitance (Cin) is determined by the charges QCin illustrated
in Fig 3.57:
QCin ∆iin ∆i L1  1
C in = = ⋅ Tsw = ⋅  2 −  ⋅ Tsw (3.195)
∆v 8 ⋅ ∆v Cin 16 ⋅ ∆v Cin  δ
iCin
QCin
Δiin
-Δiin t
ton Toff
Tsw
2
Fig 3.57. Current through the input capacitor of the half-bridge isolated-boost
converter.
Table 3.27 summarizes the expressions of the maximum energy stored by the passive
elements, their maximum voltage stress and the rms currents circulating through them.
These expressions can be derived from the waveforms in Fig 3.56 and Fig 3.57.
From the maximum voltage and rms current expressions of Table 3.28, the semiconductor
utilization factor (Uf) of the half-bridge isolated-boost converter is:
PRated 1−δ
Uf = = (3.196)
∑all _ switches vmax ⋅ I rms 2 ⋅ 1− δ + 3 − 2 ⋅δ
121
TABLE 3.27
Maximum stored
Element rms current
energy Maximum voltage stress
1 ∆iin
2 3
1 4 ⋅δ −1
Lm ⋅ Lm ⋅ ∆i Lm 2 ∆i Lm ⋅ (Vout + ∆vCout ) ⋅ n1
2 3 n2
2 2 2
1 I   I in  ∆iL1  n 
L1 ⋅ L1 ⋅  in + ∆i L1    + ≈ Vin − (Vout + ∆vCout ) ⋅ 1 
2  2   2 3  n2 
2 2 2
1 I   I in  ∆iL 2  n 
L2 ⋅ L 2 ⋅  in + ∆i L 2    + ≈ Vin − (Vout + ∆vCout ) ⋅ 1 
2  2   2 3  n2 
(2 ⋅ δ − 1) ⋅ I out 2 +
1
Cout ⋅ Cout ⋅ (Vout + ∆vCout )2 I n 
2 (Vout + ∆vCout )
2 + 2 ⋅ (1 − δ ) ⋅  in ⋅ 1 − I out 
 2 n2 
In order to determine the operational point at which the utilization factor is maximized
(i.e. the installed semiconductor power is the minimum), Eq. (3.196) is depicted in Fig
3.58 for different duty cycles. As it can be noticed, the lower the duty cycle the better the
semiconductor utilization. In consequence, n2/n1 turn ratio must be that which guarantees
the operation of the converter with duty cycle values close to 0.5.
0.18
0.13
0.09
0.04
0
0.5 0.625 0.75 0.875 1
Duty cycle (δ)

Fig 3.58. Semiconductor utilization factor of the half-bridge isolated-boost converter.
Assuming ideal passive elements with no losses, the power losses of the converter are
given by the semiconductor power losses. In turn, semiconductor power losses depend on
conduction power losses of Eq. (3.1) and switching power losses of Eq. (3.2). To estimate
122
these losses, average and rms currents through the semiconductors must be known along
with the switched currents and voltages. Furthermore, the maximum current through them
and the maximum voltage they must block determine the required semiconductor. Once
the semiconductor is selected, the on-state as well as the switching characteristics are
determined.
Aforementioned expressions are summarized in Table 3.28 and can be deduced from Fig
3.56. The expressions of transistors are the same because they conduct the same current.
Similarly, the expressions of diodes are the same because they conduct the same current.
TABLE 3.28

Transistors S1-S2
I in I out
2 2
 I 
2
n  (∆iLm + ∆iL1 )2 
2
 ⋅ (1 − δ )
n
rms current (Irms) χ  in ⋅ 1  + 1  ⋅
 2 n2  n  3 
   2  
 I in  n
Maximum current (imax) (I in + ∆iin )  + ∆i L1 + ∆i Lm  ⋅ 1
 2  n2
 I in 
Turn-on switched current (ion)  − ∆i L1 − ∆i Lm  −
 2 
 I in   I in  n
Turn-off switched current (ioff)  + ∆i L1 + ∆i Lm   − ∆i L1 − ∆i Lm  ⋅ 1
 2   2  n2
Maximum voltage (vmax) (Vout + ∆vCout ) ⋅ n1 (Vout + ∆vCout )

n2
Turn-on switched voltage (von) (Vout + ∆vCout ) ⋅ n1 −

n2
Turn-off switched voltage (voff) (Vout − ∆vCout ) ⋅ n1 (Vout + ∆v Cout )

n2 2

χ =  I in 2 ⋅
(3 − 2 ⋅ δ ) + (∆i ) ⋅  1 − 2  + ∆iLm 2 ⋅ (2 ⋅ δ − 1) + ∆iL1
2
 2 
⋅  5 − − 2 ⋅ δ 
L1 ⋅ ∆iLm
 4 δ  3  δ 
From Table 3.28 and Eq. (3.1), average conduction power losses of transistor S1 (Pcond_S1)
and diode D1 (Pcond_D1) are:
 2 (3 − 2 ⋅ δ ) 1  
 I in ⋅ + (∆iL1 ⋅ ∆iLm ) ⋅  − 2  + ∆iLm 2 ⋅ (2 ⋅ δ − 1) + 
4 δ 
Pcond _ S1 = Vth ⋅ in + rd ⋅  
I
 2  (3.197)
2 ∆iL1  2 
+ ⋅ 5 − − 2 ⋅δ  
 3  δ  
123
 n   n  (∆i + ∆iL1 )2 
2 2
 ⋅ (1 − δ )
I out
Pcond _ D1 = Vth ⋅ + rd ⋅  I in ⋅ 1  +  1  ⋅ Lm (3.198)
2  n2   n2  3 
 
respectively.
From Table 3.28 and Eq. (3.2), average switching power losses of transistor S1 (Psw_S1)
and diode D1 (Psw_D1) are:
  I in 
2 
(Vout − ∆vCout ) ⋅ n1 A
off , S1 ⋅  + ∆iL1 + ∆iLm  + 
n2   2  
Psw _ S1 = ⋅ +
Tsw ⋅ V100 FIT + B  I in  
 off , S1 ⋅  2 + ∆iL1 + ∆iLm  + Coff , S1 
   
(3.199)
  I in 
2 
(Vout + ∆vCout ) ⋅ n1 A
on , S1 ⋅  − ∆iL1 − ∆iLm  + 
n2   2  
+ ⋅ 
Tsw ⋅ V100 FIT + B  I in  
 on, S1 2 ⋅  − ∆i L1 − ∆i Lm  + C on , S1 
   
   I in
2 
A  n1  
⋅   − ∆ i − ∆i  ⋅  +
(Vout + ∆vCout ) 
off , D1 
  2
L1 Lm
 n2  
Psw _ D1 = ⋅  (3.200)
2 ⋅ Tsw ⋅ V100 FIT   I in  n1 
 + Boff , D1 ⋅  − ∆iL1 − ∆iLm  ⋅ + Coff , D1 
  2  n2 
switch and Aon,S1, Bon,S1 and Con,S1 are transistors' turn-on energy loss characteristic
coefficients.
2.2.14 Full-bridge
The full-bridge converter of Fig 3.59 is a unidirectional step-down type converter. The
converter is composed of a DC bus filter capacitor (Cin) and a H-bridge converter (S1-S2-
S3-S4) at the input side. The H-bridge converter is connected through a medium frequency
transformer to the diode bridge (D1-D2-D3-D4) and the output side LC filter (inductor L1
and capacitor Cout).
Iin
+ + L1 -
Iout
DS1 DS3
S1 S3 iL1 +
Lσ - n1 : n2 D1 D3
+
+ iLσ +
Vin Cin Cout Vout
- iCin -
iCout
D4 D2
S4 S2 -
DS4 DS2
-
Fig 3.59. Full-bridge converter.
124
For the converter design a phase-shifted pulse width modulation technique has been
considered. As it can be observed in Fig 3.60, each transistor is on during half of the
switching period (Tsw/2). The switching orders of transistors S1and S4, and transistors S2
and S3 are complementary. Furthermore, the commands of transistors S1-S4 are phase-
shifted (φ) to that of transistors S2-S3. This way, three different voltage levels (-Vin, 0, Vin)
are applied to the primary side winding of the medium frequency transformer.
Tsw Tsw
2 2
Ton Toff
S1
S4
S2
S3
φ
Fig 3.60. Switching orders in the full-bridge converter.
Hence, when S1-S2 are on and S3-S4 are off (ton time interval), the energy coming from the
input and the energy stored in Cin capacitor are transferred to the leakage inductance of
the MFT (Lσ), the output inductor (L1) and the load (cf. Fig 3.61a). Then, S2 is turned-off
while S3 is turned-on (cf. Fig 3.61b). During this time interval (Toff), the energy coming
from the input is stored in Cin and zero voltage is applied to the MFT. Thus, the output
load is supplied by the leakage inductance and the inductor L1. Subsequently, S1 is turned-
off and S4 is turned-on (cf. Fig 3.61c). Therefore, input voltage is applied to the leakage
inductance and the current circulating through it flows through the freewheel diodes DS3
and DS4. The energy stored in the leakage inductance is transferred to the input side
capacitor along with the energy coming from the input. Meanwhile, the load is supplied
by L1. When the current sense in the MFT is inverted (cf. Fig 3.61d), transistors S3-S4 start
conducting current and the energy stored in the capacitor Cin and the energy coming from
the input are transferred to Lσ, L1 and the load (second ton time interval). Next, S3 is
turned-off while S2 is turned-on and during a Toff time interval (cf. Fig 3.61e), Cin stores
the energy coming from the input while the output load is supplied by the leakage
inductance and the output side inductor. During this time interval, zero voltage is applied
to the MFT. Last, S4 is turned-off and S1 is turned-on (cf. Fig 3.61f). While the current
through the leakage inductance remains negative, input voltage is applied to the leakage
inductance and the current flows through the freewheel diodes DS1 and DS2. Therefore, the
energy coming from the input as well as the energy stored in the leakage inductance are
transferred to the input side capacitor. The load is supplied by the output side inductor.
125
+ L1 + L1
DS1 DS3 DS1 DS3
S1 S3 + S1 S3 +
Lσ n1 : n2 D1 D3 Iout Lσ n1 : n2 D1 D3 Iout
Vin Cin Cout Vout Vin Cin Cout Vout
D4 D2 D4 D2
Iin S4 S2 - Iin S4 S2 -
DS4 DS2 DS4 DS2
- -
a) b)
+ L1 + L1
DS1 DS3 DS1 DS3
S1 S3 + S1 S3 +
Iout Iout
Lσ n1 : n2 D1 D3 Lσ n1 : n2 D1 D3
Vin Cin iLσ Cout Vout Vin Cin Cout Vout
D4 D2 D4 D2
S4 S2 - S4 S2 -
Iin DS4 DS2 Iin DS4 DS2
- -
c) d)
+ L1 + L1
DS1 DS3 DS1 DS3
S1 S3 + S1 S3 +
Iout Iout
Lσ n1 : n2 D1 D3 Lσ n1 : n2 D1 D3
Vin Cin iLσ Cout Vout Vin Cin iLσ Cout Vout
D4 D2 D4 D2
S4 S2 - S4 S2 -
Iin DS4 DS2 Iin DS4 DS2
- -
e) f)
Fig 3.61. Currents circulating through the full-bridge converter a) when S1-S2 are on
and S3-S4 are off, b) when S1-S3 are on and S2-S4 are off, c) when S3-S4 are on and S1-
S2 are off (the current circulates through the freewheel diodes DS3-DS4), d) when S3-S4
are on and S1-S2 are off, e) when S4-S2 are on and S1-S3 are off, and f) when S1-S2 are
on and S3-S4 are off (the current circulates through the freewheel diodes DS1-DS2).
In a continuous current mode operation, the waveforms derived from the afore described
operation are illustrated in Fig 3.62. As it can be noticed in Fig 3.62a, the current through
the transformer is alternating. So, the magnetization of the transformer is bidirectional,
thereby leading to a good utilization of the element. However, in order to prevent the
saturation of the transformer, a control strategy must be considered to guarantee that the
average voltage applied to the MFT is zero.
During the time interval Toff at which zero voltage is applied to the MFT (cf. Fig 3.61b
and Fig 3.62a), the leakage inductance is in series with the output inductor. Hence, part of
the output voltage drops over the leakage inductance until non-complementary transistors
(S1-S2 or S3-S4) are on (end of Toff time interval). The voltage drop in the leakage
inductance during Toff (Vs) and the current through it at the end of Toff (Is) are respectively
approached as:
Vout ⋅ Lσ
Vs = 2
n  (3.201)
Lσ ⋅  2  + L1
 n1 
n2  V ⋅ (0.5 − δ ) ⋅ Tsw 
Is = ⋅  I out + ∆i L1 − s 
 (3.202)
n1  Lσ 
where Vout is the average output voltage, n2/n1 is the turn ratio of the MFT, Iout is the
average output current (cf. Fig 3.59), ∆iL1 is the current ripple in L1 (cf. Fig 3.62b), Tsw is
the switching frequency and δ is the duty cycle of the converter (Ton/Tsw).
126
iLσ
n2
n1 (Iout+∆iout)
Is S1-DS3 Conducting
n2 DS2-DS1 Conducting DS3-DS4 Conducting
n1 (Iout-∆iout) S4-DS2 Conducting S1-S2 Conducting
-nn1 (Iout-∆iout)
2 S3-S4 Conducting Tsw
Tsw
t
2
-Is ta ta
n
- 2 (Iout+∆iout) ton toff ton toff
n1
vLσ Toff Ton
Vin
Vs
Vin- n
n2 Vout
1
n1 V )
-(Vin- n
2
out t
-Vs
-Vin
a)
iL1 D1-D2-D3-D4
Conducting
Iout ΔiL1
Toff Toff
ton toff ton toff
D3-D4 D1-D2
vL1
Tsw Tsw t
2
n2
n1 Vin-Vout
y=-sinx, x∊
x∊[0,2
[0,2π
π]]
π
t
Vs-Vout
-Vout
b)
Fig 3.62. Typical voltage and current waveforms in full-bridge converter's a) leakage
inductance Lσ and b) inductor L1.
When non-complementary transistors are on, there is a time interval (toff-Toff) at which all
the DC bus voltage (Vin) is applied to the leakage inductance (cf. Fig 3.62a). In
consequence, the energy coming from the input is used to invert the polarity of the
current through Lσ. This results in a reduction of the duty cycle of the converter:
t on Ton − (t off − Toff )  2 ⋅ I out n 2 

δ eff = = = δ − Lσ ⋅  ⋅  (3.203)
Tsw Tsw  Vin ⋅ Tsw n1 
where Ton is the time interval at which non-complementary transistors are on (cf. Fig
3.60), toff is the time interval at which the energy coming from the input side is not
127
transferred to the output (cf. Fig 3.62) and Vin and Iin are respectively average input DC
voltage and average input current (cf. Fig 3.59).
Therefore, the DC voltage transfer function derived from steady state analysis of the
waveforms of Fig 3.62b is expressed in function of the effective duty cycle:
n2
Vout = 2 ⋅ Vin ⋅ δ eff ⋅ (3.204)
n1
If an ideal operation without losses is assumed (Pin=Pout), the DC current transfer function
is given by:

 I in n
n  → I out = ⋅ 1 (3.205)
Vout = 2 ⋅ Vin ⋅ δ eff ⋅ 2 2 ⋅ δ eff n 2
n1 
On the other hand, the value of the leakage inductance Lσ can be derived from Eq. (3.201)
while the value of the output side inductor L1 is obtained from the steady state analysis of
the waveforms in Fig 3.62b:
L1
Lσ = 2
 Vout

  n2  (3.206)
− 
 V  n
 s   1 
 n 
Vin ⋅ 2 − Vout 
∆t  n1  (3.207)
L1 = v L1 ⋅ = ⋅ δ eff ⋅ Tsw
∆i 2 ⋅ ∆i L1
Assuming input and output currents (Iin and Iout) are constant, the currents through input
and output capacitors can be illustrated as in Fig 3.63.
iCin
(Iin+Is) iCout
QCout
ΔiL1
Iin QCin
-ΔiL1 t
ton toff
t Tsw
Iin- n 2
n1 (Iout-∆iout) 2
Toff tb
Iin- n2 (Iout+∆iout) ton toff
n1
a) b)
capacitor of the full-bridge converter.
Therefore, calculating the charges circulating through the capacitors (grey colored areas)
the input DC bus capacitance (Cin) and the output capacitance (Cout) can be derived:
QCin 2 ⋅ I in ⋅ Toff + t b ⋅ (I in + I s )
C in = = (3.208)
∆v 4 ⋅ ∆v Cin
128
QCout ∆iL1
Cout = = ⋅ Tsw (3.209)
where ∆vCin and ∆vCout are respectively the half of the desired peak to peak voltage ripple
in the input and in the output, and tb is a time interval given by:
I in + I s
tb = (
⋅ t off − Toff )
n2
⋅ (I out − ∆i L1 ) + I s
(3.210)
n1
Additionally, from the waveforms of Fig 3.62 and Fig 3.63, the expressions of the
maximum energy stored by the passive elements, their maximum voltage stress and the
rms currents circulating through them are derived. These expressions are summarized in
Table 3.29.
TABLE 3.29

stress
1 2⋅χ
Cin ⋅ C in ⋅ (Vin + ∆v Cin )2
3 ⋅ Tsw
(Vin + ∆vCin )
2
2
1 n 
⋅ Lσ ⋅ (I out + ∆i L1 )2 ⋅  2  2 ⋅κ
Lσ 2  n1 
≈ (Vin + ∆v Cin )
3 ⋅ Tsw
1
⋅ L1 ⋅ (I out + ∆i L1 )2 ∆iL12 ≈ (Vout + ∆vCout )
L1 I out 2 +
2 3
1 ∆i L1
2 3
  
2
n 
2 
( ) n
 t off − Toff − t b ⋅  I in − 2 ⋅ (I out − ∆i L1 ) + t on
  ⋅  2 ⋅ ∆i L1  + 3 ⋅ Toff ⋅ I in 2 + t b ⋅ (I in + I s )2 + 
  n1   n1  
χ = 
2
  n2  
+ 3 ⋅ t on ⋅  I in − ⋅ I out  
  n1  
 2 2 
( n
)  n 
(
 toff − Toff − ta ⋅  2 ⋅ (I out − ∆iL1 ) + ton ⋅  2  ⋅ 3 ⋅ I out 2 + ∆iL12 + ta ⋅ I s 2
 n  n  ) +

 1   1
κ = 
2
  n2    
+ Toff ⋅  ⋅ (I out + ∆iL1 ) + Toff ⋅ I s ⋅  I s + ⋅ (I out + ∆iL1 )
n2

  1
n   n1  
where ta is given by:
ta =
Is
(
⋅ t off − Toff )
⋅ (I out − ∆i L1 ) + I s
n2
n1
129
Considering a very small leakage inductance it can be assumed that ton≈Ton. Under this
assumption and neglecting the current and voltage ripple in the expressions of Table 3.32,
the semiconductor utilization factor (Uf) is provided by:
PRated 2 ⋅δ
Uf = =
∑all _ switches v max ⋅ I rms 2 ⋅ ( 2 + δ + 1−δ + 2 ) (3.211)
This utilization factor is illustrated in Fig 3.64 for different duty cycle values. As it can be
noticed, the higher the duty cycle the better the semiconductor utilization. Therefore, in
order to minimize the installed semiconductor power in the converter, the n2/n1 turn ratio
must be carefully chosen to guarantee that the converter operates with duty cycles values
close to 0.5.
0.14
0.1
0.07
0.03
0
0 0.125 0.25 0.375 0.5
Duty cycle (δ)

Fig 3.64. Semiconductor utilization factor of the full-bridge converter.
Generally speaking, the power losses of the converters are given by the semiconductor
power losses, which can be estimated through Eq. (3.1) and Eq. (3.2), discussed at the
beginning of section 3.2.1.
As it can be noticed in Fig 3.62a, the current conducted by transistors S1-S4 is the same,
but differs from the current conducted by transistors S2-S3 (the current conducted by this
latter transistors is also the same). This also happens with their respective freewheel
diodes (DS1-DS4 and DS2-DS3). Conversely, the current through the diodes of the output
side diode bridge is the same (cf. Fig 3.62b). In consequence, power losses are calculated
for one semiconductor in each group (S1, S2, DS1, DS2 and D1). The tables below
summarize the expressions of the currents through the semiconductors as well as of the
voltages they block.
130
TABLE 3.30
EXPRESSIONS OF THE VOLTAGES/CURRENTS IN THE FREEWHEEL DIODES
Current and voltage Freewheel diodes

Freewheel diodes DS2-DS3
expressions DS1-DS4
I s ⋅ ta Is   (I + ∆i L1 ) n 2 
Average current (Iave) ⋅  t a + Toff ⋅ 1 + out ⋅ 

2 ⋅ Tsw 2 ⋅ Tsw 
  Is n1 
ta c
rms current (Irms) Is ⋅
3 ⋅ Tsw 3 ⋅ Tsw
Maximum current (imax) Is (I out + ∆i L1 ) ⋅

n2
n1
Maximum voltage (vmax) (Vin + ∆vCin ) (Vin + ∆vCin )

  n  n 
2 
c = t a ⋅ I s 2 + Toff ⋅  I s 2 + I s ⋅ (I out + ∆i L1 ) ⋅  2  + (I out + ∆i L1 )2 ⋅  2  
  
   n1   n1  
TABLE 3.31
EXPRESSIONS OF THE VOLTAGES/CURRENTS IN THE DIODE BRIDGE
Current and
Diodes
voltage
D1-D2-D3-D4
expressions

( (I out − ∆iL1 ) + ton ⋅ I out + Toff
)  n
⋅  I out + ∆iL1 + I s ⋅ 1
 t a ⋅ I s ⋅ n1 
+
Average current (Iave)  toff − Toff − t a ⋅  2 ⋅T ⋅ n 
 2 ⋅ Tsw Tsw 2 ⋅ Tsw  n2  sw 2
  3  
   I ⋅ n1  − (I + ∆i )3  
   s  out L1 

 t − T − t ⋅ (I out − ∆iL1 ) + off ⋅ 
2  n2 
(
 off off a ) 3 ⋅ Tsw
T
3 ⋅ Tsw 
 +

3
− (I out + ∆iL1 ) 
n1
rms current (Irms)   Is ⋅ 

  n2  

 ta  n1 
2
( 2
3 ⋅ I out + ∆iL1 2
) 

+ 3 ⋅ T ⋅  I s ⋅ n  + ton ⋅ 3 ⋅ Tsw 
 sw  2  
Maximum current
(imax)
(I out + ∆i L1 )
Maximum voltage
(vmax)
(Vin + ∆vCin ) ⋅ n 2
n1
131
TABLE 3.32
EXPRESSIONS OF THE VOLTAGES/CURRENTS IN THE TRANSISTORS
Current and
voltage Transistors S1-S4 Transistors S2-S3
expressions
  n  
 Toff ⋅  I out + ∆iL1 + I s ⋅ 1  

n2  I out ⋅ δ eff +
⋅

2 ⋅ Tsw
n2  
+ n2 
⋅  I out ⋅ δ eff +
(
(I out − ∆iL1 ) ⋅ toff − Toff − ta ) 
n1   2 ⋅ Tsw 
(
 (I out − ∆iL1 ) ⋅ toff − Toff − ta
 +
) 

n1  
 2 ⋅ Tsw 
 n2  a  n2  b
rms current (Irms)  ⋅  ⋅
n  3 ⋅ Tsw n  3 ⋅ Tsw
 1  1
Maximum current
(imax)
(I out + ∆i L1 ) ⋅
n2
(I out + ∆i L1 ) ⋅
n2
n1 n1
Turn-off switched
current (ioff)
Is (I out + ∆i L1 ) ⋅
n2
n1
Maximum voltage
(vmax)
(Vin + ∆vCin ) (Vin + ∆vCin )
Turn-off switched
voltage (voff)
≈ Vin (Vin − ∆vCin )

( ) 2
( 3 3 
 toff − Toff − t a ⋅ (I out − ∆iL1 ) + 2 ⋅ ∆i ⋅ (2 ⋅ ∆iL1 + I out − ∆iL1 ) − (I out − ∆iL1 ) + 
ton
)
 L1 
  2  
 
 I 3 ⋅  1  − (I + ∆i )3 ⋅ 2 
a= 
n n
  s n  out L1
n1  
+ T ⋅   2 
 
 off
 n2  
  I s − (I out + ∆iL1 ) ⋅  
 
  n1  

( )
b =  t off − Toff − t a ⋅ (I out − ∆i L1 )2 +
2 ⋅
t on
∆
( 
⋅ (2 ⋅ ∆i L1 + (I out − ∆i L1 ))3 − (I out − ∆i L1 )3  )
 i L1 
From Eq. (3.1) and the expressions in Table 3.30, Table 3.31 and Table 3.32, the
expressions of the average conduction power losses of transistors S1 (Pcond_S1) and S2
(Pcond_S2), freewheel diodes DS1 (Pcond_Ds1) and DS2 (Pcond_Ds2) and output diode D1 (Pcond_D1)
are given by:
  n  
 ⋅  I out + ∆iL1 + I s ⋅ 1  
n2 
Pcond _ S1 = Vth ⋅ ⋅  I out ⋅ δ eff +
Toff
 +
(
n2  (I out − ∆iL1 ) ⋅ toff − Toff − ta ) +

n1  2 ⋅ Tsw 2 ⋅ Tsw 
 
  (3.212)
 a n 
2
+ rd ⋅  ⋅  2  
 3 ⋅ Tsw  n1  
 
132
n 
Pcond _ S 2 = Vth ⋅ 2 ⋅  I out ⋅ δ eff +
(
(Iout − ∆iL1 ) ⋅ toff − Toff − ta )  + r ⋅  b  n2 
⋅ 
2
 (3.213)
  3 ⋅ Tsw  n1 
d
n1  2 ⋅ Tsw  
 
I s ⋅ta I 2 ⋅ta
Pcond _ Ds1 = Vth ⋅ + rd ⋅ s (3.214)
2 ⋅ Tsw 3 ⋅ Tsw
Is   (I + ∆i L1 ) n 2  c
Pcond _ Ds 2 = Vth ⋅ ⋅  t a + Toff ⋅ 1 + out ⋅   + rd ⋅
 (3.215)
2 ⋅ Tsw  3 ⋅ Tsw
  Is n1 

( (I out − ∆iL1 ) + ton ⋅ I out + ta ⋅ I ⋅ n1
) 
 toff − Toff − ta ⋅ 2 ⋅ T Tsw 2 ⋅ Tsw
s
n2
+
Pcond _ D1 = Vth ⋅  +
sw
 Toff  n  
+ ⋅  I out + ∆iL1 + I s ⋅ 1  
 2 ⋅ Tsw  n2  
  3  
   I ⋅ n1  − (I + ∆i )3   (3.216)
  s n  out L1 

 toff − Toff − ta ⋅ (I out − ∆iL1 ) + off ⋅ 
2  2

( )
3 ⋅ Tsw
T
3 ⋅ Tsw 
 +

3
 I s ⋅ − (I out + ∆iL1 ) 
n1
+ rd ⋅  
 
  n2  

 ta  n1 
2
(
3 ⋅ I out 2 + ∆iL12 ) 

+ 3 ⋅ T ⋅  I s ⋅ n  + ton ⋅ 3 ⋅ Tsw 
 sw  2 
where rd and Vth are the on-state resistance and the threshold voltage of each
semiconductor.
Since the freewheel diodes as well as the output side rectifier diodes do not present a hard
turn-off behaviour, their switching losses are neglected (cf. Fig 3.60 and Fig 3.62).
Furthermore, the transistors operate at zero voltage switching (ZVS) conditions and in
consequence, their turn-on power losses are also negligible. Hence, switching power
losses are only given in the turn-off of the transistors:
Psw _ S1 =
Vin
Tsw ⋅ V100 FIT
(
⋅ Aoff , S1 ⋅ (I s )2 + Boff , S1 ⋅ I s + Coff , S1 ) (3.217)
(Vin − ∆vCin ) ⋅  A 
2
 n2 
( ) + Boff , S 2 ⋅ (I out + ∆iL1 ) ⋅ 2 + Coff , S 2 
n
Psw _ S 2 = ⋅  I + ∆i ⋅  (3.218)
Tsw ⋅ V100 FIT  off , S 2  out L1  
  n1  n1

provided by the manufacturer for the 100FIT test voltage (V100FIT).
All the previously presented equations can be simplified assuming the leakage inductance
as well as voltage and current ripple are negligible. This simplified equations are
described in [21].
2.2.15 Full-bridge isolated-boost
The full-bridge isolated-boost converter illustrated in Fig 3.65 is a unidirectional boost

type converter. At the input side, the converter contains a capacitor (Cin), an inductor (L1)
and a H-bridge converter (S1-S2-S3-S4). In turn, a diode bridge (D1-D2-D3-D4) and a filter
133
capacitor (Cout) form the output side. Both sides of the converter are connected via a
medium frequency transformer.
Iin +
L1
-
+ Iout
iL1
+
S1 S3
D1 D3
n1 : n2
+ + +
Vin Cin
iLm Lm Cout Vout
- - -
iCin iCout
D4 D2
S4 S2
-
-
Fig 3.65. Full-bridge isolated-boost converter.
This converter operates repeatedly storing/transferring the energy in/from inductor L1.
Thus, when all the transistors of the H-bridge are on (Ton time interval of Fig 3.66a), the
energy coming from the input is stored in the inductor L1 and the output capacitor Cout
supplies the load. As zero voltage is applied to the primary of the transformer, the current
through the magnetizing inductance remains constant and it flows through the input side
transistors. Next, transistors S3-S4 are turned-off and the energy coming from the input as
well as the energy stored in L1 are transferred to the output capacitor and the load (Toff
time interval illustrated in Fig 3.66b). In this time interval, the transformer is magnetized
positively. Then, transistors S3-S4 are turned-on and again, energy is stored in L1 while the
output capacitor Cout supplies the load and the current through Lm remains constant
(second Ton time interval). Subsequently, transistors S1-S2 are turned-off and the energy
coming from the input as well as the energy stored in L1 are transferred to the output,
while the transformer is magnetized negatively (second Toff time interval illustrated in Fig
3.66c).
Given that the transformer is magnetized bidirectionally, its utilization is good. However,
the converter requires a control scheme to avoid the DC current injection that leads to the
transformer saturation.
The leakage inductance of the MFT has been neglected in this analysis. Nonetheless, this
parasitic inductance has to be considered in real cases. With the described operation, the
current circulating through the primary of the MFT is interrupted and in consequence, the
voltage over the leakage inductance will raise in a short period of time. This leads to
overvoltages in the transistors. This overvoltages can be avoided, or at least reduced,
using snubber circuits.
134
L1
+
+
S1 S3
D1 D3
n1 : n2 Iout
D4 D2
S4 S2
Iin -
-
a)
L1
+
+
S1 S3
n1 : n2
D1 D3 Iout
D4 D2
S4 S2
Iin -
-
b)
L1
+
+
S1 S3
n1 : n2
D1 D3 Iout
D4 D2
S4 S2
Iin -
-
c)
Fig 3.66. Currents circulating through the full-bridge isolated-boost converter a) when
all the transistors are on, b) when S1-S2 are on and S3-S4 are off, and c) when S1-S2 are
off and S3-S4 are on.
The typical current and voltage waveforms of the full-bridge isolated-boost converter in
continuous current mode (CCM) are shown in Fig 3.67. From Fig 3.67a, it can be
deduced that the theoretical maximum time interval in which all the transistors are on is
Tsw/2. Thus, the maximum duty cycle of the converter is given by:
Tsw 1
Ton,max = → δ max = (3.219)
2 2
During a switching period (Tsw), the average current through the input inductor is constant
and in consequence, the average voltage drop over the input side inductor is zero.
Therefore, from Eq. (3.220) and the voltages drawn in Fig 3.67b, the DC voltage transfer
function is derived, Eq. (3.221).
1  Ton Tsw 
vL1 = ⋅  ∫ vL1 dt + ∫ vL1 dt  = 0 (3.220)
Tsw  
 0 Ton 
Vin n
Vout = ⋅ 2 (3.221)
1 − 2 ⋅ δ n1
135
cycle of the converter and n1 and n2 are respectively the number of turns of the primary
and secondary windings of the medium frequency transformer (cf. Fig 3.65).
Similarly, the DC current transfer function is obtained from the waveforms shown Fig
3.67c:
n1
I=
out (1 − 2 ⋅ δ )⋅ I in ⋅ (3.222)
n2
S1-S2-S3-S4
Conducting
iLm S1-S2 & D1-D2 S3-S4 & D3-D4

Conducting
Conducting
ΔiLm
Tsw
- ΔiLm t
Ton Toff Ton Toff
vLm
n1
V
n2 out
y=-sinx, x∊[0,2
x [0,2π]
ππ]
t
n1
- V
n2 out
a)
iL1 S1-S2 & D1-D2

Conducting
S3-S4 & D3-D4
Conducting vCout
ΔiL1 ΔvCout
Iin Vout
Ton Toff Ton Toff
S1-S2-S3-S4 S1-S2-S3-S4 Ton Toff Ton Toff

vL1
Tsw Tsw t Tsw Tsw t
2 iCout 2
Vin n1
I -I
n2 in out
π
π
π]
t t
n1
Vin - V
n2 out - Iout
b) c)
Fig 3.67. Typical voltage and current waveforms in full-bridge isolated-boost

converter's a) magnetizing inductance Lm, b) inductor L1 and c) capacitor Cout.
136
On the other hand, the inductances of the magnetic elements in the converter can be
calculated from the waveforms depicted in Fig 3.67a and Fig 3.67b:
∆t Vout n
L m = v Lm ⋅ = ⋅ 1 ⋅ (1 − 2 ⋅ δ ) ⋅ Tsw (3.223)
∆i 4 ⋅ ∆i Lm n 2
∆t Vin
L1 = vL1 ⋅ = ⋅ δ ⋅ Tsw (3.224)
∆i 2 ⋅ ∆iL1
Similarly, the value of Cout can be calculated from the steady state analysis of the
waveforms of Fig 3.67c:
∆t I out
C out = iCout ⋅ = ⋅ δ ⋅ Tsw (3.225)
∆v 2 ⋅ ∆vCout
where ∆vCout is the output voltage ripple.

Assuming the input current Iin is constant, the current circulating through the input
capacitor is the same as the current ripple in the input side inductor. Thus, the input DC
bus capacitance (Cin) can be calculated from Fig 3.68:
QCin ∆i L1
C in = = ⋅ Tsw (3.226)
∆v 16 ⋅ ∆v Cin
iCin
QCin
ΔiL1
-ΔiL1 t
Ton Toff T
sw
2
Fig 3.68. Current through the input capacitor of the full-bridge isolated-boost
converter.
The equations of the maximum energy stored by the passive elements, their maximum
voltage stress and the rms currents circulating through them are summarized in Table
3.33. These expressions can be derived from the waveforms in Fig 3.67 and Fig 3.68.
The optimal design point is determined by the semiconductor utilization factor (Uf).
Calculated from Table 3.34, the semiconductor utilization factor of the full-bridge
isolated-boost converter is given by:
PRated 1− 2 ⋅δ
Uf = =
∑all _ switches vmax ⋅ I rms  1−δ
4⋅ +
1− 2 ⋅δ 
 (3.227)
 2 2 
 
As it can be noticed, this Uf factor is the same as that discussed for the push-pull isolated-
boost converter in Eq. (3.169) and illustrated in Fig 3.49. Therefore, as discussed for that
converter, the lower the duty cycle the better the semiconductor utilization. In
137
consequence, the n2/n1 turn ratio must be chosen to make sure the converter operates with
low duty cycle values.
TABLE 3.33
Maximum stored Maximum

Element rms current
1 ∆i L1
2 3
1 1+ 4 ⋅δ (Vout + ∆vCout ) ⋅ n1
Lm ⋅ Lm ⋅ ∆i Lm 2 ∆iLm ⋅ n2
2 3
1
⋅ L1 ⋅ (I in + ∆iL1 )2
∆iL12 (Vin + ∆vCin )
L1 I in 2 +
2 3
1 2
⋅ Cout ⋅ (Vout + ∆vCout )2   (Vout + ∆vCout )
2 ⋅ δ ⋅ I out 2 + (1 − 2 ⋅ δ ) ⋅  I in ⋅ 1 − I out 
n
Cout 2
 n2 
Generally speaking, the power losses of the converter are given by semiconductor power
losses. Semiconductor power losses depend on conduction power losses, Eq. (3.1), and
switching power losses, Eq. (3.2). In turn, conduction power losses depend on average
and rms currents through the switches, while switching power losses depend on the
switched current and voltages. Assuming all the transistors of the input side H-bridge
converter conduct the same current, it can be said that their average power losses are
equal. This is applicable to output side rectifier diodes D1-D2-D3-D4. Therefore, power
losses expressions are calculated just for one semiconductor in each group. The
expressions required for calculating these power losses are summarized in Table 3.34.
All in all, average conduction power losses of transistor S1 (Pcond_S1) and diode D1
(Pcond_D1) are:
I in 
+ rd ⋅  I in 2 ⋅
(1 − δ ) + δ ⋅  ∆iLm 2 + ∆iL12  +  1 − δ  ⋅ ∆iL12 
 2
  (3.228)
2  2  6   2  3 
 n   n  (∆i + ∆iL1 )2   1
2 2
 ⋅  − δ 
I out
Pcond _ D1 = Vth ⋅ + rd ⋅  I in ⋅ 1  +  1  ⋅ Lm (3.229)
2  n2   n2  3  2 
 
respectively.
138
TABLE 3.34
Current and
Diodes
voltage Transistors S1-S2
D1-D2-D3-D4
expressions
Average current I in I out

(Iave) 2 2
 2 (1 − δ )  ∆i 2 ∆i 2  
 I in ⋅ + δ ⋅  Lm + L1  +
  (∆iLm + ∆iL1 )2   1
2 2
 2  2 6    n
   ⋅  − δ 
n
rms current (Irms)    I in ⋅ 1  + 1  ⋅
  n  3  2
 1  ∆iL1
2
 
n2   2   
+  2 − δ  ⋅ 3 
   
(I in + ∆iL1 )
n1
Maximum current
(imax)
(I in + ∆i L1 + ∆i Lm )⋅
n2
Turn-on switched (I in − ∆i L1 − ∆i Lm )
current (ion) −
2
Turn-off switched (I in + ∆i L1 + ∆i Lm ) (I in − ∆i L1 − ∆i Lm )⋅
n1
current (ioff) 2 n2
Maximum voltage
(vmax)
(Vout + ∆vCout ) ⋅ n1 (Vout + ∆vCout )
n2
Turn-on switched
voltage (von)
(Vout + ∆vCout ) ⋅ n1 −
n2
Turn-off switched
(Vout − ∆vCout ) ⋅ n1 (Vout + ∆v Cout )
voltage (voff) n2 2
Average switching power losses of the transistor S1 (Psw_S1) and diode D1 (Psw_D1) are
given by:
  (I + ∆iL1 + ∆iLm )  
2
(Vout − ∆vCout ) ⋅ n1 A
, 1 ⋅  in  + 
n2  off S
 2  
Psw _ S1 = ⋅ +
Tsw ⋅ V100 FIT
+ B ( I in + ∆iL1 + ∆iLm )
+ Coff , S1 
 off , S1 ⋅
 2 
(3.230)
  (I in − ∆iL1 − ∆iLm )  
2
(Vout + ∆vCout ) ⋅ n1 A
on , S 1 ⋅   + 
n2   2  
+ ⋅
Tsw ⋅ V100 FIT
+ B ⋅
(I in − ∆iL1 − ∆iLm ) + C 
 on, S1 on , S1 
 2 
  n1 
2 
A ⋅  (I in − ∆iL1 − ∆iLm ) ⋅  +
  
(Vout + ∆vCout )  off , D1
 n3  
Psw _ D1 = ⋅  (3.231)
2 ⋅ Tsw ⋅ V100 FIT  
 + Boff , D1 ⋅ (I in − ∆iL1 − ∆iLm ) ⋅ n + Coff , D1 
n1
 3 
provided by the manufacturer for the 100FIT test voltage (V100FIT) switch whereas Aon,S1,
Bon,S1 and Con,S1 are turn-on energy loss characteristic coefficients.
139
2.2.16 Single-active-bridge
The single-active-bridge converter depicted in Fig 3.69 is a unidirectional converter

derived from buck. The converter is composed of a medium frequency transformer, a H-
bridge converter (S1-S2-S3-S4) at the input side, a diode bridge (D1-D2-D3-D4) at the output
side and two DC bus filter capacitors, one at the input side (Cin) and another one at the
output side (Cout).
Iin
+ DS1 DS3
Iout
S1 S3 +
Lσ - n1 : n2 D1 D3
+
+ iLσ +
Vin Cin Cout Vout
- -
iCin iCout
D4 D2
S4 S2 -
- DS4 DS2
Fig 3.69. Single-active-bridge converter.
The converter operates alternating the switching orders of the transistors S1-S2 and S3-S4.
With light loads, the converter operates in discontinuous current more (DCM) while with
nominal and heavy loads, the converter operates in continuous current mode (CCM) [22].
Under nominal load operation conditions, if S1-S2 are on and S3-S4 are off (Ton time
interval), the energy coming from the input and the energy stored in the input capacitor
(Cin) are transferred to the leakage inductance of the MFT (Lσ) and the load (cf. Fig
3.70a). Then, S1-S2 are turned-off while S3-S4 are turned-on. During a Toff time interval (cf.
Fig 3.70b), the current polarity is opposite to the natural conduction sense of the
transistors and hence, current flows through freewheel diodes DS3 and DS4. The load is
supplied by the energy stored in the leakage inductance and in the output capacitor (Cout)
while the energy coming from the input is stored in Cin. Once the current polarity is
inversed, transistors S3-S4 begin to conduct the current coming from the input and a
second Ton time interval begins (cf. Fig 3.70c). Again, the energy coming from input and
the energy stored in Cin are transferred to Lσ and the load. Next, S1-S2 are turned-off and
S3-S4 are turned-on (cf. Fig 3.70d). Until its polarity is inversed, the current in the leakage
inductance circulates through freewheel diodes DS1 and DS2 (second Toff time interval).
For light loads, the transferred power is reduced diminishing the duty cycle. In
consequence, there are time intervals at which all the transistors are off, the load is
supplied by the output capacitor and the energy coming from the input is stored in the
input capacitor (cf. Fig 3.70f).
140
+ Iout
DS1 DS3 + DS1 DS3
+
S1 S3
S1 S3 +
Lσ n1 : n2 D1 D3 Iout Iout
Lσ n1 : n2 D1 D3
Vin Cin Cout Vout Vin Cout Vout

Cin
D4 D2
S4 S2 - D4 D2
Iin DS4 DS2 Iin S4 S2 -
- DS4 DS2
-
a) b)
+ DS1 DS3 + DS1 DS3
S1 S3 + S1 S3 +
Iout Iout
Lσ n1 : n2 D1 D3 Lσ n1 : n2 D1 D3
D4 D2 D4 D2
Iin S4 S2 - S4 S2 -
DS4 DS2 Iin DS4 DS2
- -
c) d)
+ DS1 DS3
S1 S3 +
Lσ n1 : n2 D1 D3 Iout
Vin Cin Cout Vout
D4 D2
S4 S2 -
Iin DS4 DS2
-
f)
Fig 3.70. Currents circulating through the single-active-bridge converter a) when S1-
S2 are on and S3-S4 are off, b) when S3-S4 are on and S1-S2 are off (the current
circulates through the freewheel diodes DS3-DS4), c) when S1-S3 are on and S2-S4 are
off, d) when S1-S2 are on and S3-S4 are off (the current circulates through the
freewheel diodes DS1-DS2) and f) when S1-S2 and S3-S4 are off.
The current and voltage waveforms in the leakage inductance of the MFT are illustrated
in Fig 3.71. As it can be noticed, the current through the medium frequency transformer is
alternating. Thus, the magnetization of the transformer is bidirectional and therefore, the
utilization of the medium frequency transformer is good. In order to prevent the
saturation of the transformer, a control strategy must guarantee that the average voltage
applied to the MFT is zero.
As it has been said, the power is only transferred during the Ton time interval. Hence,
from Fig 3.71a it can be deduced that the maximum current through the leakage
inductance imax is given by:
imax 2 ⋅ Ton i 2 ⋅ Toff

Pin = Vin ⋅ I in = Vin ⋅ ⋅ − Vin ⋅ max ⋅ →
2 Tsw 2 Tsw
(3.232)
Tsw
→ i max = I in ⋅
Ton − Toff( )
where Vin and Iin are respectively the average input voltage and current (cf. Fig 3.69), Ton
and Toff are respectively the conduction times of the transistors and the freewheel diodes
and Tsw is the switching period.
141
For any conduction mode (continuous or discontinuous, Fig 3.71), the relation between
the current through the leakage inductance and the voltage drop over this parasitic
element can be expressed as:
∆i  n  L ⋅i
v Lσ Lσ ⋅
= → Vin − Vout ⋅ 1  = σ max (3.233)
∆t  n2  Ton
∆i  n  L ⋅i
v Lσ Lσ ⋅
= → Vin + Vout ⋅ 1  = σ max (3.234)
∆t  n2  Toff
where Vout is the average output voltage and n2/n1 is the turn ratio of the MFT (cf. Fig
3.69).
Developing these equations, the relation between the duty cycle of the converter and the
conduction time of the freewheel diodes (Toff) is obtained, Eq. (3.235). This expression is
valid for continuous and discontinuous current mode conditions.
1− M
Toff Ton ⋅
= (3.235)
1+ M
Vout n1
M
= ⋅ (3.236)
Vin n 2
From the same equations, and assuming the converter operates with nominal load
conditions (hence, 2Ton+2Toff=Tsw), the DC voltage transfer function can be obtained:
n2
V
=out Vin ⋅ (4 ⋅ δ − 1) ⋅ (3.237)
n1
where δ is the duty cycle of the converter (Ton/Tsw≤0.5).
iLσ iLσ
S1-S2 & D1-D2 DS3-DS4 & D1-D2 S1-S2 & D1-D2
Conducting Conducting Conducting DS3-DS4 & D1-D2
imax DS1-DS2 & D3-D4 imax Conducting DS1-DS2 & D3-D4
Conducting
S3-S4 & D3-D4 Conducting
Conducting
S3-S4 & D3-D4
Conducting
Tsw Tsw
t Tsw Tsw
t
2 -imax 2
-imax
Ton Toff Ton Toff Ton Toff Ton Toff
vLσ vLσ
n n
Vin+ n1 Vout Vin+ n1 Vout
2 2
Vin- n
n2 Vout
1
Vin- n
n2 Vout
1
n
-(Vin- n1 Vout) t n
-(Vin- n1 Vout) t
2 2
n1 n1
-(Vin+ n Vout) -(Vin+ n Vout)
2 2
a) b)
Fig 3.71. Typical voltage and current waveforms in the leakage inductance (Lσ) of the
single-active-bridge converter in a) continuous current mode operation and b)
discontinuous current mode operation.
142
Considering an ideal operation without losses (Pin=Pout), the DC current transfer function
for nominal conditions is given by:

 I in n
n 2  → I out = ⋅ 1 (3.238)
Vout = Vin ⋅ (4 ⋅ δ − 1) ⋅  (4 ⋅ δ − 1) n 2
n1 
On the other hand, the value of the leakage inductance Lσ can be derived from Fig 3.71:
 n 
Vin − Vout ⋅ 1 
∆t n2  (3.239)
Lσ = v Lσ ⋅ = ⋅ δ ⋅ Tsw
∆i imax
Under the assumption of a CCM operation and constant input and output currents (Iin and
Iout), the currents through input and output capacitors can be drawn as in Fig 3.72.
iCin
iCout
Iin+imax n1 QCout
n2 imax - Iout
Iin QCin
- Iout t
Tsw t Ton Toff
Tsw
Iin-imax 2
Ton Toff 2
a) b)
capacitor of the single-active-bridge converter under the assumption of a continuous
current mode operation.
As a consequence, calculating the charges circulating through the capacitors (grey

colored areas in Fig 3.72) the input DC bus capacitance (Cin) and the output capacitance
(Cout) can be derived:
 I in 
(Iin − imax ) ⋅ Ton ⋅ 1 − 
QCin  imax  (3.240)
Cin = =
∆v 4 ⋅ ∆vCin
 n 
 imax ⋅ 1 − I out 
QCout  n2  ⋅T (3.241)
Cout = = sw
where ∆vCin and ∆vCout are respectively the half of the desired peak to peak voltage ripple
in the input and in the output capacitors.
Additionally, from Fig 3.71a and Fig 3.72, the expressions of the maximum energy stored
by the passive elements, their maximum voltage stress and the rms currents circulating
through them are derived and summarized in Table 3.35.
143
TABLE 3.35

Element rms current
energy stress
1 2⋅χ
Cin ⋅ C in ⋅ (Vin + ∆v Cin )2
3 ⋅ i max ⋅ Tsw
(Vin + ∆vCin )
2
1 i max  n 
Lσ ⋅ Lσ ⋅ i max 2 ≈ Vin + Vout ⋅ 1 
2 3  n2 
1  2   
2
1
Cout ⋅ Cout ⋅ (Vout + ∆vCout )2
n
⋅  I out +  imax ⋅ 1 − I out   (Vout + ∆v Cout )
2 6   n2  

[ ( ) (
χ = Ton ⋅ I in 3 − (I in − i max )3 + Toff ⋅ (I in + i max )3 − I in 3 )]
From the expression in Table 3.36 and Table 3.37, the semiconductor utilization factor
(Uf) is provided by:
PRated 3 ⋅ M ⋅δ
Uf = =
∑all _ switches v max ⋅ I rms 
2 ⋅ (1 + M ) ⋅  δ +
(1 − M ) ⋅ δ +M⋅
2 ⋅δ 
 (3.242)
 1+ M 1+ M 
 
In Fig 3.73, the semiconductor utilization factor is illustrated for a given M value (M=0.6)
and different duty cycles. As for previously discussed buck derived converters, the higher
the duty cycle the better the semiconductor utilization. Therefore, in order to minimize
the installed semiconductor power in the converter, the converter must be designed to
operate with duty cycles values close to 0.5.
0.1
0.07
0.05
0.02
0
0 0.125 0.25 0.375 0.5
Duty cycle (δ)

Fig 3.73. Semiconductor utilization factor of the single-active-bridge converter.
Assuming ideal passive elements with no losses, the power losses of the converter are
given by the semiconductor power losses. These, can be estimated through Eq. (3.1) and
Eq. (3.2) discussed at the beginning of section 3.2.1. The current and voltage expressions
144
required by the mentioned equations have been obtained from Fig 3.71 and are
summarized in Table 3.36 and Table 3.37.
TABLE 3.36
EXPRESSIONS OF THE VOLTAGES/CURRENTS IN THE SEMICONDUCTORS OF THE INPUT SIDE H-BRIDGE
Current and voltage Transistors Freewheel diodes

expressions S1-S2-S3-S4 DS1-DS2-DS3-DS4
i max i max  1 − M 
Average current (Iave) ⋅δ ⋅  ⋅δ
2 2 1+ M 
δ  1− M  δ
rms current (Irms) i max ⋅ i max ⋅  ⋅
3 1+ M  3
Maximum current (imax) i max i max
Turn-off switched current (ioff) i max 0
Maximum voltage (vmax) (Vin + ∆vCin ) (Vin + ∆vCin )

Turn-off switched voltage (voff) (Vin − ∆vCin ) 0
TABLE 3.37
EXPRESSIONS OF THE VOLTAGES/CURRENTS IN THE DIODE BRIDGE
Diodes
Current and voltage expressions
D1-D2-D3-D4
i max ⋅ δ n1
Average current (Iave) ⋅
(1 + M ) n2
n1 δ 2
rms current (Irms) i max ⋅ ⋅ ⋅
n2 (1 + M ) 3
n1
Maximum current (imax) i max ⋅
n2
Turn-off switched current (ioff) 0
Maximum voltage (vmax) (Vout + ∆vCout )

Turn-off switched voltage (voff) ≈ Vout
Since the current and voltage expressions of all the transistors are the same, the power
losses expressions are calculated for one transistor only. This is also applied to the
freewheel diodes and the output rectifier diodes.
145
Thus, from Eq. (3.1) and Table 3.36, the expressions of the average conduction power
losses of transistor S1 (Pcond_S1) and freewheel diode DS1 (Pcond_Ds1) are given by:
imax δ
Pcond _ S1 = Vth ⋅ ⋅ δ + rd ⋅ imax 2 ⋅ (3.243)
2 3
imax  1 − M  2 δ 1− M 
Pcond _ Ds1 = Vth ⋅ ⋅  ⋅ δ + rd ⋅ imax ⋅ ⋅   (3.244)
2 1+ M  3 1+ M 
semiconductor.
Similarly, average conduction power losses of the output diode D1 (Pcond_D1) are expressed
as:
2
imax ⋅ δ n1  n  δ 2
Pcond _ D1 = Vth ⋅ ⋅ +r ⋅  imax ⋅ 1  ⋅ ⋅ (3.245)
(1 + M ) n2 d  n2  (1 + M ) 3
In this converter, the freewheel diodes and the rectifier diodes are turned-off with a
relatively low current slope and hence, their switching losses can be neglected [22-23].
Moreover, the turn-on of the transistors is given at zero voltage switching (ZVS)
conditions in CCM (cf. Fig 3.71a) and in zero current switching (ZCS) conditions in
DCM (cf. Fig 3.71b). In consequence, their turn-on power losses are also negligible.
Therefore, switching power losses are only given in the turn-off of the transistors:
Psw _ S1 =
(Vin − ∆vCin ) ⋅ (A ( )2 + Boff , S1 ⋅ imax + Coff , S1 )
off , S1 ⋅ imax (3.246)
Tsw ⋅ V100 FIT
provided by the manufacturer for the 100FIT test voltage (V100FIT).
2.2.17 Dual-active-bridge
The dual-active-bridge converter is a bidirectional step-up/down converter composed of

two H-bridge converters (one at the input side and the other at the output side), two DC
bus capacitors (Cin and Cout) and a medium frequency transformer.
Iin io Iout
+ DS1 DS3 DS5 DS7 +
S1 S3 S5 S7
Lσ - n1 : n2
+
+ iLσ +
Vin Cin
- Cout Vout
iCin - iCout
S4 S2 S8 S6
- DS4 DS2 DS8 DS6
-
Fig 3.74. Dual-active-bridge converter.
146
The dual-active-bridge converter operates phase-shifting the square wave voltages

applied at each side of the medium frequency transformer (cf. Fig 3.75). The voltage
resulting from the subtraction of these voltages drops over the leakage inductance (Lσ).
The voltage applied to the leakage inductance determines the current circulating through
the transformer and thus, the power transferred by the converter. This voltage drop varies
changing the phase-shift (φ) between the square wave voltages and in consequence, the
power transference can be managed by means of controlling this phase-shift.
Tsw Tsw
2 2
Toff Ton Toff Ton
S1-S2
S3-S4
S5-S6
S7-S8
φ
Fig 3.75. Switching orders in the dual-active-bridge converter.
As it can be noticed in Fig 3.75, each transistor is on during half of the switching period
(Tsw/2). The switching orders of transistors S1-S2 and transistors S3-S4 are complementary.
In the same way, the switching orders of transistors S5-S6 and transistors S7-S8 are
complementary. The operation of the converter during a switching period is illustrated in
Fig 3.76 assuming constant input and output currents (Iin and Iout in Fig 3.74). When S1-S2
are turned-on, S7-S8 are still on (cf. Fig 3.75) and the energy coming from the input is
used to invert the polarity of the current through the leakage inductance from negative to
positive (cf. Fig 3.77). During the inversion process of the current polarity, the current
circulates through freewheel diodes DS1-DS2 and DS7-DS8 (cf. Fig 3.76a). Once the current
through the leakage inductance is positive it flows through transistors S1-S2 and S7-S8 (cf.
Fig 3.76b). Then, transistors S7-S8 are turned-off while S5-S6 are turned-on and, during
their Ton time interval (cf. Fig 3.76c), the energy coming from the input is transferred to
the output. When transistors S1-S2 are turned-off and S3-S4 are turned-on, the energy
coming from the input is used to invert the polarity of the current through the leakage
inductance. While the polarity of this current is positive, the current flows through
freewheel diodes DS3-DS4 and DS5-DS6 (cf. Fig 3.76d). When the current is negative, it
circulates through transistors S3-S4 and S5-S6 (cf. Fig 3.76e). Then, transistors S7-S8 are
turned-on and transistors S5-S6 are turned-off. During the second Ton time interval (cf. Fig
3.76f), the energy coming from the input is transferred to the output.
147
+ DS1 DS3 DS5 + + DS1 DS3 DS5 DS7 +

DS7 Iout Iout
Iin S1 S3 S5 S7 Iin S1 S3 S5 S7
Lσ n1 : n2 Lσ n1 : n2
S4 S2 S8 S6 S4 S2 S8 S6
- DS4 DS2 DS8 DS6 - DS4 DS2 DS8 DS6
- -
a) b)
+ DS1 DS3 DS5 DS7 + + DS1 DS3 DS5 DS7 +
Iin S1 S3 S5 S7
Iout Iin S1 S3 S5 S7
Iout
Lσ n1 : n2 Lσ n1 : n2
S4 S2 S8 S6 S4 S2 S8 S6
- -
c) d)
+ DS1 DS3 DS5 DS7 + + DS1 DS3 DS5 +
Iout DS7 Iout
Iin S1 S3 S5 S7 Iin S1 S3 S5 S7
Lσ n1 : n2 Lσ n1 : n2
S4 S2 S8 S6 S4 S2 S8 S6
- -
e) f)
Fig 3.76. Currents circulating through the dual-active-bridge converter a) when S1-S2
are on (current circulates through the freewheel diodes DS1-DS2) and S7-S8 are on
(current circulates through the freewheel diodes DS7-DS8), b) when S1-S2 are on and
S7-S8 are on, c) when S1-S2 are on and S5-S6 are on (current circulates through the
freewheel diodes DS5-DS6), d) when S3-S4 are on (current circulates through the
freewheel diodes DS3-DS4) and S5-S6 are on (current circulates through the freewheel
diodes DS5-DS6), e) when S3-S4 are on and S5-S6 are on, and f) when S3-S4 are on and
S7-S8 are on (current circulates through the freewheel diodes DS7-DS8).
The leakage inductance current and voltage waveforms are depicted in Fig 3.77. As it can
be noticed, the current through the transformer is alternating. Thus, the magnetization of
the transformer is bidirectional and in consequence, the utilization of the transformer is
good. However, a control strategy must guarantee that the average voltage applied to the
transformer is zero in order to prevent its saturation.
iLσ S1-S2 & S7-S8

S1-S2 & DS5-DS6
Conducting
Conducting
DS3-DS4 & DS5-DS6
imax Conducting
S3-S4 & DS7-DS8
Conducting
i1 S3-S4 & S5-S6
ta Conducting
Tsw
-i1
t
DS1-DS2 & DS7-DS8
-imax Conducting
Toff Ton Toff Ton Toff

vLσ
n
Vin+ n1 Vout
2
Vin- n
n2 Vout
1
n
-(Vin- n1 Vout) t
2
n
-(Vin+ n1 Vout) φ
2
Fig 3.77. Typical voltage and current waveforms in the leakage inductance (Lσ) of the
dual-active-bridge converter.
148
The time interval at which there is no power transference from the input to the output is
given by the phase-shift (φ) of the square wave voltages:
ϕ ⋅ Tsw
Toff = (3.247)
2 ⋅π
where Tsw is the switching period.
While the time interval at which the power is transferred from the input to the output is:
Tsw T  ϕ
Ton = − Toff = sw ⋅ 1 −  (3.248)
2 2  π
From Fig 3.77, the relation between the current through the leakage inductance and its
voltage is provided by:
v Lσ = Lσ ⋅
∆i  n  (i + i )
→ Vin + Vout ⋅ 1  = Lσ ⋅ max 1 (3.249)
∆t  n2  Toff
v Lσ = Lσ ⋅
∆i  n  (i − i )
→ Vin − Vout ⋅ 1  = Lσ ⋅ max 1 (3.250)
∆t  n2  Ton
where Vin and Vout are the average input and output voltages, n2/n1 is the turn ratio of the
MFT (cf. Fig 3.74), imax is the maximum current through the leakage inductance and i1 is
the value of the current at the end of the Toff time interval (cf. Fig 3.77).
Developing Eq. (3.249) and Eq. (3.250), the values of i1 and imax can be calculated:
 
Vin ⋅ (2 ⋅ ϕ − π ) + Vout ⋅ 1 ⋅ π  ⋅ Tsw
n
(3.251)
i1 =  
n2
4 ⋅ π ⋅ Lσ
 
Vin ⋅ π + Vout ⋅ 1 ⋅ (2 ⋅ ϕ − π ) ⋅ Tsw
n
(3.252)
= 
n2
i max
4 ⋅ π ⋅ Lσ
The value of the input current (Iin) is derived from the waveforms in Fig 3.77 taking into
account the sense of the current circulating through the input side H-bridge (see Fig 3.76):
I in =
2  ϕ ⋅ Tsw
⋅ 
 i (i + i ) T  ϕ  i 
− t a  ⋅ 1 + max 1 ⋅ sw ⋅ 1 −  − max ⋅ t a  ⇒
Tsw  2 ⋅ π  2 2 2  π 2 
n1 (3.253)
Vout ⋅ ⋅ Tsw
n2  ϕ
⇒ I in = ⋅ ϕ ⋅ 1 − 
2 ⋅ π ⋅ Lσ  π
where ta is:
 
Vin ⋅ π + Vout ⋅ ⋅ (2 ⋅ ϕ − π ) ⋅ Tsw
n1
imax ϕ ⋅ Tsw  n2 
ta = ⋅ = (3.254)
(i1 + imax ) 2 ⋅ π  n1 
4 ⋅ π ⋅ Vin + Vout ⋅ 
 n2 
149
As the input power depends on the average input current as well as the DC bus voltage,
the same statement as in [23] can be obtained from Eq. (3.253) assuming ideal operation
with no power losses:
Vin 2 ⋅ Tsw  ϕ
Pout = Pin = Vin ⋅ I in = ⋅ d ⋅ ϕ ⋅ 1 −  (3.255)
2 ⋅ π ⋅ Lσ  π
Vout ⋅ n1
d= (3.256)
Vin ⋅ n2
As it can be noticed, the power transfer is dependent on the phase-shift φ. In turn, if Eq.
(3.255) is plotted in function of the phase-shift (see Fig 3.78), it can be observed that the
maximum power transference is given at φ=π/2.
Output power (Pout)
0
0 π/4 π/2 3π/2 π
Phase-shift (φ)
Fig 3.78. Output power of the dual-active-bridge converter in function of the phase-
shift.
On the other hand, the value of the leakage inductance Lσ can be derived from Eq.
(3.249):
 n  ϕ ⋅ Tsw
Lσ = Vin + Vout ⋅ 1  ⋅ (3.257)
 n2  2 ⋅ π ⋅ (imax + i1 )
Under the assumption of constant input and output currents (Iin and Iout), Fig 3.79 shows
the waveforms of the currents through input and output capacitors. Thus, the input and
output side capacitors can be derived from the waveforms in Fig 3.79:
QCin ϕ ⋅ Tsw ⋅ (I in + i max )2

C in = = (3.258)
∆v 8 ⋅ π ⋅ (i max + i1 ) ⋅ ∆vCin
QCout  n   n  ϕ ⋅ Tsw ⋅ n 2
C out = =  i1 ⋅ 1 + I out  ⋅  i1 + I out ⋅ 2  ⋅ (3.259)
∆v  n 2   n1  8 ⋅ π ⋅ (i max + i1 ) ⋅ ∆v Cout ⋅ n1
and output capacitors.
150
iCin iCout
Iin+imax n1
n2 imax - Iout
n1 QCin
n2 i1 - Iout
QCin
t
Iin-i1 t
tb
Iin-imax n
Toff Ton
Tsw - n1 i1 - Iout Tsw
2 2 Toff Ton
2
a) b)
capacitor of the dual-active-bridge converter.
Furthermore, the expressions for the maximum energy stored by the passive elements,
their maximum voltage stress and the rms currents circulating through them can be
derived from the waveforms in Fig 3.77 and Fig 3.79. Table 3.38 summarizes the latter
expressions.
TABLE 3.38

stress
1 χ
2 3⋅π
1 κ  n 
Lσ ⋅ Lσ ⋅ i max 2 (imax + i1 ) ⋅ ≈ Vin + Vout ⋅ 1 
2 3⋅π  n2 
1 n1 ⋅ ρ
Cout ⋅ C out ⋅ (Vout + ∆vCout )2 I out 2 + (Vout + ∆vCout )
2 3 ⋅ n2
  (i max + I in )3  (i − i − 2 ⋅ I in )   (π − ϕ ) ⋅ (I − i )3 − (I − i )3 
χ = ϕ ⋅ 
  (i max + i1 )
+ (I in − i1 )2 ⋅  1 max  + (
(i max + i1 )   (i1 − i max ) in max
 in 1

)
 

κ = (1 − i max ⋅ i1 ) ⋅ (π − ϕ ) +
(
ϕ ⋅ i max 3 + i13 

)
 (imax + i1 )3 
 n1  ⋅i  3 ⋅ I out ⋅ i1 
⋅  (i max + i1 )2 − max 1 ⋅ (π + 2 ⋅ ϕ ) + (2 ⋅ ϕ − π ) − 3 ⋅ I out ⋅ i max 
i
ρ=
 2
n  π  π 
Neglecting the voltage ripple, the semiconductor utilization factor can be calculated from
the rms currents and maximum voltage expressions in Table 3.39 and Table 3.40:
PRated
Uf = (3.260)
4 ⋅ Vin ⋅ (I S1 RMS + I Ds1 RMS ) + 4 ⋅ Vout ⋅ (I S 5 RMS + I Ds 5 RMS )
In Fig 3.80, the semiconductor utilization factor has been illustrated in function of the
phase-shift φ. As it can be noticed, the utilization of the semiconductors is maximized
151
with phase-shifts close to 0 and π. However, as shown by Fig 3.78, the power
transference at these points is low, which suggests that the converter is underused. Hence,
in spite of the low semiconductor utilization, it is preferable to design the converter for
operating with phase-shifts close to φ=π/2, where the maximum power transference is
given.

≈
1.6
1.1
0.6
≈
0
≈
0 π/4 π/2 π
Phase shift (φ)
Fig 3.80. S Semiconductor utilization factor of the dual-active-bridge converter.
The power losses of the converters are calculated estimating the average semiconductor
conduction losses of Eq. (3.1) and the average semiconductor switching losses of Eq.
(3.2). As the input side transistors conduct the same current, their power losses are the
same. This can be applied to the input side freewheel diodes and the output side
transistors as well as freewheel diodes. Therefore, power losses are calculated for one
semiconductor in each group (S1, S5, DS1 and DS5). In Table 3.39 and Table 3.40, main
current and voltage expressions required to estimate the power losses are summarized.
These expressions are obtained from Fig 3.77.
Therefore, average conduction power losses of transistors S1 (Pcond_S1) and S5 (Pcond_S5),
and conduction losses of freewheel diodes DS1 (Pcond_Ds1) and DS5 (Pcond_Ds5) are given by:
i  ϕ t  (i + i )  ϕ 
Pcond _ S1 = Vth ⋅  1 ⋅  − a  + 1 max ⋅ 1 −  +
 2  2 ⋅ π Tsw  4  π 
(3.261)
r
+ d
3
  ϕ
⋅ i1 2 ⋅ 
2 ⋅ π
t
− a

 (
 + i1 2 + i max ⋅ i1 + i max 2 ) 1 ϕ
⋅ −
 2 2 ⋅π



  T sw 
2
i n  ϕ t  r  n   ϕ t 
Pcond _ S 5 = Vth ⋅ 1 ⋅ 1 ⋅  − a  + d ⋅  i1 ⋅ 1  ⋅  − a  (3.262)
2 n2  2 ⋅ π Tsw  3  n2   2 ⋅ π Tsw 
i max t a i 2 ⋅ta
Pcond _ Ds1 = Vth ⋅ ⋅ + rd ⋅ max (3.263)
2 Tsw 3 ⋅ Tsw
152
n1 i t (i + i )  ϕ  c
Pcond _ Ds 5 = Vth ⋅ ⋅  max ⋅ a + 1 max ⋅ 1 −  + rd ⋅
n2  2 T sw 4  π   3 ⋅ Tsw
2
(3.264)
r
+ d
3
n
⋅  1
  2
(
 ⋅  i1 + i max ⋅ i1 + i max 2 ⋅  − )
1 ϕ  2 ta 
 + i max ⋅
 2 2 ⋅π 

 n2   Tsw 
semiconductor.
TABLE 3.39
EXPRESSIONS OF THE VOLTAGES/CURRENTS IN THE SEMICONDUCTORS OF THE INPUT SIDE H-BRIDGE
Current and Freewheel

Transistors
voltage diodes
S1-S2-S3-S4
expressions DS1-DS2-DS3-DS4
Average current  i1  ϕ t  (i1 + i max )  ϕ  i max t a

 ⋅  − a +
 ⋅ 1 −   ⋅
(Iave)
 2 ⋅ π Tsw  π  2 Tsw
 2  4
rms current
(Irms)
1  2  ϕ
⋅ i1 ⋅ 
t 
( 1
− a  + i1 2 + i max ⋅ i1 + i max 2 ⋅  −
ϕ
) 
 i max ⋅
ta
3 ⋅ Tsw
3   2 ⋅ π Tsw   2 2 ⋅π 
Maximum
i max i max
current (imax)
Turn-off
switched current i max 0
(ioff)
Maximum
voltage (vmax)
(Vin + ∆vCin ) (Vin + ∆vCin )
Turn-off
switched voltage (Vin − ∆vCin ) 0
(voff)
In this converter, transistors operate under ZVS conditions and freewheel diodes operate
under ZCS conditions. Thus, transistors turn-on losses and freewheel diodes turn-off
losses are neglected [23]. In consequence, switching power losses are given by the turn-
off losses of transistors:
Psw _ S1 =
(Vin − ∆vCin ) ⋅ (A ( )2 + Boff , S1 ⋅ imax + Coff , S1 )
off , S1 ⋅ imax (3.265)
Tsw ⋅ V100 FIT
(V − ∆vCout ) ⋅  A 
2
 n1 
⋅  i1 ⋅  + Boff , S 5 ⋅ i1 ⋅ 1 + Coff , S 5 
n
Psw _ S 5 = out   (3.266)
Tsw ⋅ V100 FIT  off , S 5 
  n2  n2

switch.
153
TABLE 3.40
EXPRESSIONS OF THE VOLTAGES/CURRENTS IN THE SEMICONDUCTORS OF THE OUTPUT SIDE H-BRIDGE
Current and
Transistors Freewheel diodes
voltage
S5-S6-S7-S8 DS5-DS6-DS7-DS8
expressions
i1 n1  ϕ t  n1 i t (i + i )  ϕ 
Average current (Iave) ⋅ ⋅  − a 
 ⋅  max ⋅ a + 1 max ⋅ 1 − 
2 n 2  2 ⋅ π Tsw  n2  2 Tsw 4  π 
n1 1  ϕ t  n1 1 
(
 2
)
2 1
 i1 + i max ⋅ i1 + i max ⋅  −
ϕ  
 +
 2 2 ⋅π  
rms current (Irms) i1 ⋅ ⋅ ⋅ − a  ⋅ ⋅
n2 3  2 ⋅ π Tsw 
 n2 3  2 ta 
+ i max ⋅ 
 Tsw 
Maximum current n1 n1
i max ⋅ i max ⋅
(imax) n2 n2
Turn-off switched n1
i1 ⋅ 0
current (ioff) n2
Maximum voltage
(vmax)
(Vout + ∆v Cout ) (Vout + ∆v Cout )
Turn-off switched
voltage (voff)
(Vout − ∆v Cout ) 0
2.3 Resonant mode DC-DC converters
The main benefit of resonant mode DC-DC converters resides in the reduction of the
switching stress due to the soft switching conditions they provide (zero current and/or
zero voltage switching). Consequently, switching power losses can be decreased and
therefore, higher efficiencies and lower EMIs are achieved. In turn, switching frequency
could be also increased in order to reduce the volume of the passive components.
However, their main drawback is the voltage/current stress in passive elements.
Generally speaking, resonant mode DC-DC converters can be divided in two groups:
resonant load converters and resonant switch (or quasi-resonant) converters [2]. In the
latter, the resonance is given in a smaller time interval than the switching period. This
way, the resonance is used to adapt the voltages and/or currents through the
semiconductors so as to achieve zero voltage switching (ZVS) and/or zero current
switching (ZCS) conditions. Conversely, in resonant load type converters, a resonant-tank
is excited to create oscillating voltages and currents that last all the switching period.
Controlling the switching instants of the semiconductors, a ZCS or a ZVS can be
achieved.
154
2.3. Resonant mode DC-DC converters
In this section, only resonant load DC-DC converters are considered. In these converters,
the amplitude of the output voltage is defined by the characteristic DC voltage gain
(voltage gain versus frequency) of the resonant-tank and the frequency of the applied
voltage. Furthermore, the resonant-tank acts as a filter, letting pass to determined
frequencies. If a DC output voltage is required, a rectifier must be used at the output
stage. The transferred power can be controlled varying the frequency of the square wave
voltage. However, despite of its effectiveness, this control method increases the difficulty
of the design of the passive elements [24]. This drawback can be addressed if the
converter is operated at a constant frequency and the applied fundamental voltage is
controlled varying the duty cycle [2].
In Fig 3.81, the general layout considered for the resonant load converters is shown. A H-
bridge converter has been considered as the input side inverter. Despite of the higher
semiconductor number, this converter has a better switch utilization than the half-bridge
inverter [2]. In addition, a diode bridge rectifier is considered in the output stage due to its
reliability and simplicity.
Iin
+ Iout
DS1 DS3
S1 S3 +
n1 : n2 D1 D3
Resonant-tank
+ +
Vin Cin Cout Vout
- iCin -
iCout
D4 D2
S4 S2 -
DS4 DS2
-
Fig 3.81. Layout of the considered resonant load DC-DC converters.
As stated in [25-26], the characteristics of the resonant-tank depend on its topology.

When two or more passive elements are connected in series (see Fig 3.82a), the resonant-
tank performs as a band-pass filter. If the switching frequency is close to the resonance
frequency, this topology offers low semiconductor switching losses and low energy
circulating through the tank. On the other hand, when the passive elements are connected
as shown by Fig 3.82b, the resonant-tank performs as a low-pass filter or a high-pass
filter. If a capacitor is shunt connected, a low-pass filter is obtained, whereas if an
inductor is shunt connected, a high-pass filter is obtained. This topology is a good choice
if a variable output voltage is required. A notch filter is obtained when the elements are
parallel connected as depicted in Fig 3.82c and Fig 3.82d. The notch filter is useful to
provide soft start-up to the converter and for protecting it against load side short circuits.
As it will be discussed later in this section, the resonant-tanks resulting from the
combination of the basic topologies of Fig 3.82 maintain the characteristics of each basic
topology.
155
Resonant-tank Resonant-tank Resonant-tank Resonant-tank
a) b) c) d)
Fig 3.82. Different resonant-tank topologies in which each dark-greyed box represents
one or more passive elements.
In this section, 10 different resonant-tank topologies are analysed and discussed. In order
to understand the behaviour of each tank, the DC voltage gain of each converter is
calculated. With these DC gain functions, the resonant-tank can be designed to operate at
any input and output voltages. Contrarily to the switch mode converters, it is easier and
more straightforward to calculate the power losses, and input and output DC bus
capacitances (Cin and Cout of Fig 3.81 respectively) by means of simulation (instead of
estimating them through analitycal approaches). In consequence, those analytical
expressions are not discussed in this chapter.
2.3.1 Series LC resonant-tank
The series LC resonant-tank shown in Fig 3.83a is a simple tank that can use the leakage
inductance of the MFT as part of the resonant-tank. Thereby, the total the amount of
components of the converter is reduced. Generally, the converter that includes this
resonant-tank is known as series-resonant converter [2, 8].
Resonant-tank
C Lr Cr Lr
+ r- + -
- -
+
Vin n1 V 4V R 4 n1 V
n2 out π in π n2 out
a) b)
Fig 3.83. a) Series LC resonant-tank. b) Equivalent circuit of the series-resonant

converter for fundamental voltage.
From Fig 3.83a, the impedance of the resonant-tank can be calculated:
1
Z R = j ⋅ ω ⋅ Lr + (3.267)
j ⋅ω ⋅ Cr
where ω is the fundamental frequency of the input square wave voltage and depends on
the switching frequency (fsw) of the converter:
ω = 2 ⋅ π ⋅ f sw (3.268)
156
The frequency at which the impedance of the resonant-tank is zero is known as the
resonance frequency (f0):
1 1
f0 = ⋅ (3.269)
2 ⋅π Lr ⋅ C r
In turn, the impedance of each passive element at the resonance frequency is known as
the characteristic impedance (Z0):
Lr
Z0 = (3.270)
Cr
In a first approach, assuming a purely resistive load and neglecting the non-linear
behaviour of the output rectifier (diode bridge and output capacitive filter, Cout), the
equivalent circuit of the series-resonant converter can be drawn as in Fig 3.83b. From this
equivalent circuit, the DC voltage gain can be calculated as:
V R Vout ⋅ n1 1
= =
Vin Vin ⋅ n 2  1  (3.271)
1 + j ⋅ ω n ⋅ Q s ⋅ 1 − 2 
 ω 
 n 
where Vin and Vout are the input and output voltages in the converter, n1/n2 is the turn ratio
of the MFT (see Fig 3.81), ωn is the normalized frequency (see Eq. (3.272)) and Qs is the
load factor, which represents the load intensity (see Eq. (3.273)). Therefore, the higher Qs
the heavier is the load and conversely, the lower Qs the lighter is the load.
f sw
ωn = (3.272)
f0
Z0 Z0
Qs = = 2
R 8 V ⋅n  (3.273)
⋅  out 1 
Pout  π ⋅ n2 
In Fig 3.84 the DC voltage gain is illustrated in function of the normalized frequency and
for different load factors. As it can be noticed, the resonant-tank performs as a band-pass
filter with no voltage gain (the output voltage of the resonant-tank is, at most, the same as
the input voltage). With light loads, the output voltage cannot be regulated by varying the
frequency. So, duty cycle control is preferred. Conversely, the output voltage varies
dramatically with heavy loads, especially, with switching frequencies close to the
resonance frequency. For convenience, this resonance frequency will be named as series
resonance frequency (SRF). At SRF and independently of the load intensity, the DC
voltage gain is always equal to 1 and the energy circulating through the tank is minimum.
157
ZCS ZVS
region region Light load
1
VR/Vin
0.75
0.5
0.25 Heavy load

0
0 0.5 1 1.5 2
fsw/f0
Fig 3.84. DC voltage gain of the series-resonant converter.
On the other hand, two regions are distinguished in Fig 3.84, the zero current switching
(ZCS) region and the zero voltage switching (ZVS) region. When the switching
frequency is lower than the SRF, the resonant-tank behaves as a capacitor, Eq. (3.267),
and the current through the tank leads the input voltage (cf. Fig 3.85a). Therefore, input
side transistors are turned-on in hard switching conditions while the turn-off is given in
ZCS conditions. Freewheel diodes are turned-off under hard switching conditions.
Furthermore, when the switching frequency is lower than f0/2, the current in the resonant-
tank result discontinuous. The commutations of all the switches are given at ZCS
conditions, so, switching losses are zero. If the power transmitted under these DCM
conditions is high, the maximum conduced current can achieve relatively high values.
v v DS3-DS4
S3-S4
S1-S2 DS1-DS2 Conducting DS3-DS4 DS1-DS2 S1-S2 Conducting
S3-S4
Conducting Conducting Conducting Conducting Conducting Conducting
Vin i Vin
t t
-Vin -Vin i
a) b)
Fig 3.85. Voltage applied to the resonant-tank of the series-resonant converter and the
current circulating through it when a) the resonant-tank behaves as a capacitor and b)
when the resonant-tank behaves as an inductor.
Conversely, when the switching frequency is higher than the resonance frequency, the
resonant-tank behaves as an inductor (cf. Fig 3.85b). Thus, the current through the tank
lags the input voltage. In consequence, input side transistors are turned-on in ZVS
conditions and freewheel diodes are turned-off under soft switching conditions. The turn-
off of the transistors is given under hard switching conditions. As the ZVS turn-on
condition allows the use of snubbers to reduce the turn-off losses of the transistors as well
as the diode switching stress, the operation in ZVS region is preferred.
158
The power losses of the converter are minimized when it operates with a switching
frequency close to the SRF. In theory, if the converter operates at the SRF, the impedance
of the resonant-tank is zero and the voltage is in phase with the current. This leads to
negligible switched currents. However, if snubbers are used, the switching frequency
must be slightly higher than the SRF to guarantee the operation in the ZVS region and
avoid the operation in the ZCS region.
2.3.2 Three-element resonant-tanks
Resonant-tanks with three passive elements provide the ability to combine and exploit the
advantages of two basic tank topologies (cf. Fig 3.82).
2.3.2.1 LLC
The LLC resonant-tank of Fig 3.86a is one of the most popular tanks in resonant mode
DC-DC converters [2, 18, 26-29]. This resonant-tank is a combination of the series and
parallel tanks in Fig 3.82a and Fig 3.82b. Therefore, it can be deduced that the LLC tank
behaves as a combination of a band-pass filter and a high-pass or low-pass filter (this will
be discussed later in this section). One advantage of this resonant-tank is that it can use
the leakage inductance and the magnetizing inductance of the MFT as part of the
resonant-tank. In that case, the transformer must be designed thoroughly to that end. The
resonant mode converter composed of this resonant-tank is known as LLC converter.
Resonant-tank
Cr Lr
Cr
+ -
Lr - + - -
+
+
+ +
Vin n1 V 4V Lp R 4 n1 V
Lp
- n2 out π in - π n2 out
a) b)
Fig 3.86. a) LLC resonant-tank. b) Equivalent circuit of the LLC converter for
fundamental voltage.
The equivalent circuit shown in Fig 3.86b makes possible to obtain the DC gain voltage
of this converter assuming a purely resistive load and neglecting the non-linearity of the
rectifier stage (output diode bridge and Cout capacitor):
V R Vout ⋅ n1 j ⋅ ω n ⋅ Q1
= =
Vin Vin ⋅ n 2 

1
j ⋅ ω n ⋅ 1 + Q1 − 2
ωn

(
 + Q1 ⋅ Qs ⋅ 1 − ω n 2

) (3.274)
 
where Vin and Vout are the input and output voltages in the DC-DC converter, n1/n2 is the
turn ratio of the MFT (cf. Fig 3.81) and ωn, Q1 and Qs are given by:
f sw
ωn = = f sw ⋅ 2 ⋅ π ⋅ Lr ⋅ C r (3.275)
f0
159
Lp
Q1 = (3.276)
Lr
Z0 Z Lr 1
Qs = = 0 = 2
⋅ 2
R 8  Vout ⋅ n1  Cr 8 V ⋅ n  (3.277)
⋅  ⋅  out 1 
Pout  π ⋅ n 2  Pout  π ⋅ n2 
where fsw is the switching frequency of the converter, Qs is the load factor, f0 is the SRF
and Z0 is the characteristic impedance of the SRF.
ZCS
region
3
VR/Vin
2
ZVS
region
Light load
1
Heavy load
0
0 0.5 1 1.5 2
f1/f0
fsw/f0
Fig 3.87. DC voltage gain of the LLC converter.
If Eq. (3.274) is graphed in function of ωn and for different load factors (Qs), Fig 3.87 is
obtained. As it can be noticed, under heavy load conditions the resonant-tank behaves as
a band-pass filter. In fact, the DC voltage gain at the SRF is always 1. However, if the
converter operates with light loads, the resonant-tank behaves as a high-pass filter. The
frequency at which the output voltage tend to infinity depends on the relation of the series
and parallel connected inductors, Eq. (3.278). For convenience, this resonance frequency
will be named as parallel resonance frequency (PRF). Close to PRF, if the converter
operates with light loads, it is possible to regulate the output voltage in a wide range.
Nevertheless, the operation in frequencies below SRF leads to high oscillating voltages
and currents in the passive elements, thereby increasing the switching power losses as
well as the amount of stored energy.
1
f1 f 0 ⋅
= (3.278)
(Q1 + 1)
As depicted in Fig 3.87, if the DC voltage gain has a positive slope, the current through
the tank leads the input voltage and thus, the transistors operate under ZCS conditions. If
the DC voltage gain slope is negative, the current through the tank lags the input voltage
and thus, the transistors operate under ZVS conditions. As discussed in the previous
section 3.3.1, operating in the ZVS region is more beneficial than operating in the ZCS
region since snubbers can be used in transistors, thereby reducing their turn-off switching
losses and increasing the overall efficiency of the converter. Moreover, if the converter is
160
designed to operate with light loads and with frequencies comprehended between the PRF
and the SRF (the converter must operate with variable frequency), the benefits of each
resonance can be combined. Thus, switching losses are reduced and the energy
circulating in the tank is minimum if the converter operates at switching frequencies close
to SRF for nominal loads. If the output voltage require to be increased, the switching
frequency is reduced and the converter takes advantage of the PRF (the voltage is
increased guaranteeing the operation in the ZVS region). In any case, the diodes in the
output side rectifier and the freewheel diodes are turned-off under soft switching
conditions.
2.3.2.2 LCC
The resonant-tank shown in Fig 3.88a is known as LCC and the DC-DC converter
composed of this resonant-tank is known as LCC converter.
Resonant-tank
Lr Cr
Lr - C
+ r-
-
+ -
+
+
+ +
Vin n1 V 4V Cp R 4 n1 V
Cp
a) b)
Fig 3.88. a) LCC resonant-tank. b) Equivalent circuit of the LCC converter for
The DC voltage gain is obtained from the equivalent circuit of the LCC converter drawn
in Fig 3.88b:
V R Vout ⋅ n1 1
= =
Vin Vin ⋅ n 2  1
j ⋅ ω n ⋅ Q s ⋅ 1 − 2
 ω

(
 +1+ Q ⋅ 1− ω 2
 1 n ) (3.279)
 n 
where Vin and Vout are respectively the input and output voltages, n1/n2 is the turn ratio of
the MFT (cf. Fig 3.81) and ωn, Q1 and Qs are given by:
f sw
ωn = = f sw ⋅ 2 ⋅ π ⋅ Lr ⋅ C r (3.280)
f0
Cp
Q1 = (3.281)
Cr
Z0 Z0 Lr 1
Qs = = 2
= ⋅ 2
R 8 V ⋅ n  Cr 8 V ⋅ n  (3.282)
⋅  out 1  ⋅  out 1 
Pout  π ⋅ n2  Pout  π ⋅ n2 
161
Fig 3.89 shows the DC voltage gain in function of ωn and with different load factors (Qs).
With heavy loads, the tank behaves as a band-pass filter while with light loads, the tank
behaves as a low-pass filter. At the SRF, independently of the load factor, the DC voltage
gain is always 1. Conversely, at the PRF, the output voltage tend to infinity. For a given
SRF, this resonance frequency depends on Q1:
1
f1
= f0 ⋅ 1+ (3.283)
Q1
The output voltage can be regulated in a wide range if the converter operates close to the
PRF. However, the energy stored by the resonant-tank is larger than that operating at the
SRF.
ZVS
3 region
ZCS
region
VR/Vin
1
Light load
Heavy load
0
0 1 2 3
f1/f0
fsw/f0
Fig 3.89. DC voltage gain of the LCC converter.
As it can be noticed in Fig 3.89, two different operational regions can be distinguished.
When the DC voltage gain has a positive slope, the resonant-tank behaves as a capacitor
and thus, the transistors operate under ZCS conditions. If the DC voltage gain slope is
negative, the resonant tank behaves as an inductor and thus, the transistors operate under
ZVS conditions. Finally, if fsw/f0<0.5, the converter operates in discontinuous current
mode (DCM) and in consequence, switching losses can be neglected.
In order to take advantage of the benefits of series and parallel resonance frequencies
(low energy circulation through the resonant-tank and voltage regulation capability), the
LCC converter must be operated in the ZCS region. In order to achieve negligible
switching power losses, it could be interesting to operate with a switching frequency
below f0/2 [30].
2.3.2.3 CLL
The CLL resonant-tank is depicted in Fig 3.90a. Similarly to the LLC resonant-tank
(section 3.3.2.1), the tank under discussion can use the leakage inductance and the
magnetizing inductance of the medium frequency transformer as part of the resonant-
162
tank. The converter composed of this resonant-tank is patented [31] and for convenience,
in this book will be named as CLL converter.
Resonant-tank
Cr Lr
Cr
+ -
Lr - + - -
+
+
+ +
Vin n1 V 4V Lp R 4 n1 V
Lp
a) b)
Fig 3.90. a) CCL resonant-tank. b) Equivalent circuit of the CLL converter for
For a purely resistive load and neglecting the non-linear behaviour of the output stage
rectifier, the equivalent circuit of the CLL converter can be illustrated as in Fig 3.90b.
From this circuit, the DC voltage gain is given by:
V R Vout ⋅ n1 1
= =
Vin Vin ⋅ n 2  1   1  1 (3.284)
j ⋅ ω n ⋅ Q s ⋅ 1 +  ⋅ 1 −  +1−

 Q1   ω n
2 
 ω n ⋅ (1 + Q1 )
2
where Vin and Vout are respectively the input and output voltages in the DC-DC converter,
n1/n2 is the turn ratio of the MFT (cf. Fig 3.81) and ωn, Q1 and Qs are given by:
f sw Lr ⋅ L p ⋅ Cr
ωn = = f sw ⋅ 2 ⋅ π ⋅ (3.285)
f0 (
Lr + L p )
Lp
Q1 = (3.286)
Lr
Z0 Z0 Lr ⋅ L p 1
Qs = = = ⋅
R 8 V ⋅ n 
2
(
Cr ⋅ Lr + L p ) 8 V ⋅ n 
2
(3.287)
⋅  out 1  ⋅  out 1 
Pout  π ⋅ n2  Pout  π ⋅ n2 
Fig 3.91 is obtained from Eq. (3.284). As illustrated in Fig 3.91, the tank behaves as a
band-pass filter with heavy loads, whereas with light loads, it behaves as a high-pass
filter. Conversely to the resonant-tanks discussed previously, the DC voltage gain of this
tank at SRF is not equal to 1. This voltage gain depends on the relation between the
parallel and series connected inductors:
1
SRFG = 1 + (3.288)
Q1
163
ZCS
region
3
ZVS
VR/Vin
2 region
SRFG Light load
1
Heavy load
0
0 0.5 1 1.5 2
f1/f0
fsw/f0
Fig 3.91. DC voltage gain of the CCL converter.
The PRF at which the output voltage tends to infinity is given by:
1
f1 f 0 ⋅
= (3.289)
(Q1 + 1)
It must be highlighted that to achieve a unity gain at the SRFG, a large shunt inductor is
required and in consequence, the tank will perform as a series-resonant tank (the effect of
the PRF will be negligible unless the converter operates with very light loads).
Depending on the switching frequency, the CLL converter can operate under ZCS or ZVS
conditions. If the converter is designed to operate with a light load between PRF and
SRF, the output voltage can be regulated in a wide range and the transistors operate under
ZVS conditions. At nominal conditions, the converter can operate close to SRF thereby
reducing the switching losses and the energy circulating through the tank. Under these
conditions, the diodes of the rectifier bridge as well as the freewheel diodes operate under
soft switching conditions.
2.3.2.4 LCL type 1
Fig 3.92a shows the LCL type 1 resonant-tank. Since it has an inductive element
connected in series with the load, the leakage inductance of the medium frequency
transformer could be integrated in the tank in order to optimize the converter design.
Resonant-tank
Lr - Ls - Lr - Ls -
+
+
+
+ +
Vin n1 V 4V Cr R 4 n1 V
Cr π in π n2 out
- n2 out -
a) b)
Fig 3.92. a) LCL type 1 resonant-tank. b) Equivalent circuit of the LCL type 1
164
For the resonant-tank analysis, a purely resistive load has been assumed. In consequence,
its equivalent circuit can be depicted as in Fig 3.92b, from which, the DC voltage gain is
obtained:
VR Vout ⋅ n1 1
= =
Vin Vin ⋅ n2 ( )
j ⋅ ω n ⋅ Qs ⋅ 1 + Q1 − Q1 ⋅ ω n 2 + 1 − ω n 2
(3.290)
where Vin and Vout are respectively the input and output DC voltages in the DC-DC
converter, n1/n2 is the turn ratio of the MFT (cf. Fig 3.81) and ωn, Q1 and Qs are given by:
f sw
ωn = =f sw ⋅ 2 ⋅ π ⋅ Lr ⋅ C r (3.291)
f0
Ls
Q1 = (3.292)
Lr
Z0 Z Lr 1
Qs = = 0 = 2
⋅ 2
R 8  Vout ⋅ n1  Cr 8 V ⋅ n  (3.293)
⋅  ⋅  out 1 
Pout  π ⋅ n2  Pout  π ⋅ n2 
where fsw is the switching frequency of the converter, Qs is the load factor, f0 is the PRF
and Z0 is the characteristic impedance of the PRF.
4
Mixed
region ZVS
VR/Vin
3
region
2
SRFG
1
Light load
Heavy load
0
0 0.5 1 f1/f0 1.5 2
fsw/f0
Fig 3.93. DC voltage gain of the LCL type 1 converter.
As it can be noticed in Fig 3.93, the performance of the tank depends on the load. At
heavy loads (high Qs) the tank performs as a band-pass filter, whereas for light loads, it
performs as a low-pass filter. The SRF is given by Eq. (3.294) and the voltage gain at this
frequency (SRFG) is given by Eq. (3.295). It can be observed that this voltage gain
depends on the relation between the inductive elements. Furthermore, the higher the SRFG
value, the lighter must be the load if significant voltage gain at the PRF is desired.
1
f1
= f0 ⋅ 1+ (3.294)
Q1
SRFG = Q1 (3.295)
165
In general, this converter must be designed to operate with light loads and between
parallel and series resonance frequencies of the ZVS region. Thus, the energy circulating
through the tank is minimum at nominal loads while the output voltage can be increased
reducing the switching frequency. Since the converter performs at the ZVS region,
snubbers connected in parallel to the transistors can be used. Under this conditions, turn-
off losses in the output rectifier are negligible.
2.3.2.5 LCL type 2
The LCL type 2 resonant-tank combines the tank topologies shown in Fig 3.82a and Fig
3.82c (see Fig 3.94a). Therefore, it can be deduced that the tank performs as a
combination of a band-pass filter and a notch filter. The latter can be useful for the start-
up process of the converter or short circuit protection. With an appropriate transformer
design, the series connected inductive element in Fig 3.94a (Ls) could be substituted by
the leakage inductance of the MFT. For convenience, the resonant mode converter
composed of a LCL type 2 resonant-tank will be named as LCL type 2 converter.
Resonant-tank
Lr - Ls - Lr - Ls -
+
+
+
+ - n2 out π in + - π n2 out
Cr Cr
a) b)
Fig 3.94. a) LCL type 2 resonant-tank. b) Equivalent circuit of the LCL type 2
Assuming a resistive load and neglecting the non-linear behaviour of the output rectifier,
the equivalent circuit of the LCL type 2 converter can be drawn as in Fig 3.94b. From this
circuit, the DC voltage gain is:
V R Vout ⋅ n1 1
= =
Vin Vin ⋅ n 2  1  (3.296)
j ⋅ ω n ⋅ Q s ⋅  Q1 + ⋅ + 1
 1− ωn 2 
 
converter, n1/n2 is the turn ratio of the MFT (cf. Fig 3.81) and ωn, Q1 and Qs are given by:
f sw
ωn = = f sw ⋅ 2 ⋅ π ⋅ Lr ⋅ C r (3.297)
f0
Ls
Q1 = (3.298)
Lr
Z0 Z0 Lr 1
Qs = = 2
= ⋅ 2
R 8 V ⋅ n  Cr 8 V ⋅ n  (3.299)
⋅  out 1  ⋅  out 1 
Pout  π ⋅ n2  Pout  π ⋅ n2 
166
where fsw is the switching frequency of the converter, Qs is the load factor, f0 is the notch
resonance frequency (NRF) and Z0 is the characteristic impedance of the NRF.
ZCS
ZVS region ZVS
region region
1
Light load
VR/Vin
0.75
0.5
0.25
Heavy load
0
0 1 f1/f0 2
fsw/f0
Fig 3.95. DC voltage gain of the LCL type 2 converter.
The DC voltage gain is illustrated in Fig 3.95 for different load factors. As it can be
observed, the maximum DC voltage gain of the tank is 1 (obtained at SRF), which means
the output voltage in the tank cannot be higher than the input voltage. In turn, it can be
noticed that the notch resonance frequency is lower than the series resonance frequency.
The latter depends on Q1 and the NRF as shown by the following expression:
1
f1
= f0 ⋅ 1+ (3.300)
Q1
If the converter is operated with variable switching frequencies below SRF and above
NRF, the transistors operate under ZCS conditions. At any other frequency, the transistors
operate under ZVS conditions and snubbers can be connected in parallel to them.
However, in general, the LCL type 2 converter should be designed to take advantage of
the characteristics provided by the SRF (low energy circulation and low losses) and the
benefits of operating in NRF (soft star-up and short circuit protection). In consequence,
the converter should operate in the ZCS region.
2.3.3 Four-element resonant-tanks
Four-element based resonant-tanks combine three different resonant-tank topologies and

in consequence, three different resonance frequencies can be obtained. Therefore, the
benefits provided by each resonance frequency can be exploited in a single converter.
2.3.3.1 LCLL
In the LCLL resonant-tank of Fig 3.96a, Ls and Lp inductors can be substituted by the
leakage inductance and the magnetizing inductance of the medium frequency transformer.
In consequence, the number of additional passive elements in the converter is kept low.
For convenience, the converter comprising this resonant-tank will be named as LCLL
converter.
167
Resonant-tank
Lr - Ls - Lr - Ls -
+
+
+
+
+ +
+ - Lp
π in + - Lp
π n2 out
Cr - n2 out Cr -
a) b)
Fig 3.96. a) LCLL resonant-tank. b) Equivalent circuit of the LCLL converter for
Under the assumption of a resistive load, the equivalent circuit of the LCLL converter can
be drawn as in Fig 3.96b. From this equivalent circuit, the DC voltage gain is obtained as:
V R Vout ⋅ n1 1
= =
Vin Vin ⋅ n 2  1  1  1  (3.301)
j ⋅ ω n ⋅ Qs ⋅  Q2 + + ⋅  Q1 + Q 2 + 
 1− ωn 2  Q1  1− ωn 2 
   
where Vin and Vout are the input and output DC voltages in the DC-DC converter, n1/n2 is
the turn ratio of the MFT (cf. Fig 3.81) and ωn, Q1, Q2 and Qs are given by:
f sw
ωn = = f sw ⋅ 2 ⋅ π ⋅ Lr ⋅ C r (3.302)
f0
Lp
Q1 = (3.303)
Lr
Ls
Q2 = (3.304)
Lr
Z0 Z0 Lr 1
Qs = = 2
= ⋅ 2
R 8 V ⋅ n  Cr 8 V ⋅ n  (3.305)
⋅  out 1  ⋅  out 1 
Pout  π ⋅ n2  Pout  π ⋅ n2 
where fsw is the switching frequency of the converter, Qs is the load factor, f0 is the NRF
and Z0 is the characteristic impedance of the NRF.
Fig 3.97 shows the DC voltage gain for different load factors. As it can be observed, the
resonant-tank performs as a combination of a notch filter, a high-pass filter and a band-
pass filter. At heavy loads, the band-pass filter prevails to the high-pass filter, whereas at
light loads the opposite occurs. The DC voltage gain is equal to 1 at the SRF.
Furthermore, for a given notch resonance frequency, the parallel and series resonance
frequencies are given by Eq. (3.306) and Eq. (3.307) respectively. As it can be noticed,
the SRF depends on Ls while the PRF depends on Ls and Lp.
(1 + Q1 + Q2 )
f1 = f 0 ⋅ (3.306)
(Q1 + Q2 )
168
(1 + Q2 )
f2
= f0 ⋅ (3.307)
Q2
ZCS
region
3
ZVS
2
region
VR/Vin
ZVS
region
1 Light load
Heavy load
0
0 1 f2/f0 2 3
f1/f0
fsw/f0
Fig 3.97. DC voltage gain of the LCLL converter.
If the converter is designed to operate in the ZVS region (cf. Fig 3.97), with light loads
and with frequencies comprehended between the PRF and the SRF, the benefits of each
resonance can be combined (low power losses and low energy circulation at nominal
conditions and wide voltage regulation capability). In addition, the rectifier diodes
operate under ZCS conditions and the switching losses of the freewheel diodes are
negligible. Under this conditions, the ZCS region must be crossed to reach the NRF.
2.3.3.2 LLCL
The LLCL resonant-tank shown in Fig 3.98a can integrate the leakage inductance of the
medium frequency transformer and in consequence, the number of passive elements in
the converter can be slightly reduced. For convenience, the converter comprising this
resonant-tank will be named as LLCL converter.
Resonant-tank
Ls1 Ls2 Ls1 - Ls2 -
+
+
- -
+
+
+ +
Lr Lr
4V 4 n1 V
Vin n1 V R
-
π in π n2 out
-
n2 out
+ +
Cr Cr -
-
a) b)
Fig 3.98. a) LLCL resonant-tank. b) Equivalent circuit of the LLCL converter for
The performance of the resonant-tank can be easily analyzed under the assumption of a
resistive load. Hence, the equivalent circuit of the LLCL converter can be illustrated as in
Fig 3.98b, from which, the DC voltage gain is calculated as given by Eq. (3.308).
169
V R Vout ⋅ n1 1
= =
Vin Vin ⋅ n 2  Q ⋅ Q ⋅ω 2  2
j ⋅ ω n ⋅ Q s ⋅  Q1 + Q 2 + 1 22 n  + 1 + Q2 ⋅ ω n (3.308)
 ωn −1  ωn 2 −1
 
converter, n1/n2 is the turn ratio of the MFT (cf. Fig 3.81) and ωn, Q1, Q2 and Qs are given
by:
f sw
ωn = =f sw ⋅ 2 ⋅ π ⋅ Lr ⋅ C r (3.309)
f0
Ls 2
Q1 = (3.310)
Lr
L s1
Q2 = (3.311)
Lr
Z0 Z Lr 1
Qs = = 0 = 2
⋅ 2
R 8  Vout ⋅ n1  Cr 8 V ⋅ n  (3.312)
⋅  ⋅  out 1 
Pout  π ⋅ n2  Pout  π ⋅ n2 
ZVS
region
3
ZCS
region
2
VR/Vin
ZCS
SRFG region
1
Light load
Heavy load 0
0 f2/f0 1 2
f1/f0
fsw/f0
Fig 3.99. DC voltage gain of the LLCL converter.
The DC voltage gain of the tank is illustrated in Fig 3.99. As it can be noticed, DC
voltage gain depends on the load factor and the switching frequency of the converter. The
DC voltage gain at the series resonance frequency can be derived from Eq. (3.308) and
depends on Ls1 and Ls2:
Q1 Ls 2
SRFG = = (3.313)
Q2 L s1
170
In turn, the parallel and series resonance frequencies are given by Eq. (3.314) and Eq.
(3.315) respectively. For a given notch resonance frequency, the PRF depends on Ls1
while the SRF depends on the two series connected inductive elements.
1
f1 = f 0 ⋅ (3.314)
(1 + Q2 )
(Q1 + Q2 )
f2 = f0 ⋅ (3.315)
(Q1 + Q2 + Q2 ⋅ Q1 )
Determined by the inductive or the capacitive behaviour of the resonant-tank, three
different regions can be distinguished in Fig 3.99. When the tank performs capacitively,
transistors are turned-off in ZCS conditions (ZCS region). Whereas, when the tank
performs inductively, transistors are turned-on in ZVS conditions and the reverse
recovery current in the freewheel diodes is negligible (ZVS region). In turn, capacitive
snubbers can be used to reduce the turn-off switching losses. Operating in the ZVS
region, low power losses and low energy storage can be achieved close to the SRF.
Furthermore, wide voltage regulation capability is achieved if the converter is designed to
operate with light loads and, additionally, the converter can take advantage of the short
circuit protection and soft start-up provided by the NRF.
2.3.3.3 CLCL
In the CLCL resonant-tank of Fig 3.100a, the leakage inductance of the medium
frequency transformer can be integrated in the tank, thereby reducing the number of
passive elements in the converter. In this book, the converter comprising the CLCL
resonant-tank is named as CLCL converter.
Resonant-tank
C Ls
Cs Ls + s-
-
+ -
+
-
+
+ +
Lr Lr
4V - 4 n1 V
Vin n1 V R π n2 out
π in
-
+
+ n2 out Cr
Cr
- -
a) b)
Fig 3.100. a) CLCL resonant-tank. b) Equivalent circuit of the CLCL converter for
Assuming a purely resistive load, the equivalent circuit of the CLCL converter can be
illustrated as in Fig 3.100b. From this circuit, the DC voltage gain is expressed as:
V R Vout ⋅ n1 1
= =
Vin Vin ⋅ n 2  1 1  (3.316)
Q
j ⋅ ω n ⋅ Qs ⋅ 1 ⋅  Q2 + −  +1+ 1 ⋅ 1
Q2   1− ωn 2
Q1 ⋅ ω n 2  Q2 1 − ω n 2

171
where Vin and Vout are the input and output DC voltages in the DC-DC converter, n1/n2 is
the turn ratio of the MFT (cf. Fig 3.81) and ωn, Q1, Q2 and Qs are given by:
f sw
ωn = =f sw ⋅ 2 ⋅ π ⋅ Lr ⋅ C r (3.317)
f0
Ls
Q1 = (3.318)
Lr
Cs
Q2 = (3.319)
Cr
Z0 Z Lr 1
Qs = = 0 = 2
⋅ 2
R 8  Vout ⋅ n1  Cr 8 V ⋅ n  (3.320)
⋅   ⋅  out 1 
Pout  π ⋅ n2  Pout  π ⋅ n2 
ZCS
6 region
ZVS
region
VR/Vin
4
SRFG2
2 ZVS
region Light load
SRFG1 Heavy load
0
0 f1/f0 1 f3/f0 2
fsw/f0 f2/f0
Fig 3.101. DC voltage gain of the CLCL converter.
The DC voltage gain is depicted in Fig 3.101 for different load factors. As it can be
noticed, apart from the notch resonance frequency, the tank has three additional
resonance frequencies, two series resonance frequencies and a parallel resonance
frequency. The DC voltage gains at the series resonance frequencies are provided by:
Q1 ⋅ Q 2 − 1 − Q1 + λ
SRFG1 = (3.321)
Q1 ⋅ Q 2 − 1 + Q1 + λ
1 − Q1 ⋅ Q 2 + Q1 + λ
SRFG 2 = (3.322)
1 − Q1 ⋅ Q 2 − Q1 + λ
where λ is given as:
=λ 1 − 2 ⋅ Q1 ⋅ (Q2 − 1 − Q1 ⋅ Q2 ) + (Q1 ⋅ Q2 )2 + Q1 2 (3.323)
172
In turn, the mentioned series and parallel resonance frequencies can be expressed as:
1 + Q1 ⋅ (Q 2 + 1) − (1 + Q1 ⋅ (Q2 + 1))2 − 4 ⋅ Q2 ⋅ Q1
f1 = f 0 ⋅ (3.324)
2 ⋅ Q 2 ⋅ Q1
1
f 2 = f0 ⋅ 1+ (3.325)
Q2
1 + Q1 ⋅ (Q 2 + 1) + (1 + Q1 ⋅ (Q2 + 1))2 − 4 ⋅ Q2 ⋅ Q1
f3 = f0 ⋅ (3.326)
2 ⋅ Q 2 ⋅ Q1
As it can be observed, for a given notch resonance frequency, the parallel resonance
frequency depends on the series connected capacitor Cs.
Operating between the PRF and SRF of the ZVS region, low energy storage and low
power losses are achieved. Furthermore, the output voltage regulation capability is wide.
However, the ZCS region must be crossed to reach the NRF.
2.3.4 CLCLL resonant-tank
With five passive elements the resonant tank provides the benefits of five different
resonant frequencies. Conversely, the reliability is reduced due to the high number of
passive components. Among the different resonant-tanks composed of five passive
elements, only the CLCLL resonant-tank shown in Fig 3.102a has been analyzed due to
its capability to transfer the energy though the third harmonic current component. In turn,
the leakage and magnetizing inductances of the MFT can be included in the CLCLL tank
and therefore, the design of the converter can be optimized in terms of volume. For
convenience, the converter comprising this resonant-tank will be named as CLCLL
converter.
Resonant-tank
C Lr Ls C Lr Ls
+ s- + s-
- - - -
+
+
+
+ +
+ - Lp
π in + - Lp
π n2 out
Cr - n2 out Cr -
a) b)
Fig 3.102. a) CLCLL resonant-tank. b) Equivalent circuit of the CLCLL converter for
The equivalent circuit of the CLCLL converter can be illustrated as in Fig 3.102b if a
resistive load is assumed. From this equivalent circuit, the DC voltage gain of the
converter is expressed as shown by Eq. (3.327).
173
V R Vout ⋅ n1
= =
Vin Vin ⋅ n 2
1 (3.327)
=
 1 1  1  1 1 
j ⋅ ω n ⋅ Qs ⋅  Q2 + − + ⋅  Q1 + Q 2 + − 
 1− ωn 2
Q3 ⋅ ω n 2  Q1  1− ωn 2
Q3 ⋅ ω n 2 
   
where Vin and Vout are respectively the input and output voltages, n1/n2 is the turn ratio of
the MFT (cf. Fig 3.81) and ωn, Q1, Q2, Q3 and Qs are given by:
f sw
ωn = =f sw ⋅ 2 ⋅ π ⋅ Lr ⋅ C r (3.328)
f0
Lp
Q1 = (3.329)
Lr
Ls
Q2 = (3.330)
Lr
Cs
Q3 = (3.331)
Cr
Z0 Z Lr 1
Qs = = 0 = 2
⋅ 2
R 8  Vout ⋅ n1  Cr 8 V ⋅ n  (3.332)
⋅  ⋅  out 1 
Pout  π ⋅ n 2  Pout  π ⋅ n2 
ZCS
region
7
5 ZCS
region
VR/Vin
3 ZVS ZVS
region region
Light load
1
Heavy load
0
0 f1/f0 f2/f0 1 f3/f0 f4/f0 2
fsw/f0
Fig 3.103. DC voltage gain of the CLCLL converter.
The DC voltage gain can be illustrated as in Fig 3.103 for different load factors. As it can
be observed, the resonant-tank performs as a combination of a notch filter, two high-pass
filters and two band-pass filters. The DC voltage gain at the series resonance frequencies
174
2.4. Summary
is always equal to 1 and the parallel and the series resonance frequencies in Fig 3.103 can
be derived from Eq. (3.327):
Q3 ⋅ (Q 2 + Q1 + 1) + 1 − (Q3 ⋅ (Q2 + Q1 + 1) + 1)2 − 4 ⋅ Q3 ⋅ (Q2 + Q1 )

f1 = f 0 ⋅ (3.333)
2 ⋅ Q3 ⋅ (Q 2 + Q1 )
Q3 ⋅ (Q 2 + 1) + 1 − (Q3 ⋅ (Q2 + 1) + 1)2 − 4 ⋅ Q3 ⋅ Q2

f2 = f0 ⋅ (3.334)
2 ⋅ Q3 ⋅ Q 2
Q3 ⋅ (Q 2 + Q1 + 1) + 1 + (Q3 ⋅ (Q2 + Q1 + 1) + 1)2 − 4 ⋅ Q3 ⋅ (Q2 + Q1 )

f3 = f0 ⋅ (3.335)
2 ⋅ Q3 ⋅ (Q 2 + Q1 )
Q3 ⋅ (Q 2 + 1) + 1 + (Q3 ⋅ (Q2 + 1) + 1)2 − 4 ⋅ Q3 ⋅ Q2

f4 = f0 ⋅ (3.336)
2 ⋅ Q3 ⋅ Q 2
As it can be observed in Eq. (3.334) and in Eq. (3.336), the series resonance frequencies
depend on Q2 and Q3. In order to transfer the energy through the third harmonic
component, the frequency of the second band-pass filter (f4) must be three times higher
than the first band-pass frequency (f2). In consequence, Q2 and Q3 must satisfy the
following relations:
16
Q2 = (3.337)
15
5
Q3 = (3.338)
3
If the converter is designed according to Eq. (3.337) and Eq. (3.338), and is operated in
the ZVS region between the first parallel and series resonance frequencies, low energy
storage and low power losses are achieved. In addition, the output voltage can be
regulated in a wide range. Moreover, the converter can operate in the NRF for providing
soft star-up and for protecting it against output side short circuits.
2.4 Summary
In this chapter, several switch mode and resonant mode DC-DC converter topologies
have been thoroughly analysed and modelled.
In the first part of this chapter, 17 different switch mode DC-DC converters have been
discussed, found among them, converters with or without galvanic isolation capability,
and complex or simple (composed of few elements) converters. High reliability and cost
reduction can be achieved by using simple converters. However, depending on the input
and output voltage, power ranges of the application, etc. more complex converter
175
topologies must be considered. In a similar way, depending on the secondary side voltage
level and galvanic isolation requirements, the use of a converter with a medium frequency
transformer that provides galvanic isolation must be assumed. For all switch mode DC-
DC converters, design and efficiency evaluation tools are discussed, i.e. analitycal
equations for passive element sizing and semiconductor power loss estimation
expressions are shown. Furthermore, by means of the semiconductor utilization factor
expression, the optimal design point of the converters is calculated.
In the second part of this chapter, 10 different resonant mode DC-DC converters have
been studied. All of them provide galvanic isolation by means of a medium frequency
transformer. Furthermore, the structure of the analysed converters is the same, a H-bridge
at the input side followed by a medium frequency transformer and a diode rectifier at the
output side. Thus, the resonant-tank topology is the only differece between the discussed
converters. By analysing the transfer function of these resonant-tanks, the DC voltage
gain expression of each resonant mode DC-DC converter topology is estimated.
Additionally, switching frequency dependent operational regions of the converters are
identified, i.e. zero voltage switching and zero current switching regions. Based on the
reduction of the semiconductor power losses in these regions, optimal converter design
regions are adviced.
All in all, it can be said that this chapter provides the basic tools to select the appropriate
DC-DC converter for a given application.
176
Chapter 3
Medium frequency
transformer
The medium frequency transformer is a key component of some of the DC-DC converters
analysed in the previous chapter. Generally, although the behaviour of these converters
can be understood considering an ideal transformer, the leakage and the magnetizing
inductances affect the behaviour of the real converters. So, these parameters must be
carefully designed. In addition, the thermal behaviour and the space requirements of the
transformers must be considered during the design process. The design of the medium
frequency transformer is challenging due to the operation at high frequency and with
non-sinusoidal current and voltage waveforms. Therefore, this chapter details the design
of the medium frequency transformer.
3.1 Introduction
The transformer is an electrical device that magnetically couples two or more electrical
circuits that, generally, have different voltage levels. The design of low frequency
transformers is an addressed process [32], however, when the operating frequency
increases, the design of the transformer becomes challenging [33]. At high frequencies,
the influence of the skin and the proximity effects in the windings is more noticeable.
These effects increase the resistance of the conductors and in consequence, the power
losses and the temperature of the transformer are increased. The operation at high
temperature increases even more the windings resistance. On the other hand, core power
177
Chapter 3. Medium frequency transformer
losses also increase along with the frequency. So, it can be concluded that the thermal
stability of the medium frequency transformer is a challenging design issue.
The standard transformer design criteria considers sinusoidal current and voltage
waveforms. However, the medium frequency transformers (MFTs) in the analysed DC-
DC converters (cf. Chapter 3) operate with non-sinusoidal waveforms. This makes invalid
the standard design criteria and demands more advanced calculation methods [34].
Hence, this chapter analyses the design of the MFT. The selection of the transformer
geometry (core and winding geometry) is discussed and appropriate conductor and core
materials are introduced. Furthermore, methods for the calculation of the leakage
inductance, the magnetizing inductance and the power losses are described. Finally, a
design procedure for the MFT is presented, which, for given technical specifications
(nominal power, operational frequency, isolation requirement, etc.), outputs the optimum
transformer design.
3.2 Geometry of the transformer
Generally speaking, the geometry of the transformer depends on the operational

specifications, the core shape and the selected core materials, insulators and conductors.
3.2.1 Core
So far, the constructed MFT prototypes are mainly based on four core materials
(amorphous alloys, nanocrystallines, ferrites and silicon-steel materials) and three
different transformer geometries (coaxial-type, shell-type and core-type) [35-36]. On the
one hand, the use of core materials with high saturation flux minimizes the core cross
sectional area (Score) compared to that required by the materials with a low saturation flux,
see Eq. (4.12). This leads to a higher power density transformer design. Generally
speaking, the saturation flux of amorphous alloys, nanocrystallines and silicon-steel based
materials are above 1.1T while that of ferrites is about 0.45T [37]. However, it must be
highlighted that due to their demanding manufacturing process, the cost of these materials
is higher than the cost of ferrites [36].
On the other hand, coaxial-type transformers (Fig 4.1a) are built through ring shaped core
structures while shell-type (Fig 4.1b) and core-type (Fig 4.1c) transformers are built
through C-shaped core structures. Due to their orbital shaped geometry, coaxial-type
transformers are appropriate for high power applications [34]. Nonetheless, even though
they achieve high isolation levels, the difficulty of independently selecting the number of
primary and secondary turns due to the coaxial cable they use limits their design
flexibility [36]. Therefore, this type transformers are discarded in this book.
178
3.2. Geometry of the transformer
Windings
Core Core
Core Core
Windings Windings Windings
a) b) c)
Fig 4.1. a)Typical coaxial-type transformer. b) Typical shell-type transformer.
c) Typical core-type transformer.
An advantage of shell-type and core-type transformers is that the use of C-shaped core
structures is very common in industrial applications and therefore, its availability is very
high. Compared to core-type transformers, shell-type transformers make easier the design
of the MFT to achieve a desired leakage inductance. In turn, when the windings in the
core-type transformer are placed in different legs, the minimization of the leakage
inductance is a very difficult task. In [33] it is stated that for the same volume, a shell-
type transformer requires 15% more core material and 36% less winding material than a
core-type transformer. As discussed in [35], this suggests that shell-type transformers are
more suitable for high voltage applications than core-type transformers. All in all, in the
present book only shell-type transformers are considered (cf. Fig 4.2a).
The volume of a shell-type core depends on the required window area (Wa), the core cross
sectional area (Acore) and the depth of the core (z). As it can be noticed in Fig 4.2b, the
window area depends on the diameter of the winding cables, their number of turns, the
number of layers and the required amount of insulating material. Therefore, the window
area can be expressed as:
( )
W a = l ⋅ h = m1 ⋅ d c1 + m 2 ⋅ d c 2 + d ins1 + d f 2 + d f 1 ⋅ h (4.1)
where m1 and m2 are respectively the number of layers of the primary and the secondary
windings, dc1 and dc2 are the diameters of the cables in the primary and the secondary
windings, dins1 is the insulation distance between the primary and the secondary windings,
df1 is the insulation distance between the primary winding and the core, df2 is the
insulation distance between the secondary winding and the core and h is the height of the
window.
The window height must be large enough to shelter the primary and secondary windings.
Since both windings are different, the winding with the larger window height requirement
determines the window height (note that the last turn of the ending loop in each winding
must be taken into account):
h = max(h x,min ) (4.2)
179
n 
h1, min =  1 + 1 ⋅ d c1 + 2 ⋅ d f 1 (4.3)
 m1 
n 
h2, min =  2 + 1 ⋅ d c1 + 2 ⋅ d f 2 (4.4)
 m2 
where h1,min is the minimum height of the primary winding, h2,min is the minimum height
of the secondary winding and n1 and n2 are respectively the primary and the secondary
turn numbers.
Windings
Core
a)
m2 m1
{
{
dc2 df1 Primary Core

Secondary winding
winding
Insulator z
material
Acore
h
dins3 dins2
a/2
df2 dins1 dc1 a l a/2

b)
Fig 4.2. a)Typical shell-type transformer's frontal and upper views. b) Detailed
illustration of the considered shell-type transformer.
Vertical isolation distances dins2 and dins3 are given by the winding that determines the
maximum height. Therefore, if the maximum height is determined by the primary
winding (h1,min), dins2 and dins3 will be respectively expressed as in Eq. (4.5) and Eq. (4.6).
Whereas, if the maximum height is determined by the secondary winding (h2,min), dins2 and
dins3 will be respectively expressed as in Eq. (4.7) and Eq. (4.8).
d ins 2 = d f 1 (4.5)
180
(h1,min − h2,min )
d ins 3 = d f 2 + (4.6)
2
(h2,min − h1,min )
d ins 2 = d f 1 + (4.7)
2
d ins 3 = d f 2 (4.8)
The isolation distances inside the window depend on the required isolation level (voltages
in the primary and the secondary sides) and the used insulation material. Dry-type soft
potted insulators as EPOXY or Micares are attractive insulator materials due to their
flexible mechanical characteristics and their high dielectric strengths, 16 kV/mm and 8-24
kV/mm respectively [38]. Thus, isolation distances can be expressed as follows:
V pri
d f1 = (4.9)
ν ⋅ E ins
V se
df2 = (4.10)
ν ⋅ E ins
(V se − V pri )
d ins 2 = (4.11)
ν ⋅ E ins
where Vpri and Vse are the voltages in the primary and the secondary windings
respectively, Eins is the dielectric strength of the used insulator material and ν is the safety
margin considered for the isolation distances.
For given technical specifications, the core cross sectional area (Acore) depends on the
maximum saturation flux (Bsat) of the selected core material:
V pri , avg ⋅ ∆T
Acore = (4.12)
2 ⋅ n1 ⋅ (1 − ξ ) ⋅ B sat
where Vpri,avg is the average voltage applied to the primary side winding in a ΔT time
period and ξ is the safety margin considered for the saturation flux (typically 0.1-0.2
[38]).
The width of the central leg of the core (a) depends on the depth of the core itself (z):
Acore
a= (4.13)
z
Considering that the transformer is made up by four C-shaped cores, it can be said that
the width of the central leg is two times that of the lateral legs as it has been illustrated in
Fig 4.2b. Thus, the core volume of the discussed shell-type MFT can be expressed as:
Vcore = Acore ⋅ (2 ⋅ a + 2 ⋅ l + h ) (4.14)
3.2.2 Windings
In the design process the medium frequency transformer, the skin and proximity effects
must be taken into account. The skin effect is a non-uniform current distribution through
181
the cable caused by the magnetic field created by the AC current circulating in the cable.
This magnetic field induces opposite currents, known as eddy currents, that increase the
current density in the outer surface area and reduce it in the inner area (cf. Fig 4.3a). The
penetration of these currents is known as the skin depth:
1
δ = (4.15)
π ⋅ f ⋅ µ ⋅σ
where f is the frequency of the current, μ is the permeability of the material (≈1.256·10-6
turns/A2 for copper) and σ is the conductivity of the material (≈5.688·107 S/m for copper).
Similarly, the proximity effect is a non-uniform current distribution through the cable
caused by the magnetic field created by the AC current circulating in the adjacent cables.
The use of stranded, insulated and twisted cables reduces the influence of the skin and
proximity effects. The reduced surface area of each strand reduces the skin effect (the
skin depth is equal or smaller than the cable radius) while the proximity effect is reduced
twisting the strands [35]. The twisted and stranded conductors are known as Litz-cables
(cf. Fig 4.3b). Consequently, these cables are usually preferred for MFT applications [36].
Cable cross sectional area

dcable
δ
H
Cable ieddy ieddy
surface i i
i
dstrand
a) b)
Fig 4.3. a) Graphical representation of the skin effect. b) Cross sectional illustration of
a Litz-cable.
In [33] a procedure to calculate the optimal strand diameter is presented, however,

manufacturers tend to provide standard strand diameters (dstrand) for certain operation
frequencies [39]. For this reason, the strand diameters considered in this book are the
ones provided by the manufacturers. The number of strands required by the cable depends
on the assumed current density and the copper area required by the current circulating
through the cable. For naturally cooled transformers, the maximum allowable current
density in the cables (J) is about 1.7-2 A/mm2 [33]. Hence, for a specific rms current
circulating through the cable (Irms), the required copper area is given by:
I rms
Aideal = (4.16)
J
From a given copper area, the number of strands can be derived from:
182
Aideal ⋅ 4
ns = (4.17)
d strand 2 ⋅ π
The diameter of the Litz-cable (dcable) is determined by the number of strands and the
thickness of the insulator material. As a first approach, it can be assumed that the
insulator material is distributed in the outer side of the cable as illustrated in Fig 4.4.
dcable
rcopp
0.5·dins,cable
Fig 4.4. Simplified approach of the required copper and insulator in a Litz-cable.
The thickness of the insulator material depends on its dielectric strength and the winding
process, which determines the voltage isolation requirements.
a) b)
Fig 4.5. Graphical representation of different coil winding processes where the
direction of the winding process is pointed by the arrow. a) The horizontal layers are
coiled first. b) The vertical layers are coiled first.
If the winding process is the one illustrated in Fig 4.5a (where the layers are coiled first),
the required insulation thickness can be estimated by Eq. (4.18). This winding process
leads to a good distribution of the parasitic capacitances between the cables and is a good
solution if few layers are required. Conversely, if the winding process is the one
illustrated in Fig 4.5b, the required insulation thickness can be estimated by Eq. (4.19).
This winding process is a good solution if high number of layers are required. However,
this second solution leads to a non-uniform parasitic capacitances distribution.
Vx m
d ins , cable = ⋅ x (4.18)
ν ⋅ Eins ,cable 2 ⋅ nx
Vx
dins ,cable = (4.19)
ν ⋅ Eins ,cable ⋅ mx
183
where Vx is the voltage applied to the winding, nx and mx are respectively the number of
turns and the number of layers, Eins,cable is the dielectric strength of the selected insulator
material and ν is the safety margin considered for the isolation distances. A commonly
used insulator material in Litz-cables is nylon [39], whose dielectric strength is about
14kV/mm.
Therefore, the cable diameter can be approached as:
d cable = 2 ⋅ rcopp + d ins ,cable (4.20)
rcopp is the equivalent copper radius given by Eq. (4.21), where the distances between each
strand as well as the thickness of the isolator material of each strand have been neglected.
d strand
rcopp = ⋅ ns (4.21)
2
Once the cable diameter is known, the packing factor (i.e. the relation between the area of
the cable and the area of each strand) of the cables is calculated with:
2
d 
pf = n s ⋅  strand 
 (4.22)
 d cable 
On the other hand, the volume required by the windings can be calculated from Fig 4.2,
which gives:
V w = l ⋅ h ⋅ [2 ⋅ (a + z ) + l ⋅ π ] (4.23)
3.2.3 Magnetizing and leakage inductances
Transformers can be ideally represented by a magnetizing inductance (Lm), the leakage

inductance of each winding (Lσ1 and Lσ2) and their equivalent series resistances (cf. Fig
4.6). Since the leakage and the magnetizing inductances affect the behaviour of the
converters analysed in section 3.3, these parameters must be carefully designed.
Rσ1 Lσ1 n1 : n2 Lσ2 Rσ2
Vn1 Lm Rm Vn2
Fig 4.6. Equivalent circuit of a transformer.
3.2.3.1 Magnetizing inductance
The magnetizing inductance of the transformer can be estimated in a relatively easy way
through the equivalent magnetic circuit of the transformer. The magnetic circuit of the
shell-type transformer can be drawn as in Fig 4.7a under the assumption of uniform
magnetic flux distribution in the core and considering the leakage flux is negligible
comparing to the magnetizing flux.
184
ϕ Rgap
F Rcore F Rcore
ϕ
a) b)
Fig 4.7. a) Equivalent magnetic circuit of the shell-type transformer. b) Equivalent
magnetic circuit of the shell-type transformer with an air gap.
From Ampere's law, the magnetomotive force (F) in Fig 4.7a can be defined as:
  
F = ∫ H ⋅ dl = ∑ H ⋅ l = N ⋅ i = n1 ⋅ i = φ ⋅ Rcore (4.24)
where ϕ is the magnetic flux through the core, n1 represents the number of turns in the
primary winding and Rcore is the core reluctance, which depend on the core cross sectional
area (Acore) and its length (lcore):
l core
Rcore = (4.25)
Acore ⋅ µ r ,core ⋅ µ 0
where μr,core is the relative permeability of the core material (generally between 104 and
105 for nanocrystalline materials [40]) and μ0 is the vacuum permeability (4π·10-7
turns/A2).
Hence, the magnetizing inductance can be expressed as:
N2 n2 n1 2 ⋅ Acore ⋅ µ r ,core ⋅ µ 0 n1 2 ⋅ Acore ⋅ µ r ,core ⋅ µ 0

Lm = = 1 = = (4.26)
R Rcore l core 2 ⋅ (l + h + a )
If an air gap is introduced in the core (Fig 4.7b), the magnetizing inductance becomes
very dependent on the air gap length (lgap). Thus, the desired magnetizing value can be
accomplished with a good accuracy:
N2 n2 n 2 ⋅ Acore ⋅ µ 0 n1 2 ⋅ Acore ⋅ µ 0
Lm = = 1 = 1 =
R Rcore l
l gap + core 2 ⋅ (l + h + a ) − l gap (4.27)
µ l gap +
r ,core µ r ,core
3.2.3.2 Leakage inductance
The flux that leaks from the core and returns through the air is represented by the leakage
inductance. Neglecting the skin and proximity effects and assuming a constant current
density in the windings, this phenomena can be represented as in Fig 4.8a. As it can be
noticed, the magnetic field in the core window increases linearly until the maximum
value is achieved in the region between the primary and the secondary windings. Then,
the magnetic field decreases linearly until the field value reaches to zero (after the last
layer of the secondary winding). From this magnetic field distribution, the energy stored
in the core window and in consequence, in the leakage inductance, can be estimated
through Eq. (4.28).
185
1 µ µ l
Wσ = ⋅ ∫ H ⋅ B dV = 0 ⋅ ∫ H 2 dV = 0 ⋅ ∫ H 2 ⋅ (MTL ⋅ h ) dx =
2 V 2 V 2 0
µ0 m1 ⋅d c1l  n ⋅ i ⋅ x  2 m1 ⋅d c1 + d ins1

 m1 ⋅ n1 ⋅ i1 
2
= ⋅ (MTL ⋅ h ) ⋅ ∫ 
  1 1
 dx + ∫  h  dx +
2  0  h ⋅ m1 ⋅ d c1 
 m1 ⋅d c1
(4.28)
m1 ⋅d c1 + d ins1 + m2 ⋅d c 2 2
 m1 ⋅ n1 ⋅ i1   m1 ⋅ d c1 + d ins1 − x 
2 
+ ∫   ⋅  + 1 dx  =
 h   m2 ⋅ d c2  
m1 ⋅d c1 + d ins1 
µ 0 ⋅ (n1 ⋅ i1 )2 ⋅ MTL  m1 ⋅ d c1 m2 ⋅ d c2 
= ⋅  + d ins1 + 
2⋅h  3 3 
where h is the height of the window and MTL is the mean turn length of the windings
illustrated in Fig 4.8b.
m2
m1
{
ϕσ
{
dins1
dc1 df2 Secondary
winding
Windings
Core
Mean turn length (MTL)

Primary df1 dc2
winding
m1·n1·i1
Magnetic field (H)
Hmax=
h
Length (x)
a) b)
Fig 4.8. Schematics for the leakage inductance calculation. a) Magnetic field
distribution and leakage flux representation. b) Representation of the mean turn length
of the windings.
The value of the MTL can be easily calculated from Fig 4.8 as follows:
MTL = 2 ⋅ (a + z ) + π ⋅ l − d f 2 + d f 1 ( ) (4.29)
Furthermore, the energy stored by the leakage inductance can also be expressed as
follows:
1
Wσ = ⋅ Lσ ⋅ i1 2 (4.30)
2
186
3.3. Power losses estimation
Thus, introducing Eq. (4.28) into Eq. (4.30), the leakage inductance of the transformer
referenced on the primary is approached by:
µ 0 ⋅ n1 2 ⋅ MTL  m1 ⋅ d c1 m2 ⋅ d c2 
Lσ = ⋅  + d ins1 +  (4.31)
h  3 3 
As it can be observed, the value of the leakage inductance highly depends on the number
of turns, the number of layers in the windings and the insulation distance. Nonetheless,
the value of the leakage inductance can be reduced by increasing the height of the core
window.
It must be highlighted that if the primary and secondary windings are interleaved, the
maximum magnetic field in the window is reduced, thereby considerably reducing the
value of the leakage inductance [33], Eq. (4.32). However, this increases the difficulty of
the transformer construction and makes more complex the estimation of the winding
power losses.
2
 n  µ ⋅ MTL  m1 ⋅ d c1 m ⋅d 
Lσ ,int =  1  ⋅ 0 ⋅  + p ⋅ d ins1 + 2 c 2  (4.32)
 p h  3 3 
where p represents the number of times that the windings are interleaved.
3.3 Power losses estimation
The power losses of a transformer are divided into core power losses and winding power
losses.
3.3.1 Core power losses
Generally, core power losses are calculated using the Steinmetz equation, which gives the
volumetric power losses for a given material (w/dm3). This equation, Eq. (4.33), is an
improved version of the empirical equation proposed in 1892 by C.P. Steinmetz.
Pv = K ⋅ f α ⋅ B max β (4.33)
where K and α represents the dependency of the losses in a given material, Bmax is the
peak flux density value and β is the maximum flux density. Generally, K, α and β
parameters are known as the Steinmetz parameters.
Although this expression provides good results for sinusoidal excitations, it is not valid
for the typical non-sinusoidal waveforms in DC-DC converters [34]. In order to address
this issue, different empirical expression have been introduced so far [33]. Among them,
the improved generalized Steinmetz equation (IGSE) introduced in [41] is generally
accepted as the estimation method that most accurate results provides [34] and the
method that better copes with a variety of excitation waveforms [42]. Furthermore, IGSE
187
results in Steinmetz equation for sinusoidal excitation waveforms [33, 43]. The IGSE is
expressed as follows:
dB(t )
α
1 T
Pv = ⋅ ∫ k i ⋅ ⋅ (∆B )β −α dt (4.34)
T 0 dt
K
ki = 2⋅π
(2 ⋅ π )α −1 ∫ cos θ
α
⋅ 2 β −α dθ
(4.35)
0
where K, α and β are the Steinmetz parameters, ΔB is the peak to peak flux density value
and θ is the phase angle of the sinusoidal waveform.
As discussed in Eq. (4.12), the magnetic induction is proportional to the voltage applied
to the transformer. DC-DC converters apply square wave voltages in the MFTs (see
Chapter 3) and in consequence, the magnetic inductions in the MFTs required by
different DC-DC converters can be depicted as in Fig 4.9.
Magnetic induction (B)

Magnetic induction (B)
Voltage applied to
Voltage applied to
Vpri Vpri
the MFT (V)
the MFT (V)
Bmax Bmax
-Bmax
-Vpri -Vpri
0 Ton T/2 0 Ton T

Time (t) Time (t)
a) b)
Fig 4.9. Typical voltage and magnetic induction waveforms in a) bidirectionally
magnetized MFTs and b) unidirectionally magnetized MFTs.
From these waveforms, piecewise linear (PWL) models of the magnetic induction can be
calculated [42]. Thus, in order to provide an easy to use equation, the expression in Eq.
(4.34) can be simplified. For bidirectionally magnetized transformers (cf. Fig 4.9a), the
PWL model of the magnetic induction is given by:
 2 ⋅ t − Ton
 0 < t < Ton
 Ton
 1 Ton < t <
T
 2
B(t ) = B max ⋅ T + T − 2 ⋅ t (4.36)
T T 
 on < t <  + Ton 
 Ton 2 2 
 T 
 −1  + Ton  < t < T
 2 
where T is the period of the square wave voltage applied to the MFT, Ton is the time
interval at which the DC bus voltage (Vin) is applied to the primary winding and Bmax is
the maximum magnetic induction in the core given by Eq. (4.37).
188
Vin ⋅ Ton
B max = (4.37)
2 ⋅ n1 ⋅ Acore
where Acore is the cross sectional area of the core and n1 represents the number of turns of
the primary winding.
Introducing the PWL model of Eq. (4.36) into Eq. (4.34), a straightforward expression for
the calculation of the core power losses in bidirectionally magnetized transformers is
obtained:
Pv = 2 β +1 ⋅ k i ⋅ f α ⋅ B max β ⋅ δ 1−α (4.38)
where δ is the duty cycle of the converter (Ton/T).

Furthermore, according to [41], the calculation of ki can be simplified as follows when
PWL models are used:
K
ki =
 1.7061  (4.39)
2 β +1 ⋅ π α −1 ⋅  0.2761 + 
 α + 1.354 
On the other hand, for unidirectionally magnetized transformers (cf. Fig 4.9b), the PWL
model of the magnetic induction is given by:
 t
 T 0 < t < Ton
B(t ) = B max ⋅  on (4.40)
T −t
 Ton < t < T
 T − Ton
Introducing this PWL model into Eq. (4.34), core power losses in unidirectionally
magnetized transformers are provided by:
(
Pv = k i ⋅ f α ⋅ Bmax β ⋅ δ 1−α + (1 − δ )1−α ) (4.41)
where δ is the duty cycle of the converter (Ton/T).
All in all, the total power losses in the core are obtained by means of:
Pcore = Pv ⋅ Vcore (4.42)

where Vcore is the total core volume.
3.3.2 Winding power losses
The power losses in a conductor where a DC current is flowing can be expressed as:
PDC = I 2 ⋅ R DC (4.43)
where RDC is the DC resistance of the conductor and I is the value of the current through
the conductor.
189
Analogously, it can be said that the power losses in a conductor with a purely sinusoidal
AC current flowing through it are given by:
2
 I 
PAC =   ⋅R
 (4.44)
 2
where I is the maximum amplitude of the current and R is the resistance of the conductor.
In medium frequency applications, the skin and proximity effects are considerable (see
section 4.2.2). Thus, these effects must be taken into account when calculating the
resistance of the conductors. The expression modelling the resistance of the foil
conductors in transformer windings was introduced by P.L Dowell in [44]:
R = R DC ⋅ Fr (4.45)
where Fr is a resistance factor (known as Dowell's resistance factor) given by:
 2
3
( 
Fr = ∆ ⋅  S + ⋅ m 2 − 1 ⋅ P  ) (4.46)
 
sinh (2 ⋅ ∆ ) + sin (2 ⋅ ∆ )
S= (4.47)
cosh (2 ⋅ ∆ ) − cos(2 ⋅ ∆ )
sinh (∆ ) − sin (∆ )
P= (4.48)
cosh (∆ ) + cos(∆ )
d cable η w ⋅π
∆= ⋅ (4.49)
δ 2
where S and P are the expressions that gives the skin and proximity effects respectively,
m is the number of layers of the winding, dcable is the diameter of the conductor, δ is the
skin depth (see Eq. (4.15)) and ηw is the porosity factor, which relates the round or
rectangular conductors with their equivalent whole window foil conductors.
For the round Litz-cables considered in this book, Dowell's resistance factor can be
rewritten as follows [33]:
γ 4  1 pf ⋅ n s ⋅ π 2  24 
Fr = 1 + ⋅ + ⋅ 16 ⋅ m 2 − 1 + 2  (4.50)
192  6 4  π 
d strand
γ= (4.51)
δ⋅ 2
where dstrand is the diameter of each Litz strand, ns represents the number of strands (see
Eq. (4.17)) and pf is the packing factor of the Litz-cable (see Eq. (4.22)). As it can be
noticed, an increase in the strand diameter as well as in the number of layers leads to
higher resistance factors and in consequence, to higher power losses.
On the other hand, the DC resistance of each winding can be estimated by means of:
4 ⋅ n x ⋅ MTL x
R DC = (4.52)
n s ⋅ σ ⋅ π ⋅ d strand 2
190
where σ is the conductivity of the material, nx represents the number of turns of each
winding and MTLx is the mean turn length of each winding. For the shell-type
transformer's geometry (cf. Fig 4.2b), the MTLs of the primary and the secondary
windings are expressed respectively as:
(
MTL1 = 2 ⋅ (a + z ) + π ⋅ m1 ⋅ d c1 + 2 ⋅ d f 1 ) (4.53)
m ⋅d 
MTL2 = 2 ⋅ (a + z ) + 2 ⋅ π ⋅  2 c 2 + m1 ⋅ d c1 + d f 1 + d ins1  (4.54)
 2 
The current through the MFTs in the DC-DC converters is generally a non-sinusoidal
current. Hence, the current circulating through the windings is composed of several
harmonics. As Dowell's resistance factor varies for each current harmonic (the skin depth
varies depending on the frequency), the expression of the power losses in Eq. (4.44) must
be rewritten in order to take into account the losses due to each current harmonic. Thus,
power losses in each winding can be expressed as:
2
 I 
Pw = ∑  i  ⋅ R DC ⋅ Fr i (4.55)
i  2
where Ii is the amplitude of each current harmonic and Fri is the resistance factor of each
current harmonic.
3.3.3 Thermal behaviour
Core and winding power losses discussed in previous sections generate heat, which leads
to an increase of the transformer temperature. In order to keep this temperature within
allowable levels, the thermal behaviour of the transformer must be modelled. In [34, 38,
45-47] detailed thermal models are discussed. Whereas in [48], a more simple method is
proposed.
Assuming that the transformer is naturally cooled and avoiding the use of heat sinks,
complicated nodal models can be avoided (these models usually require detailed heat sink
specifications) and in consequence, the approach proposed in [48] is suitable for
estimating the thermal performance of the transformer. Considering the thermal energy is
dissipated uniformly through the surface area of the transformer, the temperature raise of
the transformer is expressed as:
0.833
 P + Pw1 + Pw2 
∆T =  core  (4.56)
 10 ⋅ S T 
where ST is the total surface area of the transformer, Pw1 and Pw2 are respectively the
power losses in the primary and the secondary windings and Pcore are the core power
losses.
191
3.4 Optimization procedure
The optimized design of a MFT is given by the definition of its best dimensions.
However, the transformer designs for certain specifications can be infinite. Therefore,
optimization procedures must be used in order to find an optimum MFT design. The
flowchart of the design optimization procedure presented in this book is shown by Fig
4.10.
Operational specifications Properties of the selected materials

ipri(t), Vpri(t), Vse, f, N, Lme, Lσe Bsat , Steinmetz parameters , Eins , Litz strand
diameter
Definition of the core geometry
Inductances calculation
Power losses estimation Optimization

process
Thermal calculation
Optimization
Optimized MFT design
Fig 4.10. Flowchart of the design optimization procedure.
As it can be observed, the procedure has few steps. First, insulator material as well as
core and windings materials must be selected and their properties must be introduced in
the optimization program. Furthermore, operational specifications must be defined. These
specifications, imposed by the application and the converter topology, can be listed as
follows: the voltages to be isolated in the primary and the secondary windings, the
required transformer turn ratio, the operational frequency, the voltage and current
waveforms in the conductors and the expected leakage and magnetizing inductances.
Then, the geometry of the core is defined and the values of the inductances derived from
that geometry are calculated (as discussed in section 4.2).
Next, the power losses are estimated and the temperature raise due to these losses is
calculated (as discussed in section 4.3).
Finally, the optimal designs are found by means of an iterative process based on the multi
objective genetic algorithm provided by MATLAB simulation platform. The use of a
genetic algorithm requires to define objectives, optimization variables and constraints. As
the desired MFT design is that which fulfils high efficiency and low volume
requirements, the cost functions or objectives to optimize by the genetic algorithm are the
total power losses of the transformer (Ploss) and the total volume of it (Vtot):
192
3.4. Optimization procedure
min f 1 (x ) = min Ploss (x )

 x x
 (4.57)
min f (x ) = min V (x )
 x 2 x
tot
To achieve this objectives, optimization variables must be defined. Through the different
values given to these variables, different optimal designs will be provided. In this
optimization procedure, the optimization variables are the following ones:
• The depth of the core (z).

• The number of turns in the primary winding (n1).
• The number of layers in the primary winding (m1).
• The number of layers in the secondary winding (m2).
• The current density in the windings (J).
• The margin of the maximum magnetic induction in the core (ξ).
• In the cases where small magnetizing inductance values are demanded, an air gap
is required in the core. In consequence, the length of the air gap (lgap) is treated as
an optimization variable.
Furthermore, so as to penalize the undesired designs, the design constraints have to be
defined. Two constraints have been defined in this design procedure. On the one hand, the
integration of the magnetic elements within the transformer provides higher power
density to the DC-DC converters. Thus, the error between the desired inductances and the
inductances derived from the design is treated as a constraint. In switch mode DC-DC
converters a high magnetizing inductance is required whereas in resonant mode DC-DC
converters an specific magnetizing inductance value is required. Thus, the constraint for
the latter is given by Eq. (4.59) while the constraint of the switch mode converters is
given by Eq. (4.60). The leakage inductance is treated equally for both type of DC-DC
converters, Eq. (4.58).
0.95 ⋅ Lσd < Lσ < 1.05 ⋅ Lσd (4.58)
0.95 ⋅ L md < L m < 1.05 ⋅ L md (4.59)
0.95 ⋅ L md < L m (4.60)
where Lσd and Lmd are respectively the desired leakage and magnetizing inductance
values.
On the other hand, the temperature of the transformer must be kept within allowable
levels, which makes the maximum surface temperature of the transformer the second
design constraint. Following the results of [33], the maximum surface temperature could
be limited to 100ºC as a first approach.
The genetic algorithm will output a curve containing the best solutions with minimum
power losses and volume. This curve is known as the Pareto front, from which, the
designer can select the design that better suits with the requirements of the application
with the security of knowing that all the results are optimal.
193
3.5 Summary
Medium frequency transformers provide galvanic isolation and adapt the voltage levels
between the input and the output of DC-DC converters. The design of these medium
frequency transformers is challenging due to the frequency at which they operate and the
non-sinusoidal current and voltage waveforms applied to them. At high frequencies, the
skin and proximity effects in the windings are considerable. Those effects, increase the
winding power losses thereby reducing the efficiency of the transformer. In turn, the non-
sinusoidal voltages that excite these transformers require the use of more complex core
power losses estimation methods than that used for the transformers excited with
sinusoidal voltages. Furthermore, the current harmonics of the non-sinusoidal waveforms
increase the power losses in the windings.
In order to achieve high power densities, the volume of the transformer must be reduced.
To do so, appropriate core materials with high magnetic induction saturation levels must
be selected (e.g. nanocrystalline), which reduce the core volume and in consequence, the
volume of the transformer. The selection of insulator materials with high dielectric
strength also reduces the total volume of the transformer. Moreover, selecting appropriate
conductor material as Litz-cables, skin and proximity effects are minimized, thereby
diminishing the power losses in the windings and increasing the efficiency of the
transformer.
In this chapter, the design of the medium frequency transformers required by the isolated
DC-DC converters has been discussed. Among coaxial-type, core-type and shell-type
transformers, the latter results the more attractive for the MFTs for high voltage
applications. Thus, detailed design equations for naturally cooled shell-type transformers
are presented. Furthermore, the calculation of the leakage and magnetizing inductances of
the transformer is discussed. It is deduced that an increase in the number of turns, number
of layers in the windings and insulation distance leads to high leakage inductances,
whereas an increase of the core window height reduces the leakage inductance value. In
turn, adding an air gap, the value of the magnetizing inductance is reduced. Moreover, the
power losses in the windings increase with a high number of layers. Straightforward and
easy to implement piecewise linear models for the estimation of the core power losses in
unidirectionally and bidirectionally magnetized transformers have been presented
together with a design optimization procedure. This optimization procedure outputs a
Pareto front that determines which are the optimum transformer designs for certain
operational specifications.
194
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198
Appendix A
Validation of switch
mode DC-DC converter
models
The simulations for validating the models of switch mode DC-DC converters have been
carried out through Synopsys/SABER. A constant input DC bus voltage has been
considered. Since a resistive load has been assumed, in the converters with an output LC
filter, some deviations in the capacitor rms currents can be observed. Furthermore, the
simulations have been carried out without any output voltage control strategy. Hence,
there are small differences between the estimated and simulated stored energy values.
Additionally, the lack of an average voltage control applied to the MFT leads to
deviations in the stored energy and rms currents in the magnetizing inductance.
The converters have been designed with the voltages, rated power and switching
frequency summarized in Table B.1.
TABLE B.1
VALIDATION SCENARIO
Design characteristics
Pin 555.555 kW
Vin 1833 V
Vout 2780 V
fsw 1 kHz
I
Appendix A
B.1 Boost
TABLE B.2
PASSIVE ELEMENTS
Boost converter
Cin 20.668 μF
L1 20.601 mH
Cout 244.874 μF
TABLE B.3
Cin L1 Cout
Maximum stored energy 34.72 J 1.049 kJ 1.040 kJ
Simulation rms current 8.82 A 304.1 A 144.4 A
Maximum voltage stress 1833 V 1830 V 2915 V
Maximum stored energy 34.72 J 1.043 kJ 1.043 kJ

Analytical
rms current 8.74 A 303.2 A 143.6 A
estimation
Maximum stored energy 0 0.57 0.28

Estimation error [%] rms current 0.91 0.29 0.55
Maximum voltage stress 0 0.16 0.13
II
References
TABLE B.4
Analytical Estimation Analytical Estimation

Simulation Simulation
estimation error [%] estimation error [%]
Average
103.2 A 104 A 0.76 199.8 A 199.9 A 0.05
current (Iave)
rms current
176.9 A 177.8 A 0.50 246.2 A 246.7 A 0.20
(Irms)
Maximum
318.2 A 319.1 A 0.28 318.2 A 319.1 A 0.28
current (imax)
Turn-on
switched 287.9 A 288.1 A 0.06 - - -
current (ion)
Turn-off
switched 318.2 A 319.1A 0.28 287.9 A 288.2 A 0.10
current (ioff)
Maximum
2919 V 2918 V 0.03 2919 V 2912 V 0.24
voltage (vmax)
Turn-on
switched 2919 V 2918 V 0.03 - - -
voltage (von)
Turn-off
switched 2641 V 2635 V 0.22 2919 V 2912 V 0.24
voltage (voff)
B.2 Zeta
TABLE B.5
PASSIVE ELEMENTS
Zeta converter
Cin 657.024 μF
L1 36.446 mH
L2 55.276 mH
C1 433.21 μF
Cout 6.98 μF
III
Appendix A
TABLE B.6
Cin L1 C1 L2 Cout
Maximum stored energy 1.103 kJ 1.841 kJ 1.833 kJ 1.209 kJ 28.9 J
Simulation rms current 246.5 A 302.9 A 245.9 A 199.3 A 3.1 A
Maximum voltage stress 1833 V 2912 V 2909 V 2881 V 2878 V
Maximum stored energy 1.103 kJ 1.845 kJ 1.845 kJ 1.216 kJ 38.28 J

Analytical
rms current 246.3 A 303.2 A 246.1 A 199.9 A 5.76 A
estimation
Maximum stored energy 0 0.21 0.65 0.57 24.50
Estimation error [%] rms current 0.08 0.09 0.08 0.30 46.18
Maximum voltage stress 0 0.23 0.34 1.30 1.40
TABLE B.7

Average
303 A 300.5 A 0.83 199.8 A 201.6 A 0.89
current (Iave)
rms current
390.5 A 388.6 A 0.48 317.1 A 318.2 A 0.34
(Irms)
Maximum
528 A 527 A 0.18 528 A 527 A 0.18
current (imax)
Turn-on
switched 477.7 A 476.6 A 0.23 - - -
current (ion)
Turn-off
switched 528 A 527 A 0.18 477.7 A 476.6 A 0.23
current (ioff)
Maximum
4752 V 4745 V 0.14 4752 V 4738 V 0.29
voltage (vmax)
Turn-on
switched 4752 V 4745 V 0.14 - - -
voltage (von)
Turn-off
switched 4474 V 4465 V 0.20 4752 V 4738 V 0.29
voltage (voff)
IV
References
B.3 Sepic
TABLE B.8
PASSIVE ELEMENTS
Sepic converter
Cin 20.668 μF
L1 36.446 mH
L2 55.276 mH
C1 657.024 μF
Cout 433.21 μF
TABLE B.9
Cin L1 C1 L2 Cout
Maximum stored energy 34.72 J 1.923 kJ 1.328 kJ 1.174 kJ 1.828 kJ
Simulation rms current 8.93 A 307.9 A 245.3 A 193 A 245.2 A

Analytical
estimation
V
Appendix A
TABLE B.10

Average
303 A 301.8 A 0.40 199.8 A 198.9 A 0.45
current (Iave)
rms current
390.5 A 388.8 A 0.44 317.1 A 315.8 A 0.41
(Irms)
Maximum
528 A 526.2 A 0.34 528 A 526.1 A 0.36
current (imax)
Turn-on
switched 477.7 A 475.4 A 0.48 - - -
current (ion)
Turn-off
switched 528 A 526.2 A 0.34 477.7 A 475.8 A 0.40
current (ioff)
Maximum
4843 V 4919 V 1.55 4843 V 4912 V 1.40
voltage (vmax)
Turn-on
switched 4843 V 4919 V 1.55 - - -
voltage (von)
Turn-off
switched 4382 V 4370 V 0.27 4843 V 4912 V 1.40
voltage (voff)
B.4 Isolated-sepic
TABLE B.11
PASSIVE ELEMENTS
Isolated-sepic converter
Cin 20.668 μF
L1 30.239 mH
Lm 30.239 mH
C1 826.746 μF
Cout 359.424 μF
n2 / n1 1.5166
VI
References
TABLE B.12
Cin L1 C1 Lm Cout
Simulation rms current 11.48 A 303 A 303.1 A 302.8 A 199.7 A

Analytical
rms current 8.74 A 303.2 A 303 A 303.2 A 199.8 A
estimation
TABLE B.13

Average
303 A 303.1 A 0.03 199.8 A 199.3 A 0.25
current (Iave)
rms current
428.8 A 428.5 A 0.07 282.7 A 282.3 A 0.14
(Irms)
Maximum
636.4 A 636.3 A 0.02 419.6 A 419.5 A 0.02
current (imax)
Turn-on
switched 575.8 A 574.3 A 0.26 - - -
current (ion)
Turn-off
switched 636.4 A 636.3 A 0.02 369.3 A 378.7 A 2.48
current (ioff)
Maximum
3849 V 3938 V 2.26 5838 V 5963 V 2.10
voltage (vmax)
Turn-on
switched 3849 V 3938 V 2.26 - - -
voltage (von)
Turn-off
switched 3482 V 3535 V 1.50 5838 V 5963 V 2.10
voltage (voff)
VII
Appendix A
B.5 Ćuk
TABLE B.14
PASSIVE ELEMENTS
Ćuk converter
Cin 20.668 μF
L1 36.446 mH
L2 55.276 mH
C1 261.072 μF
Cout 8.985 μF
TABLE B.15
Cin L1 C1 L2 Cout
Maximum stored energy 34.72 J 1.841 kJ 3.050 kJ 1.209 kJ 36.98 J
Simulation rms current 8.73 A 303 A 246 A 199.3 A 3.68 A
Maximum stored energy 34.72 J 1.845 kJ 3.062 kJ 1.216 kJ 38.28 J

Analytical
estimation
VIII
References
TABLE B.16

Average
303 A 302.8 A 0.07 199.8 A 199.3 A 0.25
current (Iave)
rms current
390.5 A 390.1 A 0.10 317.1 A 316.4 A 0.22
(Irms)
Maximum
528 A 526.9 A 0.21 528 A 526.9 A 0.21
current (imax)
Turn-on
switched 477.7 A 476.9 A 0.17 - - -
current (ion)
Turn-off
switched 528 A 526.9 A 0.21 477.7 A 476.6 A 0.23
current (ioff)
Maximum
4843 V 4837 V 0.12 4843 V 4829 V 0.29
voltage (vmax)
Turn-on
switched 4843 V 4837 V 0.12 - - -
voltage (von)
Turn-off
switched 4382 V 4374 V 0.18 4843 V 4829 V 0.29
voltage (voff)
B.6 Isolated-ćuk
TABLE B.17
PASSIVE ELEMENTS
Isolated-ćuk converter
Cin 20.668 μF
L1 30.239 mH
Lm 30.239 mH
C1 826.746 μF
L2 69.555 mH
C2 359.424 μF
Cout 8.985 μF
n2 / n1 1.5166
IX
Appendix A
TABLE B.18
Cin L1 C1 Lm C2 L2 Cout
Maximum
34.72 J 1.540 kJ 1.627 kJ 13.35 J 1.625 kJ 1.529 kJ 37.06 J
stored energy
Simulation rms current 8.74 A 304.3 A 303.9 A 13.6 A 200.3 A 199.8 A 3.64 A
Maximum
1833 V 2016 V 1984 V 1979 V 3007 V 2875 V 2872 V
voltage stress
Maximum
34.72 J 1.531 kJ 1.531 kJ 3.47 J 1.531 kJ 1.531 kJ 38.28 J
stored energy
Analytical
rms current 8.74 A 303.2 A 303 A 8.74 A 199.8 A 199.9 A 5.76 A
estimation
Maximum
1833 V 2016 V 1924 V 1924 V 2919 V 2919 V 2919 V
voltage stress
Maximum
0 0.59 6.27 284.73 6.14 0.13 3.19
stored energy
Estimation error [%] rms current 0 0.36 0.30 55.61 0.25 0.05 36.81
Maximum
0 0 3.12 2.86 3.01 1.51 1.61
voltage stress
TABLE B.19

Average
303 A 303.1 A 0.03 199.8 A 201.5 A 0.84
current (Iave)
rms current
429 A 428.7 A 0.07 282.8 A 284 A 0.42
(Irms)
Maximum
651.6 A 666.1 A 2.18 429.6 A 439.2 A 2.19
current (imax)
Turn-on
switched 560.7 A 569.9 A 1.61 - - -
current (ion)
Turn-off
switched 651.6 A 666.1 A 2.18 369.7 A 378.9 A 2.43
current (ioff)
Maximum
3849 V 3849 V 0 5838 V 5828 V 0.17
voltage (vmax)
Turn-on
switched 3849 V 3849 V 0 - - -
voltage (von)
Turn-off
switched 3482 V 3475 V 0.20 5838 V 5828V 0.17
voltage (voff)
X
References
B.7 Flyback
TABLE B.20
PASSIVE ELEMENTS
Flyback converter
Cin 826.746 μF
Lm 15.119 mH
Cout 359.424 μF
n2 / n1 1.5166
TABLE B.21
Cin Lm Cout
Maximum stored energy 1.388 kJ 3.055 kJ 1.522 kJ
Simulation rms current 302.9 A 605.9 A 199.8 A
Maximum stored energy 1.388 kJ 3.062 kJ 1.531 kJ

Analytical
rms current 303.3 A 606.4 A 199.8 A
estimation
Estimation error [%] rms current 0.13 0.08 0
XI
Appendix A
TABLE B.22

Average
303 A 303.2 A 0.07 199.8 A 199.4 A 0.20
current (Iave)
rms current
428.8 A 428.6 A 0.05 282.7 A 282.3 A 0.14
(Irms)
Maximum
636.4 A 635.7 A 0.11 419.6 A 419.1 A 0.12
current (imax)
Turn-on
switched 575.8 A 575.1 A 0.12 - - -
current (ion)
Turn-off
switched 636.4 A 635.7 A 0.11 379.6 A 379.1 A 0.13
current (ioff)
Maximum
3757 V 3754 V 0.08 5699 V 5683 V 0.28
voltage (vmax)
Turn-on
switched 3757 V 3754 V 0.08 - - -
voltage (von)
Turn-off
switched 3574 V 3570 V 0.11 5699 V 5683 V 0.28
voltage (voff)
B.8 Forward
TABLE B.23
PASSIVE ELEMENTS
Forward converter
Cin 1.023 mF
Lm 11.895 mH
L1 77.415 mH
Cout 8.985 μF
n2 / n1 1.2547
n3 / n1 3.4197
XII
References
TABLE B.24
Cin Lm L1 Cout
Maximum stored energy 1.878 kJ 27.52 J 1.688 kJ 36.65 J
Simulation rms current 369.2 A 39.20 A 198.8 A 3.64 A
Maximum voltage stress 1833 V 1828 V 3579 V 2856 V

Analytical
rms current 374.69 A 39.45 A 199.9 A 5.76 A
estimation
Maximum stored energy 0 0.90 8.26 4.26
Estimation error [%] rms current 1.47 0.63 0.55 36.81
Maximum voltage stress 0 0.27 2.61 2.16
TABLE B.25

Average
318.2 A 316.2 A 0.63 15.15 A 14.99 A 1.07
current (Iave)
rms current
478.5 A 475.9 A 0.55 23.45 A 23.27 A 0.77
(Irms)
Maximum
785.9 A 782.3 A 0.46 54.46 A 54.16 A 0.55
current (imax)
Turn-on
switched 649.2 A 645.3 A 0.60 - - -
current (ion)
Turn-off
switched 785.9 A 782.3 A 0.46 0A 0A 0
current (ioff)
Maximum
3293 V 3295 V 0.06 4133 V 4126 V 0.17
voltage (vmax)
Turn-on
switched 3293 V 3294 V 0.03 - - -
voltage (von)
Turn-off
switched 3293 V 3293 V 0 4133 V 4126 V 0.17
voltage (voff)
XIII
Appendix A
TABLE B.26
Diode D2 Diode D3

Average
88.62 A 88.07 A 0.62 111.2 A 110.7 A 0.45
current (Iave)
rms current
133.1 A 132.4 A 0.53 149.1 A 148.3 A 0.54
(Irms)
Maximum
209.8 A 208.9 A 0.43 209.8 A 208.9 A 0.43
current (imax)
Turn-off
switched 209.8 A 208.9 A 0.43 189.8 A 188.7 A 0.58
current (ioff)
Maximum
4995 V 4997 V 0.04 6268 V 6249 V 0.30
voltage (vmax)
Turn-off
switched 4995 V 4997 V 0.04 6268 V 6249 V 0.30
voltage (voff)
B.9 Two-transistor forward
TABLE B.27
PASSIVE ELEMENTS
Two-transistor forward converter
Cin 925.956 μF
Lm 14.520 mH
L1 70.946 mH
Cout 8.985 μF
n2 / n1 3.0951
XIV
References
TABLE B.28
Cin Lm L1 Cout

Analytical
rms current 340.6 A 35.35 A 199.9 A 5.76 A
estimation
TABLE B.29
Transistor S1-S2 Diode D1-D2

Average
318.2 A 317.4 A 0.25 15.15 A 15 A 1
current (Iave)
rms current
455.3 A 453.8 A 0.33 24.99 A 24.82 A 0.68
(Irms)
Maximum
711.3 A 708.4 A 0.41 61.85 A 61.55 A 0.49
current (imax)
Turn-on
switched 587.6 A 584.5 A 0.53 - - -
current (ion)
Turn-off
switched 711.3 A 708.4 A 0.41 0A 0A 0
current (ioff)
Maximum
1833 V 1833 V 0 1833 V 1833 V 0
voltage (vmax)
Turn-on
switched 916 V 916 V 0 - - -
voltage (von)
Turn-off
switched 1833 V 1833 V 0 916 V 916 V 0
voltage (voff)
XV
Appendix A
TABLE B.30
Diode D3 Diode D4

Average
97.92 A 97.68 A 0.25 101.9 A 101.2 A 0.69
current (Iave)
rms current
139.9 A 139.49 A 0.29 142.7 A 141.9 A 0.56
(Irms)
Maximum
209.8 A 208.9 A 0.43 209.8 A 208.9 A 0.43
current (imax)
Turn-off
switched 209.8 A 208.9 A 0.43 189.8 A 188.9 A 0.48
current (ioff)
Maximum
5673 V 5679 V 0.11 5673 V 5643 V 0.53
voltage (vmax)
Turn-off
switched 5673 V 5679 V 0.11 5673 V 5643 V 0.53
voltage (voff)
B.10 Push-pull
TABLE B.31
PASSIVE ELEMENTS
Push-pull converter
Cin 82.674 μF
Lm 24.493 mH
L1 6.955 mH
Cout 4.492 μF
n2 / n1 1
n3 / n1 1.6851
XVI
References
TABLE B.32
Cin Lm L1 Cout
Maximum stored energy 138.8 J 3.82 J 151.66 J 18.59 A
Maximum stored energy 138.8 J 3.47 J 153.12 J 19.14 J

Analytical
rms current 102.62 A 10.64 A 199.9 A 5.76 A
estimation
TABLE B.33
Transistors S1-S2 Diodes D1-D2-D3-D4

Average
151.5 A 152 A 0.33 99.9 A 99.7 A 0.20
current (Iave)
rms current
226.2 A 226.8 A 0.26 137.7 A 137.6 A 0.07
(Irms)
Maximum
370.4 A 369.5 A 0.24 209.8 A 208.8 A 0.48
current (imax)
Turn-on
switched 303 A 302.3 A 0.23 - - -
current (ion)
Turn-off
switched 370.4 A 369.5 A 0.24 94.92 A 89.1 A 6.53
current (ioff)
Maximum
3666 V 3663 V 0.08 3088 V 3082 V 0.19
voltage (vmax)
Turn-on
switched 1833 V 1833 V 0 - - -
voltage (von)
Turn-off
switched 1833 V 1833 V 0 3088 V 3082 V 0.19
voltage (voff)
XVII
Appendix A
B.11 Push-pull isolated-boost
TABLE B.34
PASSIVE ELEMENTS
Push-pull isolated-boost converter
Cin 10.334 μF
Lm 37.798 mH
L1 6.047 mH
Cout 71.884 μF
n2 / n1 1
n3 / n1 1.2133
TABLE B.35
Cin Lm L1 Cout
Maximum stored energy 17.36 J 2.84 J 304 J 300.1 J
Maximum voltage stress 1833 V 2385 A 1832 V 2890 V

Analytical
rms current 8.74 A 8.28 A 303.2 A 99.9 A
estimation
XVIII
References
TABLE B.36

Average
151.5 A 151.3 A 0.13 99.9 A 99.6 A 0.30
current (Iave)
rms current
203.4 A 203.1 A 0.15 158.2 A 158 A 0.13
(Irms)
Maximum
318.2 A 317 A 0.38 272.2 A 271.1 A 0.41
current (imax)
Turn-on
switched 137.9 A 137.1 A 0.58 - - -
current (ion)
Turn-off
switched 165.1 A 164.5 A 0.36 227.3 A 226.1 A 0.53
current (ioff)
Maximum
4811 V 4770 V 0.86 2919 V 2890 V 1
voltage (vmax)
Turn-on
switched 4811 V 4770 V 0.86 - - -
voltage (von)
Turn-off
switched 4353 V 4311 V 0.97 1459 V 1435 V 1.67
voltage (voff)
B.12 Half-bridge
TABLE B.37
PASSIVE ELEMENTS
Half-bridge converter
Cin1 1.818 mF
Cin2 1.818 mF
Lm 6.123 mH
L1 6.955 mH
Cout 4.492 μF
n2 / n1 3.3703
XIX
Appendix A
TABLE B.38
Cin1 Lm L1 Cout
Simulation rms current 331.7 A 24.17 A 199.1 J 4.27 A

Analytical
rms current 336 A 21.29 A 199.9 A 5.76 A
estimation
Maximum voltage stress 0 0 0.99 1.10
TABLE B.39

Average
303 A 299.4 A 1.20 99.9 A 99.3 A 0.60
current (Iave)
rms current
452.5 A 446.9 A 1.25 137.7 A 137.1 A 0.44
(Irms)
Maximum
740.8 A 745 A 0.56 209.8 A 208.9 A 0.43
current (imax)
Turn-on
switched 606.1 A 614.1 A 1.30 - - -
current (ion)
Turn-off
switched 740.8 A 745 A 0.56 94.9 A 91 A 4.29
current (ioff)
Maximum
1833 V 1835 V 0.11 3088 V 3145 V 1.81
voltage (vmax)
Turn-on
switched 916 V 917 V 0.11 - - -
voltage (von)
Turn-off
switched 916 V 917 V 0.11 3088 V 3145 V 1.81
voltage (voff)
XX
References
B.13 Half-bridge isolated-boost
TABLE B.40
PASSIVE ELEMENTS
Half-bridge isolated-boost converter
Cin 0.9394 μF
Lm 134.395 mH
L1 66.525 mH
L2 66.525 mH
Cout 35.942 μF
n2 / n1 0.6824
TABLE B.41
Cin Lm L1 Cout

Analytical
rms current 0.79 A 4.31 A 151.6 A 64.9 A
estimation
XXI
Appendix A
TABLE B.42

Average
151.5 A 149.9 A 1.07 99.9 A 99.3 A 0.60
current (Iave)
rms current
208.8 A 206.8 A 0.97 149.1 A 148.2 A 0.61
(Irms)
Maximum
304.4 A 301.1 A 1.10 243.1 A 241.1 A 0.83
current (imax)
Turn-on
switched 137.1 A 135.7 A 1.03 - - -
current (ion)
Turn-off
switched 165.9 A 163.9 A 1.22 200.9 A 198.9 A 1.01
current (ioff)
Maximum
4277 V 4169 V 2.59 2919 V 2842 V 2.71
voltage (vmax)
Turn-on
switched 4277 V 4169 V 2.59 - - -
voltage (von)
Turn-off
switched 3869 V 3775 V 2.49 1459 V 1417 V 2.96
voltage (voff)
B.14 Full-bridge
TABLE B.43
PASSIVE ELEMENTS
Full-bridge converter
Cin 174.820 μF
Lσ 217.720 μH
L1 13.911 mH
Cout 4.492 μF
n2 / n1 1.8957
XXII
References
TABLE B.44
Cin Lσ L1 Cout

Analytical
rms current 183 A 355.8 A 199.9 A 5.76 A
estimation
TABLE B.45
EXPRESSIONS OF THE VOLTAGES/CURRENTS IN THE TRANSISTORS
Transistors S1-S4 Transistors S2-S3

Average
167.1 A 162.5 A 2.83 159.2 A 159.5 A 0.19
current (Iave)
rms current
246.7 A 245.4 A 0.53 243.5 A 243 A 0.21
(Irms)
Maximum
397.7 A 394.3 A 0.86 397.7 A 394.5 A 0.81
current (imax)
Turn-off
switched 394.2 A 392.6 A 0.41 397.7 A 394.5 A 0.81
current (ioff)
Maximum
1833 V 1836 V 0.16 1833 V 1836 V 0.16
voltage (vmax)
Turn-off
switched 1833 V 1836 V 0.16 1833 V 1836 V 0.16
voltage (voff)
XXIII
Appendix A
TABLE B.46
EXPRESSIONS OF THE VOLTAGES/CURRENTS IN THE FREEWHEEL DIODES
Freewheel diodes DS1-DS4 Freewheel diodes DS2-DS3

Average
9.27 A 9.05 A 2.43 13.2 A 12 A 10
current (Iave)
rms current
49.3 A 48.5 A 1.65 63.8 A 59.3 A 7.59
(Irms)
Maximum
394.2 A 392.6 A 0.41 397.7 A 394.5 A 0.81
current (imax)
Maximum
1833 V 1836 V 0.16 1833 V 1836 V 0.16
voltage (vmax)
TABLE B.47
EXPRESSIONS OF THE VOLTAGES/CURRENTS IN THE DIODES
Diodes D1-D2-D3-D4
Analytical estimation Simulation Estimation error
Average current (Iave) 90.9 A 99.2 A 8.37
rms current (Irms) 131.1 A 136.2 A 3.74
Maximum current (imax) 209.8 A 208 A 0.87
Maximum voltage (vmax) 3474 V 3420 V 1.58
XXIV
References
B.15 Full-bridge isolated-boost
TABLE B.48
PASSIVE ELEMENTS
Full-bridge isolated-boost converter
Cin 10.334 μF
Lm 37.798 mH
L1 6.047 mH
Cout 71.884 μF
n2 / n1 1.2133
TABLE B.49
Cin Lm L1 Cout
Maximum stored energy 17.36 J 2.83 J 303.7 J 299.9 A

Analytical
rms current 8.74 A 8.28 A 303.2 A 99.9 A
estimation
XXV
Appendix A
TABLE B.50
Transistors S1-S2-S3-S4 Diodes D1-D2-D3-D4

Average
151.5 A 151.3 A 0.13 99.9 A 99.6 A 0.30
current (Iave)
rms current
203.4 A 203 A 0.20 158.2 A 157.9 A 0.19
(Irms)
Maximum
318.2 A 316.9 A 0.41 272.2 A 271 A 0.44
current (imax)
Turn-on
switched 137.9 A 137 A 0.66 - - -
current (ion)
Turn-off
switched 165.1 A 164.4 A 0.43 227.3 A 225.5 A 0.80
current (ioff)
Maximum
2405 V 2384 V 0.88 2919 V 2890 V 1.00
voltage (vmax)
Turn-on
switched 2405 V 2384 V 0.88 - - -
voltage (von)
Turn-off
switched 2176 V 2154 V 1.02 1459 V 1441 V 1.25
voltage (voff)
B.16 Single-active-bridge
TABLE B.51
PASSIVE ELEMENTS
Single-active-bridge converter
Cin 334.832 μF
Lσ 217.720 μH
Cout 89.856 μF
n2 / n1 1.8957
XXVI
References
TABLE B.52
Cin Lσ Cout
Maximum stored energy 562.5 J 61.67 J 396.7 J
Simulation rms current 318.5 A 443 A 119.8 A

Analytical
rms current 315.4 A 437.4 A 115.3 A
estimation
TABLE B.53
Transistors S1-S2-S3-S4 Freewheel diodes DS1-DS2-DS3-DS4

Average
170.4 A 171.9 A 0.87 18.9 A 18 A 5
current (Iave)
rms current
293.4 A 298.4 A 1.68 97.8 A 95.1 A 2.84
(Irms)
Maximum
757.7 A 752.6 A 0.68 757.7 A 748.2 A 1.27
current (imax)
Turn-off
switched 757.7 A 752.6 A 0.68 0A 0A 0
current (ioff)
Maximum
1833 V 1837 V 0.22 1833 V 1837 V 0.22
voltage (vmax)
Turn-off
switched 1833 V 1837 V 0.22 0V 0V 0
voltage (voff)
XXVII
Appendix A
TABLE B.54
Diodes D1-D2-D3-D4
Analytical estimation Simulation Estimation error
Average current (Iave) 99.9 A 100.2 A 0.30
rms current (Irms) 163.1 A 165.2 A 1.27
Maximum current (imax) 399.6 A 397 A 0.65
Turn-off switched current (ioff) 0A 0A 0
Maximum voltage (vmax) 2919 V 2973 V 1.82
Turn-off switched voltage (voff) 2919 V 2973 V 1.82
B.17 Dual-active-bridge
TABLE B.55
PASSIVE ELEMENTS
Dual-active-bridge converter
Cin 508.255 μF
Lσ 680.377 μH
Cout 156.203 μF
n2 / n1 1.6851
XXVIII
References
TABLE B.56
Cin Lσ Cout
Simulation rms current 428.2 A 531 A 241.6 A

Analytical
rms current 412.4 A 523.1 A 237.5 A
estimation
TABLE B.57

Average
195.8 A 200.8 A 2.49 44.3 A 43.2 A 2.55
current (Iave)
rms current
341.9 A 349.1 A 2.06 141 A 139.6 A 1.00
(Irms)
Maximum
673.5 A 678.9 A 0.80 673.5 A 674.6 A 0.16
current (imax)
Turn-off
switched 673.5 A 678.9 A 0.80 0A 0A 0
current (ioff)
Maximum
1833 V 1837 V 0.22 1833 V 1837 V 0.22
voltage (vmax)
Turn-off
switched 1833 V 1837 V 0.22 0V 0V 0
voltage (voff)
XXIX
Appendix A
TABLE B.58

Average
21.2 A 21.7 A 2.30 121.2 A 123.1 A 1.54
current (Iave)
rms current
71.4 A 72.5 A 1.52 207.5 A 211 A 1.66
(Irms)
Maximum
359.7 A 361.5 A 0.50 399.6 A 402.9 A 0.82
current (imax)
Turn-off
switched 359.7 A 361.5 A 0.50 0A 0A 0
current (ioff)
Maximum
2944 V 2953 V 0.30 2944 V 2953 V 0.30
voltage (vmax)
Turn-off
switched 2615 V 2615 V 0 0V 0V 0
voltage (voff)
XXX
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Power Electronic Converter Design Handbook

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What is the purpose and scope of the book?

What is the purpose and scope of the book?

What topics are covered in the book related to AC-DC rectifiers?

What topics are covered in the book related to AC-DC rectifiers?

Iin

Manex Barrenetxea Iñarra

MANEX BARRENETXEA IÑARRA - Mondragon Unibertsitatea, Faculty of Engineering

Diseño y maquetación: AZK Taldea

2L-VSC Two-level voltage source converter

1.1 Introduction ....................................................................................................... 13

1.2 Three-phase diode front end .............................................................................. 14

1.2.2 DC bus capacitor design ................................................................................ 16

1.3 Two-level voltage source converter .................................................................. 17

1.3.2 DC bus capacitor design ................................................................................23

1.4 Three-level neutral point clamped converter ..................................................... 23

1.4.2 DC bus capacitor design ................................................................................ 33

1.5 Cascaded H-bridge converter ............................................................................ 36

1.5.2 DC bus capacitor design ................................................................................ 40

1.6 Summary .......................................................................................................... 41

2.1 Introduction ....................................................................................................... 43

2.2 Switch mode DC-DC converters ....................................................................... 44

2.2.2 Zeta ................................................................................................................ 50

2.2.3 Sepic .............................................................................................................. 56

2.2.4 Isolated-sepic ................................................................................................. 62

2.2.5 Ćuk ................................................................................................................ 68

2.2.6 Isolated-ćuk ................................................................................................... 73

2.2.7 Flyback .......................................................................................................... 79

2.2.8 Forward ......................................................................................................... 85

2.2.10 Push-pull ........................................................................................................99

2.2.11 Push-pull isolated-boost...............................................................................105

2.2.12 Half-bridge ..................................................................................................112

2.2.13 Half-bridge isolated-boost ...........................................................................117

2.2.14 Full-bridge ...................................................................................................124

2.2.15 Full-bridge isolated-boost ............................................................................133

2.2.16 Single-active-bridge .....................................................................................140

2.2.17 Dual-active-bridge .......................................................................................146

2.3 Resonant mode DC-DC converters.................................................................. 154

2.3.2 Three-element resonant-tanks ......................................................................159

2.3.2.2 LCC .............................................................................................................161

2.3.2.4 LCL type 1 ...................................................................................................164

2.3.2.5 LCL type 2 ...................................................................................................166

2.3.3 Four-element resonant-tanks .......................................................................167

2.3.3.1 LCLL ...........................................................................................................167

2.3.3.2 LLCL ...........................................................................................................169

2.3.3.3 CLCL ...........................................................................................................171

2.3.4 CLCLL resonant-tank ..................................................................................173

2.4 Summary ....................................................................................................... 175

3 Medium frequency transformer 177

3.1 Introduction...................................................................................................... 177

3.2 Geometry of the transformer............................................................................ 178

3.2.3 Magnetizing and leakage inductances .........................................................184

3.3 Power losses estimation ................................................................................... 187

3.3.2 Winding power losses ................................................................................. 189

3.3.3 Thermal behaviour ...................................................................................... 191

3.4 Optimization procedure ................................................................................... 192

3.5 Summary ....................................................................................................... 194

Appendix A - Validation of switch mode DC-DC converter models ............................ I

The electrical devices used to convert an alternating-current (AC) to a direct-current (DC)

1.2 Three-phase diode front end

Fig 2.1. Three-phase diode front end rectifier.