Vlsi Lab Manual r16

VLSI LAB

III-B.TECH, ECE

II Semester 2019-20

LAB MANUAL
(Student Manual)
Prepared by
M. Madhusudhan Reddy, M.Tech
Assistant Professor
&
N.Soniya, M.Tech
Assistant Professor
KKR & KSR INSTITUTE OF TECHNOLOGY & SCIENCES

(Approved by AICTE, Delhi, Affiliated to JNTU, Kakinada,
Accredited by NAAC with ‘A’ Grade and NBA)
Department of Electronics and Communication Engineering
Contents of Lab Manual
Page
S.NO DESCRIPTION
No.
1. Institute Vision and Mission i
2. Department Vision and Mission i
3. PO’s ii
4. PSO’s, PEO’s iii,iv
5. University Lab Syllabus v
6. CO’s vi
7. CO/ PO/ PSO Mapping & Justification vii
8. Introduction to the curriculum lab 1-47
Details of EXPERIMENTS
11. Design and Implementation of an Universal Gates 48-52
12. Design and Implementation of an Inverter 53-55
13. Design and Implementation of Full Adder 56-61
14. Design and Implementation of Full Subtractor 62-67
15. Design and Implementation of Decoder 68-69
16. Design and Implementation of RS-Latch 70-72
17. Design and Implementation of D-Latch 73-77
18. Design and Implementation asynchronous counter 78-80
19. Design and Implementation of static RAM cell 81-83
Design and Implementation of 8 bit DAC using R-2R latter
20. 84-86
network
(Approved by AICTE, Delhi, Affiliated to JNTU, Kakinada )
Department Of Electronics and Communication Engineering
INSTITUTE VISION /MISSION
Vision:
To become a knowledge center for technical education and also to become the top
Engineering college in the sun rise state of Andhra Pradesh.
Mission:
 To incorporate benchmarked teaching and learning pedagogies in curriculum.
 To ensure all round development of students through judicious blend of curricular,

co curricular and extracurricular activities.
 To support cross-cultural exchange of knowledge between industry and academy.
 To provide higher/continued education and research opportunities to the employees of

the institution.
DEPARTMENT VISION/MISION
Vision of ECE Department
To develop highly qualitative, technically competent and socially responsible engineers.
Mission of ECE Department
To provide quality education in the domain of Electronics and Communication Engineering
through periodically updated curriculum, effective teaching learning processes, best of laboratory
facilities and collaborative ventures with the industries.
FACULTY I/C HOD
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PROGRAM OUTCOMES (PO’S)

1. Engineering knowledge: Apply the knowledge of mathematics, science, engineering
fundamentals, and an engineering specialization to the solution of complex engineering problems.
2. Problem analysis: Identify, formulate, research literature, and analyze complex engineering
problems reaching substantiated conclusions using first principles of mathematics, natural sciences,
and engineering sciences.
3. Design/development of solutions: Design solutions for complex engineering problems and design
system components or processes that meet the specified needs with appropriate consideration for the
public health and safety, and the cultural, societal, and environmental considerations.
4. Conduct investigations of complex problems: Use research-based knowledge and research
methods including design of experiments, analysis and interpretation of data, and synthesis of the
information to provide valid conclusions.
5. Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern
engineering and IT tools including prediction and modeling to complex engineering activities with an
understanding of the limitations.
6. The engineer and society: Apply reasoning informed by the contextual knowledge to assess
societal, health, safety, legal and cultural issues and the consequent responsibilities relevant to the
professional engineering practice.
7. Environment and sustainability: Understand the impact of the professional engineering solutions
in societal and environmental contexts, and demonstrate the knowledge of, and need for sustainable
development.
8. Ethics: Apply ethical principles and commit to professional ethics and responsibilities and norms
of the engineering practice.
9. Individual and team work: Function effectively as an individual, and as a member or leader in
diverse teams, and in multidisciplinary settings.
10. Communication: Communicate effectively on complex engineering activities with the
engineering community and with society at large, such as, being able to comprehend and write
effective reports and design documentation, make effective presentations, and give and receive clear
instructions.
11. Project management and finance: Demonstrate knowledge and understanding of the
engineering and management principles and apply these to one’s own work, as a member and leader
in a team, to manage projects and in multidisciplinary environments.
12. Life-long learning: Recognize the need for, and have the preparation and ability to engage in
independent and life-long learning in the broadest context of technological change.
FACULTY I/C HOD
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PROGRAM SPECIFIC OUTCOMES (PSO’S)

PSO1 : Professional Skills
To understand the basic concepts of Electronics & Communication Engineering and to apply
them to various areas, like Electronics, Communications, VLSI, Embedded systems to arrive cost
effective and appropriate solutions.
PSO2: Problem-solving skills
To be equipped with the principles of Semiconductor Devices, Digital Systems, Microprocessor

and Signal processing for the fields of Consumer Electronics, Medical, Defense and Spacecraft
Electronics industry
PSO3:Successful career
To be successful in professional career by using latest hardware and software tools like
VHDL,MATLAB,MULTISIM,MENTOR GRAPHICS along with analytical skills to work in
core industries
PSO4 :Exposure for research and development:
To analyze latest trends in Electronics and Communication and apply the knowledge for the
improvement in the present technology by doing research through higher education
PSO5 :Development for real time applications
To develop a innovative real world applications in Home, Agriculture and Industrial automation
FACULTY I/C HOD
iii
PROGRAM EDUCATIONAL OUTCOMES (PEO’S)
PEO1: Develop a strong background in basic science and mathematics and ability to use these
tools in their chosen fields of specialization.
PEO2: Have the ability to demonstrate technical competence in the fields of electronics and
communication engineering and develop solutions to the problems.
PEO3: Attain professional competence through life-long learning such as advanced degrees,
professional registration, and other professional activities.
PEO4: Function effectively in a multi-disciplinary environment and individually, within a global,

societal, and environmental context.
PEO5: Take individual responsibility and to work as a part of a team towards the fulfillment of
both individual and organizational goals.
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UNIVERSiTY SYLLABUS
v
COURSE OBJECTIVES
 Basic characteristics of MOS transistor and examines various possibilities for configuring
inverter circuits and aspects of latch-up are considered.
 Design processes are aided by simple concepts such as stick and symbolic diagrams but
the key element is a set of design rules, which are explained clearly.
 Basic circuit concepts are introduced for MOS processes we can set out approximate
circuit parameters which greatly ease the design process.
COURSE OBJECTIVES
COURSE Taxanomy
COURSE |OUTCOMES
CODE Level
Basic characteristics of MOS transistor and examine
C323.1 various possibilities for configuring inverter circuits and L2
aspects of latch-up are considered.
Know three sets of design rules with which nMOS and
C323.2 L3
CMOS designs may be fabricated.
Understand the scaling factors determining the L2
characteristics and performance of nMOS circuits in
C323.3 silicon and Realize logic circuits with different design
styles
Basic knowledge about chip I/O circuits, fault models

C323.4 L3
and testing techniques.
Understand the basic concepts of FPGA design flow,
C323.5 L3
architecture and logic synthesis related to digital circuits.
Demonstrate an understanding of different sources of
C323.6 L3
power dissipation and reduction in CMOS logic circuits.
Faculty I/C H.O.D
vi

MAPPING OF CO’S WITH PO’S
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
C323.1 3.0 2.0
C323.2 2.0 2.0
C323.3 2.0
C323.4 2.0 2.0
C323.5 2.0 2.0
C323.6 2.0
Average 3.0 2.0 2.0 2.0 2.0
MAPPING OF CO’S WITH PSO’S
PSO1 PSO2 PSO3 PSO4

C323.1 1.0 1.0 1.0 2.0
C323.2 2.0 2.0 2.0 1.0
C323.3 2.0
C323.4 2.0
C323.5 3.0 3.0 3.0 3.0
C323.6 2.0 1.0 2.0
Average 2.0 2.0 2.0 2.0
1: LOW 2:MEDUIM 3:HIGH
Faculty I/C H.O.D
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R16
B.Tech VLSI
Laboratory-II
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Department of ECE, KKR and KSR institute of technology and sciences
Engineering College
INTRODUCTION:
This document gives a overview of how to design & simulate with Mentor Graphics tools.
There are five basic steps:
1. Design the schematic in Pyxis.
2. Simulate the schematic and check for parameters.
3. Layout the schematic in Pyxis.
4. Perform Physical Verification using Calibre which includes DRC, LVS and PEX &
Net list Extraction.
5. Back annotation of parasitics into the schematic.
INVOKING MENTOR TOOLS:
Right click on the Linux desktop and click on open in terminal.
Type csh and press enter.
Type source /home/software/cshrc/cshrc130.cshrc

Type cd /home/software/FOUNDRY/GDK/Pyxis_SPT_HEP
Type ./pyxismgr and press enter then pyxis project manager window will be invoked as
shown below.
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CREATING A PROJECT:
To create a new project click on File New project, this will invoke the new project window as
shown.
Select the project path in the project navigator window.

Select the root folder.
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Create a new directory and give the directory name as shown and click on OK.
Next technology libraries have to be added to the project. In order to add the technology
files browse on the folder as shown.
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Browse the folder to
root/software/FOUNDRY/GDK/Pyxis_SPT_HEP/ic_reflibs/tech_libs/generic13 file and
click on OK.
Again click on OK then manage external/logic libraries window will pop up as shown.
Click on the Add Standard Libraries. The libraries will be added up as shown below and click
on OK.
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Then the pyxis project manager window will be shown where the technology libraries are added
to the project and are placed below the project name.
CREATING A LIBRARY:
To create a library right click on the project name and select new library or click on the icon on
the icon bar.
Then a new library window will pop up asking for the library name.
Next name the library and click on OK.
CREATING A SCHEMATIC CELL VIEW:
To create a schematic cell view, a new cell has to be created in which new Schematic has to be
defined. In order to create new cell right click on the manual library below the project name and
select new cell or select the library and click on the icon in the icon bar.
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Then a new cell window will pop up asking for the cell name in which give the cell name and
click OK.
To create a schematic in the cell, right click on the cell name and select new schematic
or click on the new cell and select the icon in the icon bar.
A window will pop up asking for the schematic name.
Now name the schematic and click on OK which in turn leads to the pyxis schematic
editor window as shown.
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CREATING A SCHEMATIC:
In this section you will become familiar with placing primitive analog devices for a inverter.
You‟ll learn how to:
• place primitives on the schematic
• select and manipulate devices
• customizing hotkeys for placing devices
• route devices
• edit device parameter values
• name instances
• check and save the schematic
• create upper hierarchical symbols
• create test bench
• simulate using eldo
• view results
CREATING AN INVERTER:
Placing devices:
From the left icon bar press on add instance icon
or press „I‟
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Then a file browser which contains entire libraries will pop up as shown.
Next double click on generic13 in the library list.
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And then follow the path to select pmos from $generic13/symbols/pmos as shown in the figure.
Select the pmos and click on OK to place the pmos on the workspace as shown.
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And then follow the path to select nmos from $generic13/symbols/nmos as shown.
Select the nmos and click on OK to place the nmos on the workspace as shown.
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CHANGING DEVICE PROPERTIES:
In order to change the properties of the devices on the workspace click on the device then the
corresponding device properties will be shown in the object editor as shown.
Change the Width & Length values of the Transistors to

For PMOS : L = 0.13u; W=0.3u
For NMOS : L = 0.13u; W =0.15u
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Connect the circuit as shown below.
ADDING THE PORTS AND CONNECTING THE DEVICES:

Select generic library and place ground from the Instance window.
In the similar way place IN and OUT ports as above from the generic library.
Then the schematic would look as follows
For changing the port names click on the port and change the net name in the object editor to the required
name as shown below.
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After editing the schematic check for errors by selecting check & save option in the icon
bar.
This will result to an window which shows the error report where the errors and warnings in the
schematic can be seen in the Transcript Area.
GENERATING THE SYMBOL:
Go to Add  Generate Symbol

Select Replace existing & activate symbol options. Click Ok.
Symbol gets generated for you.
Change the shape of symbol if required from choose shape.
Then click on OK which leads to the pyxis symbol window.
Save the symbol.
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After saving the symbol check for errors by selecting check and save option in the icon
bar.
schematic can be seen in the Transcript Area.
TEST BENCH CREATION:

To create a test bench close all schematics and symbol windows and go back to pyxis project
manager window. In the project manager window to create a new cell right click on the manual
library below the project name and select new cell or select the library
and click on the icon in the icon bar.
Then a new cell window will pop up asking for the cell name in which give the cell
name and click OK.
Here the test bench cell name has been specified as inv_tb.
Right click on the test bench cell and select new schematic which in turn opens pyxis Schematic
editor window.
Add symbol of the schematic made.
Add InstanceChoose Symbol.
Place the symbol on the work space as shown.
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Add a Pulse Source at the input to inverter and a DC Voltage source VDD port.
And do the necessary connections as per the figure given below.
Right click on the Pulse Source and select Edit Properties.
 Change the values of the below mentioned parameters and apply the changes.
 Initial = 0V Pulse = 5V Delay = 1nS Rise = 1nS
 Fall = 1nS Width = 25nS Period = 50ns.
Also change the magnitude of the Voltage Source from 1V to 5V by following the
below step.
Right Click on the Voltage source adjacent to VDD and then Edit properties
Next click on check & save icon in the icon bar.
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symbol can be seen in the Trascript area.
SIMULATING THE SCHEMATIC:
SIMULATING TEST BENCH
When you have no errors select the simulation icon from the left icon palette to go into the
design context and simulate our design and select the run simulation.
Now in the design context we need to setup the analysis type, plots and load in the ELDO
models.
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Select a New configuration (Give a new name for the simulation).
Select ac, dc, tran from setup simulation window.
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Select Analysis setup and enable “DC” and ”Transient” and click on Apply.
Drop down the Analysis setup and select DC setup give the parameters as
 Select option Source

 Select the voltage source as V1
 Start: 0 Stop: 5 Step 0.1 and click on Apply.
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Select Transient Setup and change the Stop time to 1000N click on Apply.
Select the input path A and then hold CTRL key and then output path Y.
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Click on Edit Probes from the Setup Simulation. Select DC in Analysis tab, Plot from Task
tab. Select add.
Select TRAN from Analysis tab and select add and close the window.
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Select the symbol, and from the setup simulation select TRAN in Analysis tab,
Plot from task tab, power from type tab then save and select add.
Select libraries from setup simulation, edit libraries window will pop up.
Select import library and browse for library path to /home/software/FOUNDRY/GDK/
Pyxis_SPT_HEP/ ic reflibs/tech libs/generic13/models/lib.eldo
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Select Edit Corners/Families, from Library Corners tab check for TT
Click on Ok.
Select Edit Scenarios from Device Families tab check for TT
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After adding the analysis, libraries and edit probes minimize the setup simulation window
and run the simulator. To run the simulation select from the left icon palette or select
simulate run simulation
View the simulation results by selecting the plot results from latest run icon from the
left icon palatte. This will open EZ Wave for you with the output waveforms.
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Click on Measurement tool in the icon bar which opens up the measurement
tool window where we can measure the different properties of your waveforms.
Save these waveform as inv_ideal .
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CREATING A LAYOUT:
• To create a layout select inv cell. Right click on the cell and select New layout.
A new window named New layout will pop up, here the layout name is same as the cell name as
shown and click Ok.
Pyxis layout window will be invoked with a New layout sub-window in it and keep the
settings as shown and click on OK.
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Make the Schematic window active by selecting it with the Left Menu Bar. Select PMOS and
Press on the Pick & Place icon from the SDL tool bar on the Icon Bar. The tool will place
the device on the Workspace of IClayout window. Similarly select the NMOS and place it on
the workspace.
Note: To make SDL toolbar active, goto setup->toolbar->SDL tool bar
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With the layout window active, select the Pick Place Ports icon from the SDL toolbar.
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Place Schematic ports window will pop up. Select the VDD port and select a layer for this port.
The Width and Height will be updated automatically according to the minimum metal1
dimensions. Press Apply to place the port.
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Place the rest of the ports.
To add the substrate contacts to the mosfets. Select Add Device icon from the Left Hand Palette,
then select Path-based Guard Band select psub
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Do the same for but choose nwell instead of psub
To add the over flow lines for both psub & nwell , Select psub then Connectivity > Net > Add
to Net to set psub to Ground and the same for nwell to set it to VDD
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ROUTING THE LAYOUT:
Manual routing:
To start routing press on the IRoute icon in the SDL toolbar. Once you place the cursor on
where you want to start routing, it will start guided by the fly lines. You can toggle between the
connectivity layers by pressing space-bar
Route all the ports in the layout except input port as shown
For routing poly and input port of M1, VIA has to be created.
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Routing Poly-M1
VIA CREATION:
Select Route in the ic palatte window as shown
Now select Options in ARoute Setup then following window will be invoked
Click on Advanced button in the ARoute Options window.
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Then Advanced route options window pops up, Select the VIA OPTIONS check use via
generator and click OK and OK.
Select Iroute, place POLYG at the input and start routing as shown. Now press SPACE BAR
automatically VIA will be created.
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Then complete layout for the inverter will be generated as shown.
PHYSICAL VERIFICATION OF LAYOUT:

1. DRC
2. LVS
3. PEX
1.DRC:
Now you can verify the layout by running DRC and LVS checks. We will run Calibre Interactive
RUNNING CALIBRE INTERACTIVE DRC:
In the pyxis layout window, Select Tools CalibreRun DRC
This will bring up the Calibre Interactive – DRC
Note: Make sure the tabs named Rules, Inputs, Outputs, Run control should be green in color as
shown above which ensures the paths specified are correct. Otherwise paths have to be changed .
Select Run DRC in the Calibre Interactive window.
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The Calibre RVE window will popup and you should see the following results.
The error in the layout will be highlighted as shown in the fig once if you select on the error.
Here the error is due to the percentage of the polysilicon. It requires polyarea coverage of 14%
which is not possible in the smaller circuits. So you can ignore that error.
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RUNNING LVS (Layout versus Schematic):
Before going to LVS, text the ports on the layout .In the pyxis window menu bar select
Add  Text on Ports.
Add text on ports window will pop up. Here click on OK then automatically port names will be
assigned to layout.
LVS:
Select Tools  Calibre  Run LVS entry from the pull down menu.
The Calibre Interactive – LVS window will popup.
Inputs : layout browse for GDS file.
Check “Export from layout viewer” & “Export from schematic viewer” format.
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Select Run LVS in the Calibre Interactive window shown above.
Calibre RVE window will popup and you should see results similar to this.
If the comparison is wrong click on the comparison results in the RVE window, which shows the
results and select schematics then the netlists will be displayed as shown
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Click on the blocks of the Netlist of the schematic and layout which yields the circuits from you
can verify the connections and ports name and avoid the incorrect LVS.
RUNNING CALIBRE INTERACTIVE PEX:
Select Tools Calibre  Run PEX from the menu.

The Calibre Interactive – PEX window will popup.
Make sure Export from schematic viewer is selected while the Inputs and Netlist tabs are
active as shown.
Choose the Outputs netlist to be in DSPF Format and select only R+C instead of R+C+C from
the Extraction Type as in the figure below.
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Select Run PEX
The PEX Netlist file windows will be invoked as shown.
Save the PEX netlist file as inv.pex.dspf in the path as shown in the figure or any location of
your computer.
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The File is successfully written and click on OK.
Select Start RVE from Calibre Interactive - PEX.

Calibre RVE window will pop up select parasitics in the navigator then extraction results will be
shown as shown below
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Double click on the port name then the parasitic values will be shown
Double click on the value, then corresponding value will be highlighted in the layout as Shown.
POST LAYOUT SIMULATION:
Open the test bench schematic and enter the simulation mode, then select the inverter block
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Select Tools ParasiticsAdd DSPF
A window named Add DSPF will pop up where browse on the folder to the saved Netlist
inv.pex.dspf and click OK as shown.
Run the simulation by selecting run simulation icon on left icon panel.
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You can Add & Remove DSPF in Parasitic which show results with & without Parasitic.
View the wave‟s output signal.
There is a noticable increase in the delay due to the parasitics.

Save the waveforms as practical.
WAVEFORM COMPARISION:
To compare the waveforms we must save both ideal and practical waveforms i.e, test bench
waveform and layout waveform.
Open both ideal and practical waveforms on the database which we have saved earlier.
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In EZ wave 12.1 production window select the Tools menu and click on the waveform compare
wizard as shown in the figure below.
Browse the path for Choose Reference Dataset from List or Disk as shown below.
Select Compare All Waveforms and click on Next.
Click on Finish.
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The comparision results of both ideal and practical waveforms are shown below.
This ends the full custom IC design flow for an inverter using HEP 1 Design tools from Mentor
Graphics.
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Dept. of E C E VLSI LAB
1. UNIVERSAL GATES
AIM: To design and implement Universal gates.
a) NAND Gate.
b) NOR Gate.
SOFTWARES: Mentor Graphics Back End Tool - HEP-1, Personal computer.
CIRCUIT DIAGRAM:
a). NAND GATE
TRUTH TABLE:
SYMBOL:
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SIMULATION CIRCUIT:
PROCEDURE:
1. Create a schematic cell named ‘nand1’ in already created project.

2. Create a new pyxis schematic ‘nand1’ in schematic cell.
3. Open schematic window and draw the cmos logic circuit. Check and save the design of
cmos inverter.
4. Generate symbol. Check and save the symbol.
5. Create new test bench cell named ‘nand1_tb’. Create new test bench schematic named
‘nand1_sim’.
6. Draw the test bench. Check and save the test bench.
7. Set up the probes for DC, TRANSIENT and POWER analysis.
8. Run ELDO and display the waveforms on EZWAVES.
9. Verify the wave forms with truth table.
10. Open new layout named ‘nand1’ in schematic cell. Draw the layout
11. After implementing the layout go to tools –caliber-run DRC, LVS, and PEX.
12. Open test bench and enter into the simulation mode.
13. Assign .pex file to the test bench symbol.
14. Repeat the steps 8 & 9 for post layout results.
15. Compare the schematic and layout results.
SIMULATION RESULTS:
Schematic Result:
Transient Analysis Result:
Layout Result:
Power Calculation :
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b) NOR GATE
CIRCUIT DIAGRAM:
TRUTH TABLE:
SYMBOL:
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SIMULATION CIRCUIT:
PROCEDURE:
1. Create a schematic cell named ‘nor1’ in already created project.
2. Create a new pyxis schematic ‘nor1’ in schematic cell.
cmos inverter.
5. Create new test bench cell named ‘nor1_tb’. Create new test bench schematic named
‘nor1_sim’.
10. Open new layout named ‘nor1’ in schematic cell. Draw the layout
SIMULATION RESULTS:
Schematic Result:
Layout Result:
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Power Calculation:
RESULT:
VIVA QUESTIONS:
1. What do you mean by universal gate?
2. What is meant by logic analyzer?
3. Why is NAND gate preferred over NOR gate for fabrication?
4. Difference between TTL, ECL , present days cmos is competing with which of these
logics
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2. CMOS INVERTER
AIM: To design and implement CMOS inverter
SOFTWARES: Mentor Graphics HEP-1, Personal computer
CIRCUIT DIAGRAM OF CMOS INVERTER
TRUTH TABLE:
SYMBOL:
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SIMULATION CIRCUIT:
PROCEDURE:
1. Create a schematic cell named ‘inv1’ in already created project.

2. Create a new pyxis schematic ‘inv1’ in schematic cell.
cmos inverter.
5. Create new test bench cell named ‘inv1_tb’. Create new test bench schematic named
‘inv1_sim’.
10. Open new layout named ‘inv1’ in schematic cell. Draw the layout
SIMULATION RESULTS:
DC Analysis Result:
Power calculation:
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RESULT:
VIVA QUESTIONS:
1. Give the expression for CMOS switching power dissipation?
2. Define PIV?
3. What is Noise Margin? Explain with the help of Inverter.
4. Impartance of Inverter Circuit?
Answers:
1. Pstatic =Vdd * Ileakage
2. State where N MOS and PMOS are in conduction state
3. Noise Margins could be defined as follows :

NMl (NOISE MARGIN low) = Vil - Vol = 0 - 0 = 0
NMh (NOISE MARGIN high) = Voh - Vih = Vdd - Vdd = 0
4. It is a basic logic gate which is used in all digital circuits
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3. FULL ADDER
AIM: To design and implement Full Adder
CIRCUIT DIAGRAM:
TRUTH TABLE:
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XOR GATE
CIRCUIT DIAGRAM:
SYMBOL:
SIMULATION CIRCUIT:
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AND GATE
CIRCUIT DIAGRAM:
SYMBOL:
SIMULATION CIRCUIT:
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OR GATE
CIRCUIT DIAGRAM:
SYMBOL:
SIMULATION CIRCUIT:
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Symbol:
Full Adder Test Bench:
PROCEDURE:
1. Create a schematic cell named ‘fa1’ in already created project.

2. Create a new pyxis schematic ‘fa1’ in schematic cell.
cmos inverter.
5. Create new test bench cell named ‘fa1_tb’. Create new test bench schematic named
‘fa1_sim’.
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10. Open new layout named ‘fa1’ in schematic cell. Draw the layout
SIMULATION RESULTS:
Schematic Results: Transient Analysis Result:
RESULT:
VIVA QUESTIONS:
1. Difference between HA and FA?
2. Design the half Adder using NAND-NAND Logic.
3 What is the use of Carry-lookahead adder?
4. How-does-a-carry-select-adder-work ?
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4. FULL SUBTRACTOR
AIM: To design and simulate the Full Subtractor
CIRCUIT DIAGRAM:
TRUTH TABLE:
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XOR GATE
CIRCUIT DIAGRAM:
SYMBOL:
SIMULATION CIRCUIT:
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AND GATE
CIRCUIT DIAGRAM:
SYMBOL:
SIMULATION CIRCUIT:
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OR GATE
CIRCUIT DIAGRAM:
SYMBOL:
SIMULATION CIRCUIT:
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SYMBOL:
Full Subtractor: Symbol:
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SIMULATION CIRCUIT:
PROCEDURE:
1. Create a schematic cell named ‘fs1’ in already created project.

2. Create a new pyxis schematic ‘fs1’ in schematic cell.
cmos inverter.
5. Create new test bench cell named ‘fs1_tb’. Create new test bench schematic named
‘fs1_sim’.
10. Open new layout named ‘fs1’ in schematic cell. Draw the layout
SIMULATION RESULTS :
Schematic Results:Transient Analysis Result:
RESULT:
VIVA QUESTIONS:
1.Draw Full Subtractor circuit by using Half Subtractor circuit and minimum
no. of logic gate?
2. Write Boolean function for half Subtractor?
67
5. 2 X 4 DECODER
AIM: To design and simulate the 2 X 4 decoder
CIRCUIT DIAGRAM:
TRUTH TABLE:
SYMBOL:
68
SIMULATION CIRCUIT:
PROCEDURE:
1. Create a schematic cell named ‘rsl1’ in already created project.

2. Create a new pyxis schematic ‘rsl1’ in schematic cell.
cmos inverter.
5. Create new test bench cell named ‘rsl1_tb’. Create new test bench schematic named
‘rsl1_sim’.
10. Open new layout named ‘rsl1’ in schematic cell. Draw the layout

RESULT:
VIVA QUESTIONS:
1. What is 2 x4 decoder?
2 What are decoder applications?
3 .Where is decoder used?
4. What i9sm the purpose of decoder?
69
6. RS-LATCH
AIM: To design and simulate the RS-Latch
CIRCUIT DIAGRAM:
TRUTH TABLE:
NAND GATE
70
SYMBOL:
SYMBOL:
SIMULATION CIRCUIT:
71
PROCEDURE:
16. Create a schematic cell named ‘rsl1’ in already created project.

17. Create a new pyxis schematic ‘rsl1’ in schematic cell.
cmos inverter.
20. Create new test bench cell named ‘rsl1_tb’. Create new test bench schematic named
‘rsl1_sim’.
25. Open new layout named ‘rsl1’ in schematic cell. Draw the layout

RESULT:
VIVA QUESTIONS:
1.What is Flip-Flop?
2 What is Latch circuit?
3 .What is the disadvantages of S-R Flip-Flop?
4. How can you remove the problem of S-R Flip –Flop?
5. What do you understand by Race Aground condition? How it is over come in J-K Flip Flop?
72
7. D-LATCH
AIM: To design and simulate the D-Latch
CIRCUIT DIAGRAM:
TRUTH TABLE:
73
NAND GATE
SYMBOL:
74
SYMBOL:
D- latch SYMBOL :
SYMBOL:
75
SIMULATION CIRCUIT:
PROCEDURE:
1. Create a schematic cell named ‘dl1’ in already created project.

2. Create a new pyxis schematic ‘dl1’ in schematic cell.
cmos inverter.
5. Create new test bench cell named ‘dl1_tb’. Create new test bench schematic named
‘dl1_sim’.
10. Open new layout named ‘dl1’ in schematic cell. Draw the layout
76
SIMULATION WAVEFORMS: Transient Analysis
RESULT:
VIVA QUESTIONS:
1.What is meant by a clocked flip-flop
2.What is meant by excitation table?
3. What is the difference between flip-flop and latch?
4. What are the various methods used for triggering flip-flops?
5.Explain level triggered flip-flop?
77
8. ASYNCHRONOUS COUNTER
AIM: To design and implement asynchronous counter
LOGIC CIRCUIT:
TRUTH TABLE:
78
SYMBOL:
TESTBENCH:
PROCEDURE:
1. Create a schematic cell named ‘asc1’ in already created project.

2. Create a new pyxis schematic ‘asc1’ in schematic cell.
cmos inverter.
5. Create new test bench cell named ‘asc1_tb’. Create new test bench schematic named
‘asc1_sim’.
79
10. Open new layout named ‘asc1’ in schematic cell. Draw the layout
SIMULATION RESULTS:
RESULT:
VIVA QUESTIONS:
1. Differentiate between synchronous and asynchronous counter?
2. How many no.of flip-flops are required for decade counter?
3. If the modulus of a counter is 12 how many flip-flops are required?
4. What is a sequential circuit?
80
9. STATIC RAM CELL

AIM: To design and simulate the Static RAM Cell

.
CIRCUIT DIAGRAM:
SYMBOL:
81
SIMULATION CIRCUIT:
PROCEDURE:
1. Create a schematic cell named ‘src1’ in already created project.

2. Create a new pyxis schematic ‘src1’ in schematic cell.
cmos inverter.
5. Create new test bench cell named ‘src1_tb’. Create new test bench schematic named
‘src1_sim’.
10. Open new layout named ‘src1’ in schematic cell. Draw the layout
Schematic Results:
Power Calculation Result:
82
RESULT: Hence SRAM cell is designed, sinulated and Layout is drawn using Mentor graphics
tool.
VIVA QUESTIONS:
1. What is the meaning of RAM, and what is its primary role?
2. The storage element for a static RAM is the
3. What is meant by semiconductor memory devices?
4. Difference between static ram and dynamic ram
83
10. 8 BIT DAC USING R-2R LATTER NETWORK

AIM: To design and simulate the 8 bit DAC using R-2R latter network

.
CIRCUIT DIAGRAM:
SYMBOL:
84
SIMULATION CIRCUIT:
PROCEDURE:
1. Create a schematic cell named ‘src1’ in already created project.

2. Create a new pyxis schematic ‘src1’ in schematic cell.
cmos inverter.
5. Create new test bench cell named ‘src1_tb’. Create new test bench schematic named
‘src1_sim’.
10. Open new layout named ‘src1’ in schematic cell. Draw the layout
Schematic Results:
85
Power Calculation Result:
RESULT: Hence 8 bit DAC using R-2R latter network is designed, sinulated and Layout is
drawn using Mentor graphics tool.
VIVA QUESTIONS:
1. What are applications of DAC?
2. What are the different types of DAC?
3. What are the advantages of R-2R latter DAC?
86

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VLSI LAB

M. Madhusudhan Reddy, M.Tech

KKR & KSR INSTITUTE OF TECHNOLOGY & SCIENCES

Contents of Lab Manual

INSTITUTE VISION /MISSION

 To ensure all round development of students through judicious blend of curricular,

 To provide higher/continued education and research opportunities to the employees of

To develop highly qualitative, technically competent and socially responsible engineers.

Mission of ECE Department

To provide quality education in the domain of Electronics and Communication Engineering

facilities and collaborative ventures with the industries.

FACULTY I/C HOD

PROGRAM OUTCOMES (PO’S)

FACULTY I/C HOD

PROGRAM SPECIFIC OUTCOMES (PSO’S)

PSO2: Problem-solving skills

To be equipped with the principles of Semiconductor Devices, Digital Systems, Microprocessor

PSO4 :Exposure for research and development:

PSO5 :Development for real time applications

FACULTY I/C HOD

PROGRAM EDUCATIONAL OUTCOMES (PEO’S)

PEO4: Function effectively in a multi-disciplinary environment and individually, within a global,

Basic knowledge about chip I/O circuits, fault models

Faculty I/C H.O.D

(Approved by AICTE, Delhi, Affiliated to JNTU, Kakinada,

MAPPING OF CO’S WITH PO’S

MAPPING OF CO’S WITH PSO’S

PSO1 PSO2 PSO3 PSO4

1: LOW 2:MEDUIM 3:HIGH

Faculty I/C H.O.D

INVOKING MENTOR TOOLS:

Right click on the Linux desktop and click on open in terminal.

Type csh and press enter.

Type source /home/software/cshrc/cshrc130.cshrc

Select the project path in the project navigator window.

Next name the library and click on OK.

CREATING A SCHEMATIC CELL VIEW:

A window will pop up asking for the schematic name.

Next double click on generic13 in the library list.

Change the Width & Length values of the Transistors to

ADDING THE PORTS AND CONNECTING THE DEVICES:

GENERATING THE SYMBOL:

Go to Add  Generate Symbol

TEST BENCH CREATION:

Next click on check & save icon in the icon bar.

SIMULATING THE SCHEMATIC:

SIMULATING TEST BENCH

Select ac, dc, tran from setup simulation window.

 Select option Source

Select Edit Scenarios from Device Families tab check for TT

Save these waveform as inv_ideal .

Note: To make SDL toolbar active, goto setup->toolbar->SDL tool bar

Click on Advanced button in the ARoute Options window.

PHYSICAL VERIFICATION OF LAYOUT:

Select Run DRC in the Calibre Interactive window.

RUNNING CALIBRE INTERACTIVE PEX:

Select Tools Calibre  Run PEX from the menu.

Select Start RVE from Calibre Interactive - PEX.

POST LAYOUT SIMULATION: