Latch Up Failure in IGBT
Latch Up Failure in IGBT
Latch Up Failure in IGBT
Abstract
Latch-up failure is one of the most &mrtant failure
phenomena of IGBT modules because of the pn-p-n
sandwich device structure. Half-bridge IGBT modules
latch-up failure was observed by switching test. SEM +1sv @#I
technique was employed in the failure analysis work in
order to investigate how the module was destroyed by
n
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latching-up. This paper reports the failure analysis re-
sults and the relevant failure analysis techniques used in
the work..
Power IGBT (Insulated Gate Bipolar Transistor) (T2) can be tested by switching. The interest thing is that
modules are widely used in power electric industries not only the tested low-leg IGBT (T2) was burnt out in
today, such as traction, locomotive, elevator, tram and the test, but the up-leg IGBT, i.e. the untested T1, was
subway. In the mean time, electric engineers follow the also destroyed even more terribly, as shown in figure 2.
reliability problems of IGBT with great interest. Latch- From figure 1 it can be seen that 800V voltage is applied
up failure of IGBT at turn-on andor turn-off is one of to the collector of T2. When T2 is turned on, the current
the most important failure phenomena, because of E flows through it but the rate-of rise of E (di/dt) will be
IGBT’s p-n-p-n sandwich structure, i.e. the parasitic limited by the inductance L, meaning the di/dt can not
thyristor effect. damage the module at the moment. But at the same time
Burnout failure of half-bridge IGBT modules at the voltage at the collector of T2 reduces from 8OOV to
turn-on was observed in tests, which was trigged by high its on-state voltage (Vmp2V), resulting in a dv/dt at
surging voltage dv/dt. SEM (Scanning Electron Micro- the point A (the collector of T2 and the emitter of Tl).
scope) technique, combining with other facilities, was
employed in the failure analysis works in order to deter-
mine the failure mechanisms of IGBT modules. This
paper reports the failure analysis results and the relevant
failure analysis techniques used in the work.
Tbis work was p d y suppnat by the Naaval Science Fouadation of China (69696035).and by the Nahval Science Poundationof Beijing City (4982006).
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Obviously, the value of dv/dt depends on the r& seriously the latching up failure destroyed the device
ducing rate of the voltage at the collector of T2,which internal structure of IGBT chip, SEM investigation on
is determined by the turn-on time of T2. T1 has a p-n- the cross-section of IGBT chip was done continually.
p-n thyristor-like structure, see figure 3. If the value of
dv/dt is high enough, then the parasitic thyistor in
IGBT will be turned on, no matter how the gate
biasing is [l] [2]. Whenever IGBT enters latching, it
loses the gate-controlled characteristics and the op-
eration mode of IGBT changes from transistor mode
to high current thyristor mode. As a result, the module
will be destroyed by very high power dissipation
[3][4]. This is the case with T1. As soon as T1 was
destroyed, 800V biasing acted to T2 immediately,
which was in the on state at the moment. Also, T2 was
destroyed by high power dissipation.
References
111 P.D.Taylor, ‘Thyristor Design and Realization”, John
Wiley & Sons, 1987, p.66
[2] A.P.Silard,et al., ‘The Importance of the n-Base in p-
n-p-n -like Structure Subjected to dv/dt Ramps”,
JEEE EDL, Vol.EDL-9, p.197-199, May 1988
[3] B.J.Baliga, “Modem Power Devices”, John Wiley &
Sons, 1987, p.369
[4] A.L.Robinson, et al., “Lateral Insulated Gate Tran-
sistors with Improved Latching Characteristics”,
IEEE EDL, Vol. EDL7, p.61-63, Feb. 198