Latch Up Failure in IGBT

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SEM Irivestigation on IGBT Latch-up Failure’


Wuchen Wu, Changyong Fan, Yajie Wang, Yangang Wang, Xueqing Cui
Electronic Engineering Department, Beijing Polytechnic University
Beijing, 100022, P. R.China, Email: wchwuC9bjpu.du.cn Tell: 6739 1638

Peter Jacob, Marcel Held


Swiss F e d d Institute Of Technology (ETH), Zurich, CH-8092, Switzerland

Abstract
Latch-up failure is one of the most &mrtant failure
phenomena of IGBT modules because of the pn-p-n
sandwich device structure. Half-bridge IGBT modules
latch-up failure was observed by switching test. SEM +1sv @#I
technique was employed in the failure analysis work in
order to investigate how the module was destroyed by
n
I I
-‘i I T* IIC ; I
latching-up. This paper reports the failure analysis re-
sults and the relevant failure analysis techniques used in
the work..

I. Introduction Fig.1 IGBT switching test circuit

Power IGBT (Insulated Gate Bipolar Transistor) (T2) can be tested by switching. The interest thing is that
modules are widely used in power electric industries not only the tested low-leg IGBT (T2) was burnt out in
today, such as traction, locomotive, elevator, tram and the test, but the up-leg IGBT, i.e. the untested T1, was
subway. In the mean time, electric engineers follow the also destroyed even more terribly, as shown in figure 2.
reliability problems of IGBT with great interest. Latch- From figure 1 it can be seen that 800V voltage is applied
up failure of IGBT at turn-on andor turn-off is one of to the collector of T2. When T2 is turned on, the current
the most important failure phenomena, because of E flows through it but the rate-of rise of E (di/dt) will be
IGBT’s p-n-p-n sandwich structure, i.e. the parasitic limited by the inductance L, meaning the di/dt can not
thyristor effect. damage the module at the moment. But at the same time
Burnout failure of half-bridge IGBT modules at the voltage at the collector of T2 reduces from 8OOV to
turn-on was observed in tests, which was trigged by high its on-state voltage (Vmp2V), resulting in a dv/dt at
surging voltage dv/dt. SEM (Scanning Electron Micro- the point A (the collector of T2 and the emitter of Tl).
scope) technique, combining with other facilities, was
employed in the failure analysis works in order to deter-
mine the failure mechanisms of IGBT modules. This
paper reports the failure analysis results and the relevant
failure analysis techniques used in the work.

II. Latch-up failure of bridging IGBT mod-


ules
A series of experiments including switching, ther-
mal cycling, vibration, and shocking were carried out in
order to investigate the reliability behavior of bridging
IGBT modules.
The switching test circuit is shown in figure 1, in
which the upleg IGBT (Tl) is kept “off state” by a -12
V gate-toemitter biasing, then only the low-leg IGBT
Fig.2 A top view photograph of a failed IGBT module.

Tbis work was p d y suppnat by the Naaval Science Fouadation of China (69696035).and by the Nahval Science Poundationof Beijing City (4982006).

0-7803-65209/01/$10.00 0 2001 IEEE.


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I I
! J1 J2 J3 !

Hg.3 A p-n-p-n thyristor-like structure of IGBT

Obviously, the value of dv/dt depends on the r& seriously the latching up failure destroyed the device
ducing rate of the voltage at the collector of T2,which internal structure of IGBT chip, SEM investigation on
is determined by the turn-on time of T2. T1 has a p-n- the cross-section of IGBT chip was done continually.
p-n thyristor-like structure, see figure 3. If the value of
dv/dt is high enough, then the parasitic thyistor in
IGBT will be turned on, no matter how the gate
biasing is [l] [2]. Whenever IGBT enters latching, it
loses the gate-controlled characteristics and the op-
eration mode of IGBT changes from transistor mode
to high current thyristor mode. As a result, the module
will be destroyed by very high power dissipation
[3][4]. This is the case with T1. As soon as T1 was
destroyed, 800V biasing acted to T2 immediately,
which was in the on state at the moment. Also, T2 was
destroyed by high power dissipation.

III. SEM investigation on the failed IGBT Fig.4 A SEM microphotographof a


modules crarterlke melting pit in emitter bonding pad.
In order to determine the failure mechanism of the The key point of this step is to prepare the cross
modules failed in switching test, failure analysis work section samples of the failed IGBT chip without any
was done in the following procedure. First step is to additional damage to the chip cross section. At first, the
open and remove the plastic cap mechanically with no chip was cut into two parts by a diamond saw, and the
additional damage to IGBT chips. Second is to remove cutting was aligned the centerline of the crater-like
the inner-filled gel and to c l m the chip surface chemi- melting pit. Nine steps of polishing were done with a
cally followed by an internal visual check performed special polishing machine in order to remove the cuttjng-
with optical microscope in order to detect the failure introduced damages to the chip cross section. The nine
position and determine the failure mode. Figure 2 shows polishing steps are as fol1ows:l) 70pm diamond plate
bonding wire burning out failure. SEM technique was
grinding, 2) 3 2 6 Sic paper grinding ( 4 6 p ) , 3) 50V
used for deeper investigation: the failure mechanism
determination. S i c paper polishing OW), 4) looo* Sic paper polish-
At first, the wire bonding melting failure was care- . 2400" SIC paper polishing (low),6)
ing ( 1 8 ~ ) 5)
fully studied by SEM. Figure 4 is a SEM microscopic 4000" Sic paper polishing ( 5 ~ ) 7). DP-cIoth polishing
photograph showing a big crater-like melting pit in the ( 3 ~ ) 8). DPcloth polishing ( 1 ~ ) 9) . DP-Suspension
wire bonding pad. mirror polishing ( 0 . 2 5 ~ ) .In the first 5 polishing steps
Such a crater-like melting pit has just the peculiar water was used as lubricant. From step 6 to step 8 DP-
melting pit pattern of thyristor latching up failure. So, it lubricant, instead of water, was used as the lubricant in
was verified that the failure mechanism of IGBT tested the polishing. After step 9, a cross sectional specimen
in switching is latching up failure, which is in agreement with mirror smooth finish was obtained. Another key
with the theory analysis above. In order to analyze how step is to cover a thin layer Au to the specimen by
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evaporation technology. Figure 5 is a SEM microphoto- IV. Conclusion


graph of the cross sectional structure destroyed by
latching up. From figure 5 it can be seen that the melting SEM technique was employed in IGBT latching up fail-
pit penetrated so deeply into silicon chip that the device ure analysis. SEM micrograph shows a big crater-like
structure. was completely destroyed. It can also be seen melting pit in the wire bonding pad and verifies the fail-
in the figurethere is a destructive conducting track under ure mechanism of IGBT is latching up failure, because
the melting pit, made in a wink by overcurrent and ther- the melting pit has just the peculiar melting pit pattern of
mal runaway, which passes through silicon chip to the thyristor latching up failure. Besides, it is conformed that
solder layer. The temperature inside the silicon chip, at latch-up can destroy IGBT from wire bonding to chip
the moment of latching, could be higher than the silicon structure completely.
melting point temperature (1412OC).

References
111 P.D.Taylor, ‘Thyristor Design and Realization”, John
Wiley & Sons, 1987, p.66
[2] A.P.Silard,et al., ‘The Importance of the n-Base in p-
n-p-n -like Structure Subjected to dv/dt Ramps”,
JEEE EDL, Vol.EDL-9, p.197-199, May 1988
[3] B.J.Baliga, “Modem Power Devices”, John Wiley &
Sons, 1987, p.369
[4] A.L.Robinson, et al., “Lateral Insulated Gate Tran-
sistors with Improved Latching Characteristics”,
IEEE EDL, Vol. EDL7, p.61-63, Feb. 198

Fig5 A SEM cross-sectional microphotograph


of a cratelike melting pit.

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