FinFets

A comprehensive simulation study has been conducted to show fine-grain reconfigurability in CMOS circuits using work-function engineering (WFE) on Schottky Barrier (SB) FinFETs for sub-10 nm gate length. The study has three subsections. First, two-transistor (2T) & 4T AOI (and-or-invert)/ OAI (or-and-invert) gates with select bits that allow multiple logic functions are introduced. Secondly, the use of WFE to create ultra-compact reconfigurable logic circuits of fundamental operations (0,1,OR, AND,NAND,NOR,XOR) are explored via novel 2T, 3T and 4T gates. These circuits include one or two select bits that are capable of commanding up to four functions with two inputs. To further illustrate the potential of WFE for reconfigurable logic, novel multi-stage circuits such as compact full-adders are also modelled via TCAD simulations. Power×delay product (PDP) figures and DC gain of the proposed gates are quantified and compared against the CMOS designs with similar functionality. Finally, we also design a novel compact one-bit arithmetic logic unit (ALU) which has seven exclusive logic operations (1, NAND, OR, XOR, NOR, Addition, Subtraction) with three select bits using only 26 SB-FinFETs, saving substantial amount of power and chip area. The trade-offs between the number of metal work-functions used in the designs, circuit complexity and simulated performance metrics are also provided. The comparative simulations between reconfigurable SB-FinFET based designs versus conventional p-n junction FinFET circuits show that WFE can lead to absolutely minimalist reconfigurable CMOS logic blocks using ×3 to ×10 less power and between ×2 and ×15 less area than static CMOS counterparts. Although they suffer greater delays (×2 to ×5), the overall PDP performance remains comparable to conventional CMOS.

With the aggressive downscaling of process technologies and the importance of battery-powered systems, reducing leakage power consumption has become a crucial design challenge for IC designers. In addition, the traditional bulk CMOS technologies face significant challenges related to short-channel effects and process variations. FinFET devices have attracted a lot of attention as an alternative to bulk CMOS in sub-32nm technology nodes. This paper presents a device-circuit cross-layer framework to utilize fine-grained gate-length biased FinFETs for circuit leakage power reduction in near-and super-threshold (VT) operation regimes. The impacts of cell-level and transistor-level Gate-Length Biasing (GLB) on circuit speed and leakage power are studied using a 7nm FinFET technology.

Novel ultra-compact sub-10nm XOR, NOR and NAND CMOS logic circuits based on ambipolar characteristics of Schottky-Barrier (SB) FinFET devices and gate metal workfunction engineering are introduced. Use of SB source and drain contacts, high-k gate dielectrics and ultra-thin body bestows extreme short-channel immunity to the proposed FinFETs with ambipolar current-voltage characteristics. Thus, the main physical parameter left for practical device design and threshold control is the gate workfunction along with independent-gate drive, which is creatively used in this work to build a novel conjugate (n/p channel) CMOS pass-gate transistor that can function as a two-transistor (2T) XOR gates as opposed to 4 transistor conventional pass-gates. In a similar fashion, gate workfunction engineering can be utilized to design unique ambipolar FinFETs with two independent gates and high thresholds to function as 2T NAND and NOR gates. Functionality of the proposed minimalist logic circuits are verified with Synopsys TCAD simulations, which indicate that optimized gate work-functions lead to CMOS logic circuits as small as 5nm and supply voltage of 0.6V, with a power-delay product at 5 χ 10−18 J level.

Differential Amplifier is a primary building block of analog and mixed signal circuit for pre-processing and signal conditioning of analog signal. FINFET devices with high-k gate oxide at 22nm technology are predominantly used for high speed and low power complex VLSI circuits. FINFET based differential amplifiers are widely used in ADC's and signa l Processing applications due to their advantages in terms of power dissipation. Analog front end of complex VLSI circuits need to offer high gain, higher stability and low noise figure. Designing of FINFET based VLSI sub-circuits requires proper design procedure that can provide designers flexibility in controlling the circuit performances. In this paper, differential amplifier is designed using model parameters of high-k FINFET in 22nm technology. The conventional procedures for designing MOSFET based differential amplifier are modified for designing FINFET based differential amplifier. Schematic capture is carried out in Cadence environment and simulations are obtained considering 22nm FINFET PDK. The performance metrics are evaluated and optimized considering multiple iterations. The designed differential amplifier has slew rate of 6V/µSec and settling time of 0.9 µSec which is a desired metric for ADCs. Power Supply Rejection Ratio (PSRR) is 83 dB and dynamic range is 1.6754 V. Open loop DC gain of DA is achieved to be 103 dB with phase margin of 630 that demonstrates the advantages of DA designed in this work suitable for analog front end.

Ultracompact sub-10-nm logic gates based on ambipolar characteristics of Schottky-barrier (SB) FinFETs and gate workfunction engineering (WFE) approach are introduced. Novel logic gate designs are proposed using WFE, whereby adjustment of workfunction in the contacts as well as two independently biased FinFET gates leads to an unprecedented degree of freedom for logic functionality that has not been explored before. The use of SB contacts , along with the high-k gate dielectric and ultrathin body, bestows a high-degree of short-channel immunity to the SB-FinFETs with ambipolar current-voltage characteristics down to 5 nm. The unique trait of the proposed novel logic gates is to lower CMOS transistor count by 50% and hence reduce overall area and power dissipation significantly. To illustrate this potential, an entirely novel conjugate (n/p channel) CMOS pass-gate transistor that can function as a two-transistor (2T) xor and minimalist 2T nand/nor gates is designed and verified with TCAD simulations. Depending on the gate designed, TCAD simulations indicate that judicious choice of gate workfunctions between 3.7 and 5.2 eV can lead to CMOS logic gates with a power-delay product (PDP) at 5×10 −18 J level with immunity to ±0.1-eV workfunction variations. It is shown that WFE in independent-gate SB-FinFETs can lead to ultracompact logic circuits with 50% reduction in area and up to 10 times reduction in power, without significant degradation to overall PDP performance due to slower switching response compared with the conventional designs with p-n junction FinFET counterparts.

Aging is an important concern in long term reliability of semiconductor devices. In this regard, Bias Temperature Instability (BTI) is considered the major aging mechanism in nanometer regime, particularly in FinFET devices. Therefore, a well understanding of BTI mechanism in FinFET technology is of high interest. In this paper, a three-dimensional TCAD analysis about the impact of negative BTI (NBTI) FinFET technology is presented. In addition, a new NBTI degradation model is proposed for FinFET devices that can be incorporated in Spice which allow to consider aging of a circuit in a design phase. The three-dimensional TCAD analysis is performed using Synopsys Sentaurus tool. Results from the proposed model agree with Sentaurus degradation results.

Novel ultra-compact sub-10nm XOR, NOR and NAND CMOS logic circuits based on ambipolar characteristics of Schottky-Barrier (SB) FinFET devices and gate metal workfunction engineering are introduced. Use of SB source and drain contacts, high-k gate dielectrics and ultra-thin body bestows extreme short-channel immunity to the proposed FinFETs with ambipolar current-voltage characteristics. Thus, the main physical parameter left for practical device design and threshold control is the gate workfunction along with independent-gate drive, which is creatively used in this work to build a novel conjugate (n/p channel) CMOS pass-gate transistor that can function as a two-transistor (2T) XOR gates as opposed to 4 transistor conventional pass-gates. In a similar fashion, gate workfunction engineering can be utilized to design unique ambipolar FinFETs with two independent gates and high thresholds to function as 2T NAND and NOR gates. Functionality of the proposed minimalist logic circuits are verified with Synopsys TCAD simulations, which indicate that optimized gate work-functions lead to CMOS logic circuits as small as 5nm and supply voltage of 0.6V, with a power-delay product at 5 × 10 −18 J level.

— While the selection of new "backbone" device structure in the era of post-planar CMOS is open to a few candidates, FinFET and its variants show great potential in scalability and manufacturability for nanoscale CMOS. In future, as the size of channel length decrease, the necessity of low power based circuit will be increased. In nanometer regime, CMOS based circuits may not be used due to problem in its fundamental material, short channel effect (SCE) and high leakage. To achieve low power device in nanometer region, it can be obtained by utilizing alternative devices like FinFET. This paper analyses an 8T two-stage op amp realized with FinFETs. Its most important design metric that is gain and its variability are analyzed at 32-nm technology node and compared with its CMOS counterpart. This study shows that there is a considerable improvement in feature like gain and its variability due to reduced SCE of FinFET. The FinFET-based op amp emerges out to be better between the two versions of op amp. Findings of our investigation infer that FinFET technology promises to restore the silicon industry by rescuing it from the SCEs that limit device scalability faced by current bulk-CMOS technology.

—With the aggressive downscaling of the process technologies and importance of battery-powered systems, reducing leakage power consumption has become one of the most crucial design challenges for IC designers. This paper presents a device-circuit cross-layer framework to utilize fine-grained gate-length biased FinFETs for circuit leakage power reduction in the near-and super-threshold operation regimes. The impacts of Gate-Length Biasing (GLB) on circuit speed and leakage power are first studied using one of the most advanced technology nodes – a 7nm FinFET technology. Then multiple standard cell libraries using different leakage reduction techniques, such as GLB and Dual-VT, are built in multiple operating regimes at this technology node. It is demonstrated that, compared to Dual-VT, GLB is a more suitable technique for the advanced 7nm FinFET technology due to its capability of delivering a finer-grained trade-off between the leakage power and circuit speed, not to mention the lower manufacturing cost. The circuit synthesis results of a variety of ISCAS benchmark circuits using the presented GLB 7nm FinFET cell libraries show up to 70% leakage improvement with zero degradation in circuit speed in the near-and super-threshold regimes, respectively, compared to the standard 7nm FinFET cell library.

This study aims to design an optimal nano-dimensional channel of fin field
effect transistor (FinFET) on the basis of electrical characteristics and
constituent semiconductor materials (Si, GaAs, Ge, and InAs) to overcome
issues regarding the shrinking of dimensions and ensure the best performance of FinFETs. This objective has been achieved by proposing a new scaling factor, K, to simultaneously shrink the physical scaling limits of channel dimensions for various FinFETs without degrading their performance. Asimulation-based comprehensive comparative study depending on four variable parameters (length, width, oxide thickness of the channel, and scaling factor) was carried out. The influence of changing channel dimensions on the performance of each type of FinFET was evaluated according to four electrical characteristics: i) ON-state/OFF-state current (ION/IOFF) ratio, ii) subthreshold swing (SS), iii) threshold voltage, and iv) drain-induced barrier lowering. The well-known multi-gate field-effect transistor (MuGFET) simulation tool for
nanoscale MuGFET structure was utilized to conduct experimental
simulations under the considered conditions. The obtained simulation results showed that the optimal channel dimensions for the best performance of all considered FinFET types were achieved at a minimal scaling factor K=0.125 with 5 nm length, 2.5 nm width, and 0.625 nm oxide thickness of the channel.

Objective: To compare and analyse different FinFET full adder circuits by varying the temperature.
Method/Analysis: A
1-bit full adder is designed using various logic styles and the performance of these adders are compared over a range of
temperature values. 32nm FinFET Predictive Technology Model (PTM) is used for designing purpose. Various logic design
styles utilised are Complementary Metal-Oxide Semiconductor (CMOS) logic, Transmission Gate (TG) logic, Complementary
Pass-Transistor (CPTL) logic, Gate Diffusion Input (GDI) logic. Cadence Virtuoso and Spectre are used for designing and
simulation purpose, respectively.
Findings: The performance of these adders are analysed based on key circuit metrics
like static power, dynamic power, leakage power, delay and power delay product (PDP). On comparison, it is evident that
the GDI based adder consumes less leakage power. Also, the propagation delay and power delay product is very less in GDI
adder.
Novelty/Improvements: The simulation results prove that the GDI adder structure outperforms other structures in
sub nanometer technology. This advantage makes GDI technology suitable for realisation of combinational circuits. Future
research in digital circuits can be carried out by using GDI technology for designing low power and compact integrated
circuit design.

We present a comprehensive electrical performance assessment of hafnium silicate (HfSiOₓ) high-κ dielectric and titanium-nitride (TiN) metal-gate-integrated FinFET-based complementary-metal-oxide-semiconductor (CMOS) on flexible silicon on insulator. The devices were fabricated using the state-of-the-art CMOS technology and then transformed into flexible form by using a CMOS-compatible maskless deep reactive-ion etching technique. Mechanical out-of-plane stresses (compressive and tensile) were applied along and across the transistor channel lengths through a bending range of 0.5-5 cm radii for n-type and p-type FinFETs. Electrical measurements were carried out before and after bending, and all the bending measurements were taken in the actual flexed (bent) state to avoid relaxation and stress recovery. Global stress from substrate bending affects the devices in different ways compared with the well-studied uniaxial/biaxial localized strain. The global stress is dependent on the type of channel charge carriers, the orientation of the bending axis, and the physical gate length of the device. We, therefore, outline useful insights on the design strategies of flexible FinFETs in future free-form electronic applications.

We introduce novel ten (10T) and eight (8T) transistor full-adder logic gates based on recently proposed gate work-function engineering (WFE) approach. When applied to sub-10 nm Schottky-barrier (SB) independent-gate FinFETs, WFE leads to hitherto unexplored 4T and 3T XOR implementations that operate with either only one or no inverted input, respectively. The novel 4T and 3T XOR gates eliminate the need for inverted inputs provided that ambipolar I-V characteristics is shifted by the associated gate work-function in the right direction, where another conduction channel exists. Following the logic verification of the novel 4T and 3T XOR gates via TCAD simulations, we then continue to show how these novel gates can be put to use in building ultra-compact 10T and 8T full-adder circuits, which would normally require up to 20 FinFETs in conventional CMOS architecture. Simulated power-delay products of the novel full-adders show significant (⇠ 5⇥) improvement in dynamic performance attributed largely to the 50% reduction in total area as well as parasitics, at the expense of loss in noise margins. Besides the full-adders explored, the presented WFE approach could in general provide area and performance gains also for other logic building blocks that can be redesigned using SB-FinFETs.

A simulation based design evaluation is reported for SOI FinFETs at 22nm gate length. The impact of device parameters on the static power dissipation and delay of a CMOS inverter is presented. Fin dimensions such as Fin width and height are varied. For a given gate oxide thickness increasing the fin height and fin width degrades the SCEs, while improves the performance. It was found that reducing the fin thickness was beneficial in reducing the off state leakage current (IOFF), while reducing the fin height was beneficial in reducing the gate leakage current (IGATE). It was found that Static power dissipation of the inverter increases with fin height due to the increase in leakage current, whereas delay decreased with increase fin width due to higher on current. The performance of the inverter decreased with the downscaling of the gate oxide thickness due to higher gate leakage current and gate capacitance.

In this work an attempt has been made to analyze the scaling limits of Double Gate (DG) underlap and Triple Gate (TG) overlap FinFET structure using 2D and 3D computer simulations respectively. To analyze the scaling limits of FinFET structure, simulations are performed using three variables: fin-thickness, fin-height and gate-length. From 2D simulation of DG FinFET, it is found that the gate-length (L) and fin-thickness (T fin) ratio plays a key role while deciding the performance of the device. Drain Induced Barrier Lowering (DIBL) and Subthreshold Swing (SS) increase abruptly when (L/T fin) ratio goes below 1.5. So, there will be a trade-off in between SCEs and on-current of the device since on-off current ratio is found to be high at small dimensions. From 3D simulation study on TG FinFET, It is found that both fin-thickness (T fin) and fin-height (H fin) can control the SCEs. However, T fin is found to be more dominant parameter than H fin while deciding the SCEs. DIBL and SS increase as (L eff /T fin) ratio decreases. The (L eff /T fin) ratio can be reduced below 1.5 unlike DG FinFET for the same SCEs. However, as this ratio approaches to 1, the SCEs can go beyond acceptable limits for TG FinFET structure. The relative ratio of H fin and T fin should be maximum at a given T fin and L eff to get maximum on-current per unit width. However, increasing H fin degrades the fin stability and degrades SCEs.

This paper proposes a new ultra-low leakage, single-ended FinFET-based SRAM cell to improve the stability and read ON/OFF current ratio. The design employs a power gate transistor that shares the read path and main body current to improve the cell stability (SNM) by reforming the butterfly curves. In addition adjusting the tail transistor strength reduces the hold power, suppresses the variability of the cell by acting as internal feedback and improves write ability in active mode by decreasing the voltage drop over the cell. The proposed architecture redesigns the read path circuit and leverages voltage boosting for biasing, effectively eliminating access transistor leakage in read, write and hold modes. With 20 nm FinFET technology, the results show that in above threshold (near threshold) region, the proposed structure has at least 2.2× (3.5×) lower static power, with 15% (16%) lower static power variation with respect to other state-of-the-art 10T cells. Additionally, our results show that the proposed cell improves the ON/OFF current ratio by at least 20× and 6.5× compared to prior designs in above threshold and near threshold regions respectively

A simulation based design evaluation is reported for SOI FinFETs at 22nm gate length. The impact of device parameters on the static power dissipation and delay of a CMOS inverter is presented. Fin dimensions such as Fin width and height are varied. For a given gate oxide thickness increasing the fin height and fin width degrades the SCEs, while improves the performance. It was found that reducing the fin thickness was beneficial in reducing the off state leakage current (IOFF), while reducing the fin height was beneficial in reducing the gate leakage current (IGATE). It was found that Static power dissipation of the inverter increases with fin height due to the increase in leakage current, whereas delay decreased with increase fin width due to higher on current. The performance of the inverter decreased with the downscaling of the gate oxide thickness due to higher gate leakage current and gate capacitance.

This paper presents a novel low-leakage and high-writable 8T SRAM cell based on FinFET technology. This cell reduces leakage current and consequently leakage power by dynamically adjusting the back-gate of the stacked independent-gate FinFET devices. Furthermore, these stacked transistors increase the write static noise margin of the proposed cell due to their role in reducing the strength of the pull-down network of the cross-coupled inverters. The characteristics of this cell are evaluated by device/circuit level simulations using Sentaurus device TCAD device simulator at different supply voltages and in the presence of process variations. The results indicate that the proposed SRAM cell reduces the static power by 37% and 56%, respectively, while providing comparable and even higher static noise margins, as compared to the 6T and 8T FinFET-based SRAM cells.

A 2-Dimensional (2D) FinFET simulation is presented in this study.The simulation studies are conducted based on electrical parameters such as surface potential, electric field, transfer characteristics, threshold voltage and sub threshold swing using nanohubmultiple gate field effect transistors(MUGFET) simulator. These characterization studies are performed to investigate the performance of FinFETs based on different channel width and show a better performance for lower channel width withthreshold voltage shift of 0.2 V.Further, the transfer characteristics for the device are compared with silicon dioxide and titanium oxide, as oxide material for different drain biases. Findings have shown that the device with titanium oxide as dielectric material performs better compared to silicon dioxide counterpart, where the on-statecurrent increased with decreased off current.

Germanium (Ge) is envisioned as a suitable channel candidate for field-effect transistors (FET). Properties of Ge such as high carrier mobility, compatibility with Si and adaptability with highk materials makes it comparable to silicon. This paper presents a detailed design of a 30 nm Ge based FinFET by parameter optimization using Silvaco software. Poisson and Schrodinger equation is used to come up with an analytical quantum model. The quantum model is developed based on theory of a double gate (DG) FET but the final design is a tri-gate (TG) device since they are more scalable. The quantum attributes of DG MOSFET are acquired by adopting the coupled Poisson-Schrodinger equation with the aid of the variational approach. The ratio of channel length (L C) to fin height (H f in) to fin thickness (t f in) is 4:2:1. The channel length is taken as the gate length (L G) although they are slightly differ mathematically due to side diffusion of the implanted ions. Simulation results show that physical parameters such as dimensions influence electrical characteristics of the device such as threshold voltage (V T H). Much focus is on optimization of the on/off current ratio (I ON /OF F) and V T H performances. I ON /OF F ≈ 10 6 is achieved at carrier concentration in the range 1 × 10 18 ≤ n d ≤ 1.22 × 10 18 and in this scenario, V T H = 0.4V. Systematical investigation is presented using I-V characteristics to demonstrate the sensitivity or how critical design parameters of Ge FinFET are to the device's figure of merits. Device performs well at low voltages but breaks down at higher drain voltages (V DS ≥ 4V). Gate source voltages (V GS) range between 0.05V≤ V GS ≤ 1V and conductance is dependent on it. Effects of DIBL, which is around 0.031, and velocity saturation are studied to determine how they can be suppressed during the design process.

An extensive analysis of sub-10-nm logic building blocks utilizing ultracompact logic gates based on recently proposed gate workfunction engineering (WFE) approach is provided. WFE sets the WF in the contacts as well as two independent gates of an ambipolar Schottky-barrier (SB) FinFET to alter the threshold of two channels, as a unique leverage to modify the logic functionality out of a single transistor. Thus, a single transistor (1T) CMOS pass-gate, 2T NAND and NOR gates as well as 3T or 4T XOR gates with substantial reduction in overall area (50%) and power (up to $\times 10$ ) dissipation can be implemented. To harness this potential and illustrate the capabilities of these compact ambipolar transistors, novel logic building blocks, including 6T multiplexer, 8T full-adder, 4T latch, 6T D-type flip-flop, and 4T AND-OR-invert (AOI) gates, are developed. Besides the logic verification using 7-nm devices, the dynamic performance of the proposed logic circuits is also analyzed. The ...

A comprehensive simulation study has been conducted to show fine-grain reconfigurability in CMOS circuits using work-function engineering (WFE) on Schottky Barrier (SB) FinFETs for sub-10 nm gate length. The study has three subsections. First, two-transistor (2T) & 4T AOI (and-or-invert)/ OAI (or-and-invert) gates with select bits that allow multiple logic functions are introduced. Secondly, the use of WFE to create ultra-compact reconfigurable logic circuits of fundamental operations (0,1,OR, AND,NAND,NOR,XOR) are explored via novel 2T, 3T and 4T gates. These circuits include one or two select bits that are capable of commanding up to four functions with two inputs. To further illustrate the potential of WFE for reconfigurable logic, novel multi-stage circuits such as compact full-adders are also modelled via TCAD simulations. Power×delay product (PDP) figures and DC gain of the proposed gates are quantified and compared against the CMOS designs with similar functionality. Finally,...

Conventionally polysilicon is used in MOSFETs for gate material. Doping of polysilicon and thus changing the workfunction is carried out to change the threshold voltage. Additionally polysilicon is not favourable as gate material for smaller dimensional devices because of its high thermal budget process and degradation due to the depletion of the doped polysilicon, thus metal gate is preferred over polysilicon. Control of workfunction in metal gate is a challenging task. The use of metal alloys as gate materials for variable gate workfunction has been already reported in literature. In this work various threshold voltage techniques has been analyzed and a novel aligned dual metal gate technique is proposed for threshold voltage control in FinFETs.

We introduce novel ten (10T) and eight (8T) transistor full-adder logic gates based on recently proposed gate work-function engineering (WFE) approach. When applied to sub-10 nm Schottky-barrier (SB) independent-gate FinFETs, WFE leads to hitherto unexplored 4T and 3T XOR implementations that operate with either only one or no inverted input, respectively. The novel 4T and 3T XOR gates eliminate the need for inverted inputs provided that ambipolar I-V characteristics is shifted by the associated gate work-function in the right direction, where another conduction channel exists. Following the logic verification of the novel 4T and 3T XOR gates via TCAD simulations, we then continue to show how these novel gates can be put to use in building ultra-compact 10T and 8T full-adder circuits, which would normally require up to 20 FinFETs in conventional CMOS architecture. Simulated power-delay products of the novel full-adders show significant (⇠ 5⇥) improvement in dynamic performance attri...

In this paper, the impact of process/technology co-optimization on silicon-on-insulator (SoC) performance using detailed 3-D process/device simulations has been studied for nanoscale FinFET devices. We investigated challenges in FinFET device optimization and scaling while using standard ion implantation process for both overlap and underlap designs. Moreover, an implant-free (IF) complementary metal–oxide–semiconductor process is discussed for better scalability with improved performance. FinFETs designed using this IF process shows a "~2 times" improvement in static random-access memory and digital input/output performance. Additionally, a modification to the IF process is proposed, which further helps in achieving an improved logic and analog performance for overall SoC development.

An extensive analysis of sub-10 nm logic building blocks utilizing ultra-compact logic gates based on recently proposed gate workfunction engineering (WFE) approach is provided. WFE sets the workfunction in the contacts as well as two independent gates of an ambipolar Schottky-Barrier (SB) FinFET to alter the threshold of two channels, as a unique leverage to modify the logic functionality out of a single transistor. Thus, a single transistor (1T) CMOS pass-gate, 2T NAND and NOR gates as well as 3T or 4T XOR gates with substantial reduction in overall area (50%) and power (up to ×10) dissipa-tion can be implemented. To harness this potential and illustrate the capabilities of these compact ambipolar transistors, novel logic building blocks including 6T multiplexer, 8T full-adder, 4T latch, 6T D-type flip-flop and 4T and-or-invert (AOI) gates are developed. Besides the logic verification using 7 nm devices, dynamic performance of the proposed logic circuits are also analyzed. The comparative simulation study shows that WFE in independent-gate SB-FinFETs can lead to absolutely minimalist CMOS logic blocks without significant degradation to overall power-delay product (PDP) performance.

This paper investigates the leakage current, static noise margin (SNM), delay and energy consumption of a 6 transistor FinFET based static random-access memory (SRAM) cell due to the variation in design and operating parameters of the SRAM cell. The SRAM design and operating parameters considered in this investigation are transistor sizing, supply voltage, word-line voltage, temperature and PFET and NFET back gate biasing. This investigation is performed using a 11nm FinFET shorted gate and low power technology models. Based on the investigation results, we propose a robust 6 transistor SRAM cells with optimized performance using shorted gate and independent gate low power FinFET models. By optimizing the design parameters of the cell, the shorted-gate design shows an improvement of read SNM of 261.56mV and an improvement of hold SNM of 87.68mV when compared to a shorted-gate cell with standard design parameters. The low-power design shows an improvement of read SNM of 146.18mV and a marginal decrease in hold SNM of 22.84mV when compared to a low-power cell with standard design parameters. Both the cells with the new optimized design parameters are shown to improve the overall SNM of the cells with minimal impact on the subthreshold leakage currents, performance and energy consumption.

Examples of compact reconfigurable logic gates utilizing Schottky-barrier (SB) FinFETs that take advantage of workfunction engineering (WFE) are provided. When applied to independent-gate SB-FinFETs, WFE has been shown to be capable of forming minimalist two transistor (2T) NAND,NOR and XOR logic gates that can lower power and area requirements by a factor of (5×) and (2×), respectively, with similar PDP figures as conventional FinFET logic circuits. Here, we introduce a new class of work-function engineered reconfigurable logic gates that can implement multiple logic functionality. Examples of reconfigurable gates include 2T gates that can implement (1-NOR-NOR-NAND) and (0-NAND-NAND-NOR) output functions as well as a 4T gate (1-AB’-A’B-OR) that can provide four distinct functional outputs with only two select bits. TCAD simulations are used to verify logic operation and disclose dynamic performance of the proposed ultra-compact reconfigurable circuits. Optimized for maximum reconfigurability, the PDP figures are higher by an order of magnitude as compared to the static logic circuits built using the same FinFET architecture. The fine-grain and ultra-fast reconfigurability of these circuits would be especially welcomed for logic-locking and obfuscation operations used to enhance hardware security in IC design.

We introduce novel ten (10T) and eight (8T) transistor full-adder logic gates based on recently proposed gate work-function engineering (WFE) approach. When applied to sub-10 nm Schottky-barrier (SB) independent-gate FinFETs, WFE leads to hitherto unexplored 4T and 3T XOR implementations that operate with either only one or no inverted input, respectively. The novel 4T and 3T XOR gates eliminate the need for inverted inputs provided that ambipolar I-V characteristics is shifted by the associated gate work-function in the right direction, where another conduction channel exists. Following the logic verification of the novel 4T and 3T XOR gates via TCAD simulations, we then continue to show how these novel gates can be put to use in building ultra-compact 10T and 8T full-adder circuits, which would normally require up to 20 FinFETs in conventional CMOS architecture. Simulated power-delay products of the novel full-adders show significant (⇠ 5⇥) improvement in dynamic performance attri...

Dynamic-adjusting threshold-voltage scheme (DATS) for the design of an independent-gate
(IG)-mode fin-type field-effect transistor (FinFET) circuit is discussed in this work. . DATS
makes use of the intrinsic advantage of the IG-mode FinFET to adjust the threshold of the
front gate with the back-gate bias adaptively according to the operating frequency.
Consequently, the power consumption, especially leakage power of the circuit, would be
reduced effectively without circuit performance deterioration. By further comparing the
circuits where the DATS scheme is employed with the circuits that do not adopt the scheme,
the power optimization levels with different path delays in different operating frequency
ranges are discussed in detail. A design instance of DATS based on digitally controlled phaselocked
loop is implemented with an ASAP 7-nm FinFET model. Simulation results illustrate
that by employing DATS the power reduction could be up to 30% in the best case.

Examples of compact reconfigurable logic gates utilizing Schottky-barrier (SB) FinFETs that take advantage of workfunction engineering (WFE) are provided. When applied to independent-gate SB-FinFETs, WFE has been shown to be capable of forming minimalist two transistor (2T) NAND,NOR and XOR logic gates that can lower power and area requirements by a factor of (5×) and (2×), respectively, with similar PDP figures as conventional FinFET logic circuits. Here, we introduce a new class of work-function engineered reconfigurable logic gates that can implement multiple logic functionality. Examples of reconfigurable gates include 2T gates that can implement (1-NOR-NOR-NAND) and (0-NAND-NAND-NOR) output functions as well as a 4T gate (1-AB'-A'B-OR) that can provide four distinct functional outputs with only two select bits. TCAD simulations are used to verify logic operation and disclose dynamic performance of the proposed ultra-compact reconfigurable circuits. Optimized for maximum reconfigurability, the PDP figures are higher by an order of magnitude as compared to the static logic circuits built using the same FinFET architecture. The fine-grain and ultra-fast reconfigurability of these circuits would be especially welcomed for logic-locking and obfuscation operations used to enhance hardware security in IC design. Reconfigurable hardware can provide unique solutions to cyber-physical security problems that are not only harder to avoid, attack or reverse-engineer but also dynamic in nature with characteristics that can adapt to new threats and different usage scenarios. [1], [2]. Doing so requires reconfigurable system blocks, locks and redundant states for obfuscation, which in conventional CMOS circuits demands either additional power and area resources, or significant increase in complexity of the architecture as well as the time for reprogramming. For instance, modern FPGAs can offer very elaborate solutions for fine-grain (gate-level) reconfigurability, however they cannot be reprogrammed at short (every second) intervals and consume significantly more power [3]. It is desirable to create a secure hardware platform that can respond to threats instantly without substantial resources or complexity, quickly switching between a very large permutations of possible logic pathways. This would not only minimize any interruption to normal operation, it would also provide a dynamic logic-locking options that cannot be probed or scanned with practical means. In the present paper, we introduce several reconfigurable logic gates based on recently-proposed ambipolar Schottky-barrier (SB) FinFETs that can be readily and easily programmed at the gate level without additional resources in terms of power, area or clock-cycles. Fig. 1. Work-function engineered independent-gate SB-FinFETs [4] are used as building blocks of the reconfigurable logic gates. a) Simplified device structure and band diagram; b) ON/OFF characteristic of 1T pass-gate and the corresponding e/h current densities, c) Ambipolar I-V characteristics of the 7 nm SB-FinFET as a function of contact work-function and d) hi/low threshold ambipolar SB-FinFETs based on changes in gate workfunction To achieve such powerful level of reconfigurability, SB-FinFETs utilize a novel gate workfunction engineering (WFE) approach [4], which results in ultra-compact XOR/NAND/NOR logic gates with significant (∼50%) reduction in area and 5 to 10 times lower power. This is further facilitated with independent-gate configuration that doubles the number of inputs for FinFETs and enhances the impact of WFE, leading to unique reconfigurable gates as will be explored in the following sections.

—Computer systems and micro architecture researchers have proposed using hardware data compression units within the memory hierarchies of microprocessors in order to improve performance, energy efficiency, and functionality. However, most past work, and all work on cache compression, has made unsubstantiated assumptions about the performance, power consumption, and area overheads of the proposed compression algorithms and hardware. In this work, I present a lossless compression algorithm that has been designed for fast on-line data compression, and cache compression in particular. The algorithm has a number of novel features tailored for this application, including combining pairs of compressed lines into one cache line and allowing parallel compression of multiple words while using a single dictionary and without degradation in compression ratio. We reduced the proposed algorithm to a register transfer level hardware design, permitting performance, power consumption, and area estimation.

Abstract A novel computationally efficient approach for simulation of quantum transport in nanoscale devices is proposed. The idea is based on partial coupling between the modes of the nanoscale device. The proposed approach, termed Partial-Coupled Mode Space (PCMS), is applied to the double-gate MOSFETs and device targets from the ITRS roadmap were simulated. A Comparison with the fully Coupled-Mode Space (CMS) was carried out. The PCMS reduces more than 65% of the computational burden while an accuracy of ...

<jats:p>Germanium (Ge) is envisioned as a suitable channel candidate for field-effect transistors (FET). Properties of Ge such as high carrier mobility, compatibility with Si and adaptability with high-k materials makes it comparable to silicon. This paper presents a detailed design of a 30 nm Ge based FinFET by parameter optimization using Silvaco software. Poisson and Schrodinger equation is used to come up with an analytical quantum model. The quantum model is developed based on theory of a double gate (DG) FET but the final design is a trigate (TG) device since they are more scalable. The quantum attributes of DG MOSFET are acquired by adopting the coupled Poisson–Schrodinger equation with the aid of the variational approach. The ratio of channel length (<jats:italic>L</jats:italic><jats:italic><jats:sub>C</jats:sub></jats:italic>) to fin height (<jats:italic>H</jats:italic><jats:italic><jats:sub>fin</jats:sub></jats:italic>) to fin thickness (<jats:italic>t</jats:italic><jats:italic><jats:sub>fin</jats:sub></jats:italic>) is 4:2:1. The channel length is taken as the gate length (<jats:italic>L</jats:italic><jats:italic><jats:sub>G</jats:sub></jats:italic>) although they are slightly differ mathematically due to side diffusion of the implanted ions. Simulation results show that physical parameters such as dimensions influence electrical characteristics of the device such as threshold voltage (<jats:italic>V</jats:italic><jats:italic><jats:sub>TH</jats:sub></jats:italic>). Much focus is on optimization of the on/off current ratio (<jats:italic>I</jats:italic><jats:italic><jats:sub>ON</jats:sub></jats:italic>/<jats:italic><jats:sub>OFF</jats:sub>)</jats:italic> and <jats:italic>V</jats:italic><jats:italic><jats:sub>TH</jats:sub></jats:italic> performances. <jats:italic>I</jats:italic><jats:italic><jats:sub>ON</jats:sub></jats:italic>/<jats:italic><jats:sub>OFF</jats:sub></jats:italic><jats:italic>≈ </jats:italic>10<jats:sup>6</jats:sup> is achieved at carrier concentration in the range 1 <jats:italic>× </jats:italic>10<jats:sup>18</jats:sup><jats:italic>≤ </jats:italic><jats:italic>n</jats:italic><jats:italic><jats:sub>d</jats:sub></jats:italic><jats:italic>≤ </jats:italic>1<jats:italic>.</jats:italic>22 <jats:italic>× </jats:italic>10<jats:sup>18</jats:sup> and in this scenario, <jats:italic>V</jats:italic><jats:italic><jats:sub>TH</jats:sub></jats:italic> = 0<jats:italic>.</jats:italic>4V . Systematical investigation is presented using IV characteristics to demonstrate the sensitivity or how critical design parameters of Ge FinFET are to the device's figure of merits. Device performs well at low voltages but breaks down at higher drain voltages (<jats:italic>V</jats:italic><jats:italic><jats:sub>DS</jats:sub></jats:italic><jats:italic>≥ </jats:italic>4V). Gate source voltages (<jats:italic>V</jats:italic><jats:italic><jats:sub>GS</jats:sub></jats:italic>) range between 0<jats:italic>.</jats:italic>05V<jats:italic>≤ </jats:italic><jats:italic>V</jats:italic><jats:italic><jats:sub>GS </jats:sub></jats:italic><jats:italic>≤ </jats:italic>1V and conductance is dependent on it. Effects of DIBL, which is around 0.031, and velocity saturation are studied to determine how they can be suppressed during the design process.</jats:p>

This paper presents a systematic study to show the impact of channel length on the Analog/RF performances of gate stack (GS) silicon on insulator (SOI) architecture. The downscaling of channel length becomes the biggest challenge to maintain higher speed, low power and better electrostatic integrity for each generation. This investigation is done to find out the potential of the channel length in view of analog and RF performance measures of sub-100nm GS-double gate (DG) MOSFETs. The threshold voltage (Vth) is made constant by tuning the gate metal work function while downscale the channel length (L). The impact of channel length variation on subthreshold slope (SS), drain induced barrier lowering (DIBL), transconductance (gm), output conductance (gd), early voltage (VEA), transconductance generation factor (TGF), intrinsic gain (AV), cut-off frequency (fT), transconductance frequency product (TFP), gain frequency product (GFP) and gain transconductance frequency product (GTFP) are ...

A novel computationally efficient approach for simulation of quantum transport in nanoscale devices is proposed. The idea is based on partial coupling between the modes of the nanoscale device. The proposed approach, termed Partial-Coupled Mode Space (PCMS), is applied to the double-gate MOSFETs and device targets from the ITRS roadmap were simulated. A Comparison with the fully Coupled-Mode Space (CMS) was carried out. The PCMS reduces more than 65% of the computational burden while an accuracy of ...

This paper investigates the leakage current, static noise margin (SNM), delay and energy consumption of a 6 transistor FinFET based static random-access memory (SRAM) cell due to the variation in design and operating parameters of the SRAM cell. The SRAM design and operating parameters considered in this investigation are transistor sizing, supply voltage, word-line voltage, temperature and PFET and NFET back gate biasing. This investigation is performed using a 11nm FinFET shorted gate and low power technology models. Based on the investigation results, we propose a robust 6 transistor SRAM cells with optimized performance using shorted gate and independent gate low power FinFET models. By optimizing the design parameters of the cell, the shorted-gate design shows an improvement of read SNM of 261.56mV
and an improvement of hold SNM of 87.68mV when compared to a shorted-gate cell with standard design parameters. The low-power design shows an improvement of read SNM of 146.18mV and a marginal decrease in hold SNM of 22.84mV when compared to a low-power cell with standard design parameters. Both the cells with the new optimized design parameters are shown to improve the overall SNM of the cells
with minimal impact on the subthreshold leakage currents, performance and energy consumption.