Verilog to Routing -- Open Source CAD Flow for FPGA Research

This is a robotic package for an algorithm for visual teach and repeat

Signal converter from Sony Beta 14-pin (K-type) camera to EIAJ 10-pin (J-type) VTR

Virtual Telepresence Robot

This Repo is a part of a 5-Day Workshop conducted by VLSI System Design (VSD) and the contents are divided Day wise for better understanding.

This is a Serial VTR emulator, running under Python. It simulates a VTR connected to a serial port of the computer.

FPGA acceleration vector matrix multiplication

Huawei P10 specs, notes, infos for custom ROM dev