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System Verilog support is broken due to compilation error in F4PGA plugin
#2821
opened Nov 21, 2024 by
MohamedElgammal
Wire lookahead runtime scales poorly with number of switch/segment types
#2811
opened Nov 15, 2024 by
petergrossmann21
SDC Parsing causes assertion error for specific netlist sweeping option combination
#2809
opened Nov 15, 2024 by
petergrossmann21
Comparing performance/quality trade-off of SPEC and VTR random number generators.
#2798
opened Nov 3, 2024 by
soheilshahrouz
[Prepacker] Pack Molecule Data Structure Clarity
#2791
opened Oct 30, 2024 by
AlexandreSinger
1 of 9 tasks
Change in path from input to output place file causes digest error.
#2783
opened Oct 18, 2024 by
petergrossmann21
Optimize run time and memory footprint to build the choke point data structures in routing
#2782
opened Oct 18, 2024 by
vaughnbetz
Unexpected High Gain Causes Unrelated Blocks to Be Added to Clusters
#2763
opened Oct 10, 2024 by
WindFrank
VPR error when trying to compile my design generated using PRGA
#2760
opened Oct 5, 2024 by
polarbearsrock
Turn on choke point analysis in the router by default, and make help etc. more user-friendly
#2750
opened Sep 27, 2024 by
vaughnbetz
5 tasks
[Packer] Load The ClusteredNetlist Directly From The ClusterLegalizer
VPR
VPR FPGA Placement & Routing Tool
#2731
opened Sep 20, 2024 by
AlexandreSinger
[ClusterLegalizer] Code Cleanups
VPR
VPR FPGA Placement & Routing Tool
#2730
opened Sep 20, 2024 by
AlexandreSinger
6 tasks
[Packer] Setting Higher Target Pin Utilization When Regions are Full
VPR
VPR FPGA Placement & Routing Tool
#2729
opened Sep 20, 2024 by
AlexandreSinger
Packing Devices from Two Separate Parts of a Netlist into a Single CLB
#2726
opened Sep 17, 2024 by
WindFrank
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