risc-v
Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use. A number of companies are offering or have announced RISC-V hardware, open source operating systems with RISC-V support are available and the instruction set is supported in several popular software toolchains.
Notable features of the RISC-V ISA include a load–store architecture, bit patterns to simplify the multiplexers in a CPU, IEEE 754 floating-point, a design that is architecturally neutral, and placing most-significant bits at a fixed location to speed sign extension. The instruction set is designed for a wide range of uses. The base instruction set has a fixed length of 32-bit naturally aligned instructions, and the ISA supports variable length extensions where each instruction could be an any number of 16-bit parcels in length. Subsets support small embedded systems, personal computers, supercomputers with vector processors, and warehouse-scale 19 inch rack-mounted parallel computers.
Here are 103 public repositories matching this topic...
OpenSource GPU, in Verilog, loosely based on RISC-V ISA
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Jun 21, 2024 - SystemVerilog
VeeR EH1 core
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May 29, 2023 - SystemVerilog
VeeR EL2 Core
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Nov 13, 2024 - SystemVerilog
Vector processor for RISC-V vector ISA
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Oct 19, 2020 - SystemVerilog
RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards
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Nov 14, 2018 - SystemVerilog
A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
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Sep 4, 2024 - SystemVerilog
Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
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Nov 2, 2024 - SystemVerilog
Advanced Architecture Labs with CVA6
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Jan 16, 2024 - SystemVerilog
A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
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Jan 31, 2022 - SystemVerilog
Открытый ознакомительный курс "Введение в функциональную верификацию RISC-V ядер"
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Sep 19, 2024 - SystemVerilog
A small RISC-V core (SystemVerilog)
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Aug 26, 2019 - SystemVerilog
Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door is wide open for backdoor scrutiny, be it related to RTL, embedded, build, bitstream or any other aspect of design and delivery package. Bujrum!
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Nov 12, 2024 - SystemVerilog
DUTH RISC-V Superscalar Microprocessor
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Oct 23, 2024 - SystemVerilog