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[FEA] Support for half-float mixed precise in brute-force #2382

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merged 20 commits into from
Aug 22, 2024
Merged

[FEA] Support for half-float mixed precise in brute-force #2382

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0780518
[FEA] Support for half-float mixed precise in brute-force
rhdong Jul 17, 2024
0e9e70b
Merge branch 'branch-24.08' into half_knn
rhdong Jul 17, 2024
3dd5fdf
recover the test cases
rhdong Jul 17, 2024
eb3b8a6
try to fix sddmm error in conda-cpp-tests
rhdong Jul 18, 2024
60ff874
check sparse
rhdong Jul 19, 2024
6103fd1
fix the Floating-point exception
rhdong Jul 19, 2024
d744d59
Merge remote-tracking branch 'origin/branch-24.08' into half_knn
rhdong Jul 19, 2024
efec888
conditionally skip sddmm test cases
rhdong Jul 19, 2024
a55f100
conditionally skip sddmm test cases(2nd try)
rhdong Jul 22, 2024
920997f
half2float -> to_float
rhdong Jul 22, 2024
f2f21c4
Merge branch 'branch-24.08' into half_knn
rhdong Jul 23, 2024
43ee640
CI fix caused by half2float -> to_float
rhdong Jul 23, 2024
11a9988
Merge branch 'branch-24.10' into half_knn
rhdong Jul 26, 2024
aa6da25
Merge branch 'branch-24.10' into half_knn
rhdong Aug 1, 2024
3d8b7ca
update masked_matmul to support mixed precision
rhdong Aug 1, 2024
34dbde8
fix CI fail by skipping low version cuSparse
rhdong Aug 1, 2024
10e5204
fix: illegal instruction by `masked_matmul` on V100 with a dim not mu…
rhdong Aug 9, 2024
4046bf8
Merge branch 'branch-24.10' into half_knn
rhdong Aug 13, 2024
1ed4801
[Fix] bug of `masked_matmul` on non-2-power of `num_cols`
rhdong Aug 13, 2024
4d55c57
[Fix] compilation error of `gemm` & `transpose` under cuml
rhdong Aug 21, 2024
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try to fix sddmm error in conda-cpp-tests
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@rhdong
rhdong committed Jul 18, 2024
commit eb3b8a6bdac021adf7fd18284a5eea05e195971c
21 changes: 0 additions & 21 deletions cpp/include/raft/sparse/detail/cusparse_wrappers.h
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Expand Up @@ -269,27 +269,6 @@ inline cusparseStatus_t cusparsecreatecsr(cusparseSpMatDescr_t* spMatDescr,
CUSPARSE_INDEX_BASE_ZERO,
CUDA_R_64F);
}
template <>
inline cusparseStatus_t cusparsecreatecsr(cusparseSpMatDescr_t* spMatDescr,
int64_t rows,
int64_t cols,
int64_t nnz,
int64_t* csrRowOffsets,
int64_t* csrColInd,
half* csrValues)
{
return cusparseCreateCsr(spMatDescr,
rows,
cols,
nnz,
csrRowOffsets,
csrColInd,
csrValues,
CUSPARSE_INDEX_64I,
CUSPARSE_INDEX_64I,
CUSPARSE_INDEX_BASE_ZERO,
CUDA_R_16F);
}
/** @} */
/**
* @defgroup cusparse CreateDnVec operations
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