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Commits on Jan 21, 2024

• formatting and comments on some verilog

  

  Isaiah Becker-Mayer

  authored and

  Isaiah Becker-Mayer

  committed
  69aba20

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Commits on Jan 14, 2024

• change path to absolute

  ibeckermayer

  committed
  677a559

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Commits on Oct 5, 2020

• magically got another 32k of ROM back. I think maybe the timing constraints I had in before were causing it to complain. That or luck of the draw on placement/routing, tbd in future syntheses

  ibeckermayer

  committed
  7dda98a

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• Screen is officially twerking. The issue now is that the API is jank. I forgot to account for the fact that we can only load a 15-digit binary constant into A register, because the first bit of any…

  Show description for 0a5e352
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  0a5e352

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• Fixing tests, the stupid fucking formatter bug messed up the verilog files but not worth tinkering with right now. The tests are working.

  ibeckermayer

  committed
  2e73253

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Commits on Oct 4, 2020

• wrote a program to write to screen, now need to copy over and attach the hardware components

  ibeckermayer

  committed
  19f6dd8

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Commits on Oct 3, 2020

• Needed to hack the rom down to 32k to meet the timing constraints but the dual port BRAM appears to be functioning properly

  ibeckermayer

  committed
  4421ecc

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Commits on Sep 24, 2020

• married RAM and ROM, now need to see if I can make them dualport without blowing up the synthesis/impl

  ibeckermayer

  committed
  20bcd27

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• formatting and adding if statement to ramrom

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  committed
  5ce162d

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• make ram size a function of addr_width

  ibeckermayer

  committed
  a920406

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• reverting back to unclocked ROM because for some reason that triggers some optimization that I can't track down, and ROM dissapears

  ibeckermayer

  committed
  bcfa81f

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Commits on Sep 23, 2020

• switching to clocked ROM

  ibeckermayer

  committed
  203b4f2

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Commits on Sep 22, 2020

• VgaTests were not as promised, changing to a different design

  ibeckermayer

  committed
  baeae53

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Commits on Sep 20, 2020

• adding clock constraint so that timing analysis shuts up

  ibeckermayer

  committed
  2a9b52e

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Commits on Sep 14, 2020

• switches RAM.v from async to sync, so it's synthesized as BRAM to save space on device

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  committed
  087c22e

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Commits on Aug 19, 2020

• BOOM BABY! ITS FUCKING WORKING AS FUCK! Realized that I mistakenly have 116C in there rather than 1234. But otherwise it's fucking correct. Holy shit

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  committed
  acf66fe

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• trying to create bitfile with this design, however its giving us the following error: [DRC UTLZ-1] Resource utilization: LUT as Distributed RAM over-utilized in Top Level Design (This design requir…

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  cf39110

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Commits on Aug 16, 2020

• Moved Hex_to_7_Seg* into the Hack/src directory. Added Hex_to_7_Seg to Hack, and wired it up in such a way that the 7 segment display will show us whatever's in whatever RAM address is currently be…

  Show description for 2dbb5c6
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  2dbb5c6

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Commits on Aug 12, 2020

• resetting RAM to try another debugging strategy

  ibeckermayer

  committed
  21098b8

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• adding full path for tv files to get things to twerk properly in Vivado

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  99e8991

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Commits on Mar 16, 2020

• moving bitfile to proper location

  ibeckermayer

  committed
  fb9f1b9

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• added 7 segment display driver to be used as temporary "screen"

  ibeckermayer

  committed
  e6a4ce4

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• messing with timing and constraint files

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  335d292

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• fixed a bug

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  1548858

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• bitstream generated

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  ee3941f

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• adding logic for using all 4 of the seven seg digits

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  32c30da

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• made modifications to verilog files per the syntax checker and committing bitstream file to try and ipmlement on the fpga via usb

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  1640569

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• first attempt at 7 seg with verilog

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  9a2b1b0

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• Merge branch 'add_screen_and_kb_memory_map'

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  af679e3

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• added dummy var for ROM input for synthesis

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  5f56e2b

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• attempt at screen output port on RAM

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  28acd67

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Commits on Dec 22, 2019

• restructuring directory

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  3a62eb1

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