forked from aws/aws-fpga
-
Notifications
You must be signed in to change notification settings - Fork 3
Commit
This commit does not belong to any branch on this repository, and may belong to a fork outside of the repository.
- Loading branch information
Showing
129 changed files
with
15,802 additions
and
1,430 deletions.
There are no files selected for viewing
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,4 @@ | ||
| [submodule "SDAccel/examples/xilinx"] | ||
| path = SDAccel/examples/xilinx | ||
| url = https://github.com/Xilinx/SDAccel_Examples.git | ||
| branch = 2017.1 |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,5 @@ | ||
| # Known Restrictions | ||
| * OpenCL support is limited to OpenCL 1.0 core specifications. | ||
| * For complete list of the supported OpenCL APIs, please refer to [Appendix B in Xilinx' UG1023](https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_1/ug1023-sdaccel-user-guide.pdf) | ||
| * On device - only Global memory (i.e. external DRAM) is supported. | ||
| * Shared Virtual Memory (SVM) is not supported. |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,91 @@ | ||
| # Frequently Asked Questions (FAQ) | ||
|
|
||
| This section lists issues/perceived issue and their associated investigations or solutions. | ||
|
|
||
| ## Q: What can we investigate when xocc fails with a path not meeting timing? | ||
| A: An example is WARNING: [XOCC 60-732] Link warning: One or more timing paths failed timing targeting <ORIGINAL_FREQ> MHz for <CLOCK_NAME>. The frequency is being automatically changed to <NEW_SCALED_FREQ> MHz to enable proper functionality. | ||
| 1. Generally speaking, lowering the clock will make the design functional in terms of operations (since there will not be timing failures) but the design might not operate at the performance needed due this clock frequency change. We can review what can be done. | ||
| 1. If CLOCK_NAME is `kernel clock 'DATA_CLK'` then this is the clock that drives the kernels. Try reduce kernel clock frequency see --kernel_frequency option to xocc in [latest SDAccel Environment User Guide] | ||
| 1. If CLOCK_NAME is `system clock 'clk_main_a0'` then this is the clock clk_main_a0 which drives the AXI interconnect between the AWS Shell and the rest of the platform (SDAccel peripherals and user kernels). Using --kernel_frequency as above does not have any direct effect but might have side effect in changing the topology/placement of the design and improve this issue. | ||
| 1. If OCL/C/C++ kernels were also used, investigate VHLS reports / correlate with kernel source code to see if there are functions with large number of statements in basic block, examples: might have unrolled loops with large loop-count, might have a 100++ latency; the VHLS runs and log files are located in the directory named `_xocc*compile*` | ||
| 1. Try `xocc -O3` to run bitstream creation process with higher efforts. | ||
| 1. Open vivado implementation project ```vivado `find -name ipiimpl.xpr` ``` to analyze the design; needs Vivado knowledge; see [UltraFast Design Methodology Guide for the Vivado][latest UG949] | ||
|
|
||
| ## Q: xocc issues message WARNING: [XOCC 204-69] Unable to schedule ...due to limited memory ports. | ||
| A: This may lower the performance of the implementation. | ||
| Details on this are provided in [Debug HLS Performance: Limited memory ports] | ||
|
|
||
| ## Q: xocc fails due to routing/resource overflow | ||
| A: Examine utilization reports. If OCL/C/C++ kernels were also used, look into the source code for excessive unroll happening. | ||
|
|
||
| ## Q: How do I open the design as a Vivado project (.xpr)? | ||
| A: There are 2 vivado project files: | ||
| 1. CL Design - from command line: ```vivado `find -name ipiprj.xpr\` ``` to see the connectivity of the created design | ||
| 1. Implementation project - from command line: ```vivado `find -name ipiimpl.xpr\` ``` to analyze the design in the place and routing design phases. For an additional Vivado Design reference, see [UltraFast Design Methodology Guide for the Vivado][latest UG949] | ||
|
|
||
| ## Q: What should I do if FPGA instance execution gets the wrong results or gets stuck? | ||
| A: | ||
| 1. Verify hw_emu works as expected. Using less data in hw_emu | ||
| 1. Add assert where run fails and check same conditions for hw_emu | ||
| 1. See "Chapter 8 - Debugging Applications in the SDAccel Environment" in [latest SDAccel Environment User Guide] | ||
|
|
||
| ## Q: Host code failed to link? | ||
| A: | ||
| 1. Is the code linking to *.so libs and are they setup correctly on the compiler command line argument | ||
| - Note, there has been issues reported where -ldl or -lxilinxopencl needed to be put as the last argument of the comman line for the compiler; try linking on the command line and see if moving the -l options corrects the issue. | ||
| 1. Check if LD_LIBRARY_PATH is setup correctly | ||
|
|
||
| ## Q: sw_emu passes but hw_emu fails | ||
| A: | ||
| 1. arrow down failure: what mismatches, only LSB bits different? | ||
| 1. Differences due to floating point? | ||
| 1. Run valgrind on executable to assert no seg faults or out of bounds accesses | ||
| 1. Have a reduced testcase data size if hw_emu takes too long | ||
| 1. Have sdaccel.ini configured with [Emulation] section using launch_waveform=gui or batch to generate waveform for analysis; see "Application Timeline" in [latest SDAccel Environment User Guide] | ||
|
|
||
| ## Q: Bitstream creation fails to create design less that 60 MHz? | ||
| A: SDAccel flow does not allow clocks running less that 60 MHz kernel clock, therefore, you will need to debug further using [HLS Debug suggestions](./docs/SDAccel_HLS_Debug.md) | ||
|
|
||
| ## Q: Using the .xcp file generated from xocc results in an error | ||
| A: | ||
| 1. Raw xclbin (.xcp file) from xocc is not usable | ||
| 1. Directly using the .xcp file without conversion to .xclbin file will result in an error - Error: ... invalid binary | ||
| 1. See [Instructions on how to create AFI and subsequent execution process](../README.md#create-an-amazon-fpga-image-afi-for-your-kernel) | ||
|
|
||
|
|
||
| # Additional Resources | ||
|
|
||
| The [AWS SDAccel README]. | ||
|
|
||
| Xilinx web portal for [Xilinx SDAccel documentation] and for [Xilinx SDAccel GitHub repository] | ||
|
|
||
| Links pointing to **latest** version of the user guides | ||
| [UG1023: SDAccel Environment User Guide][latest SDAccel Environment User Guide] | ||
| [UG1021: SDAccel Environment Tutorial: Getting Started Guide (including emulation/build/running on H/W flow)][latest UG1021] | ||
| [UG1207: SDAccel Environment Optimization Guide][latest SDAccel Environment Optimization Guide] | ||
| [UG949: UltraFast Design Methodology Guide for the Vivado Design Suite][latest UG949] | ||
|
|
||
| Links pointing to **2017.1** version of the user guides | ||
| [UG1023: SDAccel Environment User Guide][UG1023 2017.1] | ||
| [UG1021: SDAccel Environment Tutorial: Getting Started Guide (including emulation/build/running on H/W flow)][UG1021 2017.1] | ||
| [UG1207: SDAccel Environment Optimization Guide][UG1207 2017.1] | ||
| [UG1238: SDx Development Environment Release Notes, Installation, and Licensing Guide][UG1238 2017.1] | ||
|
|
||
| [SDAccel_landing_page]: https://www.xilinx.com/products/design-tools/software-zone/sdaccel.html | ||
| [VHLS_landing_page]: https://www.xilinx.com/products/design-tools/vivado/integration/esl-design.html | ||
| [Vivado_landing_page]: https://www.xilinx.com/products/design-tools/vivado.html | ||
|
|
||
| [latest SDAccel Environment User Guide]: https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug1023-sdaccel-user-guide.pdf | ||
| [latest UG1021]: https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug1021-sdaccel-intro-tutorial.pdf | ||
| [latest SDAccel Environment Optimization Guide]: https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug1207-sdaccel-optimization-guide.pdf | ||
| [latest UG949]: https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug949-vivado-design-methodology.pdf | ||
|
|
||
| [UG1023 2017.1]: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_1/ug1023-sdaccel-user-guide.pdf | ||
| [UG1021 2017.1]: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_1/ug1021-sdaccel-intro-tutorial.pdf | ||
| [UG1207 2017.1]: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_1/ug1207-sdaccel-optimization-guide.pdf | ||
| [UG1238 2017.1]:http://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_1/ug1238-sdx-rnil.pdf | ||
| [Xilinx SDAccel documentation]: https://www.xilinx.com/products/design-tools/software-zone/sdaccel.html#documentation | ||
| [Xilinx SDAccel GitHub repository]: https://github.com/Xilinx/SDAccel_Examples | ||
|
|
||
| [AWS SDAccel Readme]: ../README.md | ||
| [Debug HLS Performance: Limited memory ports]: ./docs/SDAccel_HLS_Debug.md |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,87 @@ | ||
| # Amazon FPGA Hardware Development Kit | ||
| # | ||
| # Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. | ||
| # | ||
| # Licensed under the Amazon Software License (the "License"). You may not use | ||
| # this file except in compliance with the License. A copy of the License is | ||
| # located at | ||
| # | ||
| # http://aws.amazon.com/asl/ | ||
| # | ||
| # or in the "license" file accompanying this file. This file is distributed on | ||
| # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or | ||
| # implied. See the License for the specific language governing permissions and | ||
| # limitations under the License. | ||
|
|
||
| # AWS HAL Driver Makefile | ||
| # set ec2=1 to compile for F1 instance | ||
|
|
||
| ifndef SDK_DIR | ||
| $(error Environment variable SDK_DIR not set) | ||
| else | ||
| $(info SDK_DIR = $(SDK_DIR)) | ||
| endif | ||
|
|
||
| ifndef SDACCEL_DIR | ||
| $(error Environment variable SDACCEL_DIR not set) | ||
| else | ||
| $(info SDACCEL_DIR = $(SDACCEL_DIR)) | ||
| endif | ||
|
|
||
| ifndef XILINX_SDX | ||
| $(error Environment variable XILINX_SDX not set) | ||
| else | ||
| $(info XILINX_SDX = $(XILINX_SDX)) | ||
| endif | ||
|
|
||
| INSTALL_ROOT = /opt/Xilinx/SDx/2017.1 | ||
| DSA = xilinx_aws-vu9p-f1_4ddr-xpr-2pr_4_0 | ||
|
|
||
| all: | ||
| make -C ${SDACCEL_DIR}/userspace/src debug=$(debug) ec2=$(ec2) | ||
| make -C ${SDACCEL_DIR}/tools/awssak debug=$(debug) ec2=$(ec2) | ||
| make -C ${SDK_DIR}/linux_kernel_drivers/xdma | ||
|
|
||
| clean: | ||
| make -C ${SDACCEL_DIR}/userspace/src clean debug=$(debug) ec2=$(ec2) | ||
| make -C ${SDACCEL_DIR}/tools/awssak clean debug=$(debug) ec2=$(ec2) | ||
| make -C ${SDK_DIR}/linux_kernel_drivers/xdma clean | ||
|
|
||
| install: | ||
| make -C ${SDK_DIR}/linux_kernel_drivers/xdma install | ||
| install -d $(INSTALL_ROOT)/runtime/platforms/$(DSA)/driver | ||
| install -d $(INSTALL_ROOT)/runtime/bin | ||
| install -d $(INSTALL_ROOT)/runtime/lib/x86_64 | ||
| install -m 755 ${SDACCEL_DIR}/userspace/src/libawsxcldrv.so $(INSTALL_ROOT)/runtime/platforms/$(DSA)/driver | ||
| install -m 755 ${SDACCEL_DIR}/tools/awssak/xbsak $(INSTALL_ROOT)/runtime/bin | ||
| install -m 755 ${XILINX_SDX}/runtime/bin/xclbincat $(INSTALL_ROOT)/runtime/bin | ||
| install -m 755 ${XILINX_SDX}/runtime/bin/xclbinsplit $(INSTALL_ROOT)/runtime/bin | ||
| install -m 755 ${XILINX_SDX}/lib/lnx64.o/libxilinxopencl.so $(INSTALL_ROOT)/runtime/lib/x86_64 | ||
| install -m 755 ${XILINX_SDX}/lib/lnx64.o/libstdc++.so* $(INSTALL_ROOT)/runtime/lib/x86_64 | ||
| @echo "Generating SDAccel F1 runtime environment setup script, $(INSTALL_ROOT)/setup.sh for bash" | ||
| @echo "export XILINX_OPENCL=$(INSTALL_ROOT)" > $(INSTALL_ROOT)/setup.sh | ||
| @echo "export LD_LIBRARY_PATH=\$$XILINX_OPENCL/runtime/lib/x86_64:\$$LD_LIBRARY_PATH" >> $(INSTALL_ROOT)/setup.sh | ||
| @echo "export PATH=\$$XILINX_OPENCL/runtime/bin:\$$PATH" >> $(INSTALL_ROOT)/setup.sh | ||
| @echo "unset XILINX_SDACCEL" >> $(INSTALL_ROOT)/setup.sh | ||
| @echo "unset XILINX_SDX" >> $(INSTALL_ROOT)/setup.sh | ||
| @echo "unset XCL_EMULATION_MODE" >> $(INSTALL_ROOT)/setup.sh | ||
| @echo "Generating SDAccel F1 runtime environment setup script, $(INSTALL_ROOT)/setup.csh for (t)csh" | ||
| @echo "setenv XILINX_OPENCL $(INSTALL_ROOT)" > $(INSTALL_ROOT)/setup.csh | ||
| @echo "if ( ! \$$?LD_LIBRARY_PATH ) then" >> $(INSTALL_ROOT)/setup.csh | ||
| @echo " setenv LD_LIBRARY_PATH \$$XILINX_OPENCL/runtime/lib/x86_64" >> $(INSTALL_ROOT)/setup.csh | ||
| @echo "else" >> $(INSTALL_ROOT)/setup.csh | ||
| @echo " setenv LD_LIBRARY_PATH \$$XILINX_OPENCL/runtime/lib/x86_64:\$$LD_LIBRARY_PATH" >> $(INSTALL_ROOT)/setup.csh | ||
| @echo "endif" >> $(INSTALL_ROOT)/setup.csh | ||
| @echo "if ( ! \$$?PATH ) then" >> $(INSTALL_ROOT)/setup.csh | ||
| @echo " setenv PATH \$$XILINX_OPENCL/runtime/bin" >> $(INSTALL_ROOT)/setup.csh | ||
| @echo "else" >> $(INSTALL_ROOT)/setup.csh | ||
| @echo " setenv PATH \$$XILINX_OPENCL/runtime/bin:\$$PATH" >> $(INSTALL_ROOT)/setup.csh | ||
| @echo "endif" >> $(INSTALL_ROOT)/setup.csh | ||
| @echo "unsetenv XILINX_SDACCEL" >> $(INSTALL_ROOT)/setup.csh | ||
| @echo "unsetenv XILINX_SDX" >> $(INSTALL_ROOT)/setup.csh | ||
| @echo "unsetenv XCL_EMULATION_MODE" >> $(INSTALL_ROOT)/setup.csh | ||
| @echo "XILINX_OPENCL="$(INSTALL_ROOT) | ||
|
|
||
| .PHONY: all clean | ||
|
|
||
| .DEFAULT_GOAL := all |
Oops, something went wrong.