《FPGA应用开发和仿真》（机械工业出版社2018年第1版 ISBN:9787111582786）的源码。Source Code of the book FPGA Application Development and Simulation(CHS).

Simple UART transmitter and receiver

SUSTech 2024 Spring CS202 Course Project RISC-V 5-Stage-Pipeline CPU

UART interface to a block ram in the Tang Nano 9k FPGA. No pin connections needed, just use the USB UART.

FPGA implementation for UART interface for rx/tx data with support AXI-Stream protocol

Simple UART modules in SystemVerilog

UART controller that uses a master-slave architecture to enstablish a communication with the other device during the configuration process. This repository provides RTL code and testbench for the device synthesis and simulation, as well as a simple driver to use it in your system.

Alchitry Au FPGA Board Example Project

This is a re-write of my previous trigger project. This time Tang Nano 9k is the target hardware and the USB UART is used to configure and enable triggering.

UART interface to a block ram in the Tang Nano FPGA. No pin connections needed, just use the USB UART.

A simple UART BFM

6.111 Final Project: Freeform Production of Gorgeous Audio

UART Receiver and Transmitter using Terasic DE-10 Standard FPGA

Tea Encryption for ECE 4304 VHDL Design Project

This repository documents a project undertaken as part of the EN2111 Electronic Circuit Design module at the University of Moratuwa, focusing on the implementation of a UART communication link between two FPGA boards.

A serial UART for FPGAs

UART Tx implemented in SystemVerilog from scratch.

RISC-V SoC