single-cycle-processor

21Summer-VE370-Intro-to-Computer-Organization-Projects: -Project1: RISC-V Assembly, simluating c code. -Project2: 1.RISC-V64 single cycle processor. 2.RISC-V64 five-stage pipelined processor. -Project3: Virtual memory, TLB, cache, memory simulator. -Project4: Literature review on Computer Organization.

cpu virtual-memory tlb risc-v cpu-emulator computer-organization tlb-simulator riscv64 computer-organisation-architechure risc-v-assembly single-cycle-processor 5-stage-pipeline computer-organization-lab computer-organization-and-design

Updated Apr 11, 2023
Verilog

Fahad-Habib / RISC-V-Single-Cycle-Processor

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Single Cycle Processor written in SystemVerilog for executing machine code of RISC-V ISA

verilog systemverilog risc-v digital-system-design single-cycle-processor risc-v-architecture

Updated Apr 23, 2023
SystemVerilog

PebPeb / Single-Cycle-RV32I

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Single Cycle CPU using the RV32I Base Instruction set

cpu computer-architecture from-scratch risc-v single-cycle-processor

Updated Jul 15, 2023
Verilog

SnrNotHere16 / RISCVSingleCycleProcessor

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A RISC-V Single Cycle Processor which is done in verilog.

module verilog vivado computer-architecture risc-v 32-bit hardware-description-language riscv32 risc-architecture-processor single-cycle-processor testbench-generator-verilog

Updated Jul 20, 2020
Verilog

samadpls / ALEPH

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Aleph is a single cycle processor that carries out one instruction in a single clock cycle

scala riscv chisel3 risc-v single-cycle-processor

Updated Aug 8, 2023
Scala

arsalanjabbari / MIPS-CPU-Design

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This project involves the creation of a single-cycle MIPS CPU design using Verilog. The single-cycle microarchitecture is characterized by executing an entire instruction in one clock cycle. The project delves into the intricacies of designing and implementing a simplified MIPS CPU, providing insights into its fundamental components.

mips cpu-design single-cycle-processor

Updated Aug 14, 2023
Verilog

arhamhashmi01 / RV32I_Single_Cycle

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This repository contains the implementation of single cycle processor based on RISC-V ISA and implemented on "LOGISIM".

vhdl verilog microprocessor hardware-designs computer-architecture pipeline-processor rv32i single-cycle-processor 5-stage-pipeline 3-stagepipeline fetch-stage-pipeline

Updated May 24, 2024
Verilog

Elzawawy / mips-processor-simulator

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A simplified MIPS machine simulator using SystemVerilog, developed with three different micro-architectures: single-cycle, multi-cycle and pipelined.

mips mips-architecture mips-simulator pipelined-processors single-cycle-processor multi-cycle-processor

Updated Aug 31, 2020
SystemVerilog

OmarAmer01 / VP_Harvard_MIPS

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A 32-bit microprocessor with 42 instructions (including multiplication and division) and 8 X 32 registers and 2048 X 32 Ram with shared stack. An assembler is also available to write programs on the microprocessor using 8086-like assembly.

mips verilog computer-architecture vlsi modelsim single-cycle-processor

Updated Feb 19, 2022
Verilog

Vedant2311 / Complete-ARM-CPU

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Single and Multi-cycle ARM processors implemented using VHDL

fpga-programming single-cycle-processor multi-cycle-processor pmod-kypd multi-cycle-cpu

Updated Jan 26, 2021
VHDL

Visheshanagu2894 / riscv

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RISC-V 32IM - Dobby SOC

pipeline riscv32 booths-algorithm risc-v-assembly single-cycle-processor risc-v32im

Updated Jul 1, 2022
Verilog

Prajjv / RISC-V-Microprocessor-verilog-code-implementation-Artix-7-tested-with-Fibonacci-series-on-7seg

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Here we are implementing Risc-V single cycle microprocessor on Basys3 (Artix-7) .We are testing with Fibonaccie Series and showing on 7 segment display..

verilog microprocessor vivado fibonacci-numbers 7-segment risc-v fibonacci-sequence basys3 vivado-hls artix-7 basys3-fpga single-cycle-processor basys3-fpga-board

Updated Dec 7, 2022
Tcl

JoyenBenitto / grape

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grape is a single cycle RISC-V [RV32I] processor synthesised using SystemVerilog. This project was done as a part of the RISC-V Architecture course(UE20EC302). This my first attempt in building a processor.

systemverilog risc-v riscv32 single-cycle-processor

Updated May 12, 2024
SystemVerilog

muhammadtalhasami / RV32I_Single_Cycle

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This repository contains an implementation of a RV32I fetch pipeline microprocessor. The RV32I is a 32-bit RISC-V instruction set architecture, with the 'I' extension indicating the base integer instructions.