An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

32-bit Superscalar RISC-V CPU

An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support for 3-5 way superscalar execution. The core is pin-to-pin compatible with the RISCY cores from PULP

DUTH RISC-V Superscalar Microprocessor

A compiler, assembler, and processor.

Super scalar Processor design

Repositório para as aulas, exercícios e resumos da matéria: organização e arquitetura de computadores (INE5607).

Educational computer simulator on a mission to "superscalate" the study of computer architecture fundamentals

MIPS32 CPU implemented in SystemVerilog, with superscalar and branch prediction support

Two Level Branch Predictor Simulator - EE382N Superscalar Microprocessor Architecture, Spring 2019, Assignment 4

Easy-to-implement n-body simulation kernels created using Intel's ispc and llvm/clang

Direct Biot-Savart solver for 2D and 3D vortex blobs accelerated with Vc

Superscalar OoO RISCV processor written in Chisel

Implementation of advanced branch predictors, including Perceptron and Combinational Two-Level Adaptive Predictors, within the SimpleScalar simulator. Showcases enhancements in prediction accuracy and dynamic branch prediction techniques. This is a project for PSU ECE 587: Advanced Computer Architecture

A superscalar processor in Python

Superscalar dual-issue RISC-V processor

Superscalar 8 bit processor made in logisim and corresponding assembly language to bit code compiler.

This Verilog implementation represents a 32-bit MIPS processor featuring out-of-order execution.

A superscalar processor simulator written in Java as part of the Advanced Computer Architecture unit.

Out of order superscalar processor simulated in Javascript