ip-core

This repository showcases various projects developed on the DE10-Lite board (Intel MAX 10 FPGA) using Quartus Prime Lite software. The projects primarily focus on Finite State Machines (FSMs) and communication protocols, implemented in VHDL. Each project includes HDL code, testbenches, simulations, and .qsf files for pin assignments

fsm dsp vhdl verification finite-state-machine gtkwave testbench verilog-hdl digital-circuits ip-core uart-vhdl rtl-simulations

Updated Sep 5, 2024
Verilog

FlorianFrank / Verilog-UART-Custom-IP

Star

A custom UART IP core. Wrting to bare metal I/O pins independent of the FPGA model.

fpga serial verilog xilinx vivado uart ip-core

Updated Apr 5, 2023
Verilog

Teddy-van-Jerry / ip-doc

Star

LaTeX Class for IP Core Documentation

latex hardware ip latex-template cls ip-core latex3

Updated Oct 17, 2024
TeX

sbaldzenka / uart_core

Star

UART IP-core for FPGA.

fpga vhdl diamond uart hdl modelsim questasim ip-core lattice-fpga machxo3

Updated Sep 19, 2022
VHDL

alexo-git / AIC1106-IPcore

Star

The Altera Avalon bus IP core for TI AIC1106 PCM Codec and Software Driver Example

fpga voice verilog pcm altera ip-core tlv320aic1106

Updated Feb 18, 2019
C

rubinsteina13 / SV_DSM_CORE

Star

Synthesizable SystemVerilog IP-Core of the First-Order Delta-Sigma Modulator

fpga verilog digital-signal-processing system-verilog cpld dac ip-core asic-design

Updated Jun 6, 2020
SystemVerilog

rubinsteina13 / SV_CLARKE_TRANSFORMATION_CORES

Star

Synthesizable SystemVerilog IP-Cores of the Forward and Backward Clarke Transformation

fpga verilog systemverilog digital-signal-processing digital-design cpld ip-core asic-design

Updated Jun 7, 2020
SystemVerilog

magictaler / RGB-LED-PWM-Demo-for-Arty-Z7-20

Star

RGB PWM LED Demo project running on ARTY Z7-20 hardware

freertos xilinx ip-core zynq-7020

Updated May 16, 2020
C

esynr3z / pip-hdl

Star

📦 Tool to enable package managing for HDL VIP or IP cores (Verilog, SystemVerilog, VHDL) using Python pip

python vhdl verification vip pip verilog systemverilog ip-core rtl-design

Updated Jan 26, 2024
Python

iDoka / ipxact-cli-tools

Star

IP-XACT based CLI-tools

asic fpga xml eda spirit rtl asciidoc ip verilog ip-xact soc vlsi uvm ip-core design-automation accellera ieee-1685 ieee1685

Updated Apr 12, 2017
Mako

iDoka / ipyxact

Star

Python-based IP-XACT parser

asic fpga xml eda spirit rtl asciidoc ip verilog ip-xact soc vlsi uvm ip-core design-automation accellera ieee-1685 ieee1685

Updated Mar 27, 2017
Python

vedranMv / axi_spi_master

Star

IP core for a simple SPI master with variable clock frequncy within AXI peripheral. Developed and tested on Zybo evaluation board (Zynq-7000 product family)

spi vhdl-modules axi axi-spi ip-core