Split SystemVerilog keywords into type / not type

Moved all SystemVerilog keywords that are used when declaring signals to a separate `word3` category, as it was done for Verilog in PR #4037. The list has been obtained by picking all the keywords marked as K_(EVENT|REGISTER|LOCALPARAM|PORT|PARAMETER|CONSTANT|SPECPARAM|NET) in ctags/parsers/verilog.c, extended with additional keywords from SystemVerilog-2017 section 6.7 "Net declarations" (as it was done for Verilog in PR #4037), and with `signed` and `unsigned`. The result is a superset of the `word3` category for Verilog, extended with some keywords such as `logic`, `int`, `ref`, etc.
geany · Nov 18, 2024 · 85564aa · 85564aa
1 parent 66710b0
commit 85564aa
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/data/filedefs/filetypes.SystemVerilog.conf b/data/filedefs/filetypes.SystemVerilog.conf
@@ -3,9 +3,9 @@
 
 [keywords]
 # all items must be in one line
-word=accept_on alias always always_comb always_ff always_latch and assert assign assume automatic before begin bind bins binsof bit break buf bufif0 bufif1 byte case casex casez cell chandle checker class clocking cmos config const constraint context continue cover covergroup coverpoint cross deassign  default defparam design disable dist do edge else end endcase endchecker endclass endclocking endconfig endfunction endgenerate endgroup endinterface endmodule endpackage endprimitive endprogram endproperty endspecify endsequence endtable endtask enum event eventually expect export extends extern final first_match for force foreach forever fork  forkjoin function generate genvar global highz0 highz1 if iff ifnone ignore_bins illegal_bins implements implies import incdir include initial inout input inside instance int integer interconnect interface intersect join join_any join_none large let liblist library local localparam logic longint macromodule matches medium  modport module nand negedge nettype new nexttime nmos nor noshowcancelled not notif0 notif1 null or output package packed parameter pmos posedge primitive priority program property protected pull0 pull1 pulldown pullup pulsestyle_ondetect pulsestyle_onevent pure rand randc randcase randsequence rcmos real realtime ref reg  reject_on release repeat restrict return rnmos rpmos rtran rtranif0 rtranif1 s_always s_eventually s_nexttime s_until s_until_with scalared sequence shortint shortreal showcancelled signed small soft solve specify specparam static string strong strong0 strong1 struct super supply0 supply1 sync_accept_on sync_reject_on table tagged task this throughout  time timeprecision timeunit tran tranif0 tranif1 tri tri0 tri1 triand trior trireg type typedef union unique unique0 unsigned until until_with untyped use uwire var vectored virtual void wait wait_order wand weak weak0 weak1 while wildcard wire with within wor xnor xor
+word=accept_on alias always always_comb always_ff always_latch and assert assign assume automatic before begin bind bins binsof break buf bufif0 bufif1 case casex casez cell checker class clocking cmos config const constraint context continue cover covergroup coverpoint cross deassign default defparam design disable dist do edge else end endcase endchecker endclass endclocking endconfig endfunction endgenerate endgroup endinterface endmodule endpackage endprimitive endprogram endproperty endsequence endspecify endtable endtask enum eventually expect export extends extern final first_match for force foreach forever fork forkjoin function generate global if iff ifnone ignore_bins illegal_bins implements implies import incdir include initial inside instance interface intersect join join_any join_none let liblist library local macromodule matches modport module nand negedge nettype new nexttime nmos nor noshowcancelled not notif0 notif1 null or package packed pmos posedge primitive priority program property protected pulldown pullup pulsestyle_ondetect pulsestyle_onevent pure rand randc randcase randsequence rcmos reject_on release repeat restrict return rnmos rpmos rtran rtranif0 rtranif1 s_always s_eventually s_nexttime s_until s_until_with sequence showcancelled soft solve specify static strong struct super sync_accept_on sync_reject_on table tagged task this throughout timeprecision timeunit tran tranif0 tranif1 typedef union unique unique0 until until_with untyped use virtual wait wait_order weak while wildcard with within xnor xor
 word2=$finish $exit $stop  $realtime $time $stime  $printtimescale $timeformat  $bitstoreal $bitstoshortreal $itor $signed $cast $realtobits $shortrealtobits $rtoi $unsigned  $bits $typename $isunbounded  $unpacked_dimensions $left $low $increment $dimensions $right $high $size  $clog2 $ln $log10 $exp $sqrt $pow $floor $ceil $sin $cos $tan $asin $acos $atan $atan2 $hypot $sinh $cosh $tanh $asinh $acosh $atanh  $countbits $onehot $isunknown $countones $onehot0  $fatal $warning $error $info  $fatal $warning $error $info  $asserton $assertkill $assertpasson $assertfailon $assertnonvacuouson $assertoff $assertcontrol $assertpassoff $assertfailoff $assertvacuousoff  $sampled $fell $changed $past_gclk $fell_gclk $changed_gclk $rising_gclk $steady_gclk $rose $stable $past $rose_gclk $stable_gclk $future_gclk $falling_gclk $changing_gclk  $coverage_control $coverage_get $coverage_save $set_coverage_db_name $coverage_get_max $coverage_merge $get_coverage $load_coverage_db  $random $dist_erlang $dist_normal $dist_t $dist_chi_square $dist_exponential $dist_poisson $dist_uniform  $q_initialize $q_remove $q_exam $q_add $q_full  $async$and$array $async$nand$array $async$or$array $async$nor$array $sync$and$array $sync$nand$array $sync$or$array $sync$nor$array $async$and$plane $async$nand$plane $async$or$plane $async$nor$plane $sync$and$plane $sync$nand$plane $sync$or$plane $sync$nor$plane  $system
-word3=
+word3=bit byte chandle event genvar highz0 highz1 inout input int integer interconnect large localparam logic longint medium output parameter pull0 pull1 real realtime ref reg scalared shortint shortreal signed small specparam string strong0 strong1 supply0 supply1 time tri tri0 tri1 triand trior trireg type unsigned uwire var vectored void wand weak0 weak1 wire wor
 docComment=
 
 [settings]