filetypes.verilog: add Verilog-2005 keywords #4037
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(Note that this PR is unrelated to SystemVerilog; all I added here is still plain old Verilog. I still plan to create a commit adding support for SystemVerilog, but that'll be on a different PR.) |
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As a side note, I see that Do you think it would be a good idea to add those as well? (Personally I've never used most of those; the only few I've ever used were properly highlighted.) Note that these are not "keywords" per se, just system functions, but I suppose it's OK to handle them as "keywords" for the purpose of highlighting. (They're highlighted in a different color from actual keywords, which is the important thing.) |
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@cousteaulecommandant Thanks. I think nobody from Geany developers uses Verilog so I guess we'll trust your choices :-).
I think it would be best to put the new keywords to the "word" list among the original keywords. The only difference is the coloring of the various lists - see the mapping to the theme colors:
Note that Geany currently doesn't respect the
Just a note - the Verilog ctags parser contains also System Verilog parser. We could enable it if you add the SystemVerilog filetype.
Depends whether Verilog users would expect them to be highlighted or not. The other "keyword" lists are used this way for other languages too but I don't know what's the common practice for Verilog. |
Some of them appear to be builtin types so maybe it makes sense to keep them in |
There's also this PR you might want to check #1831 - if it's alright, maybe that one could be merged. |
Honestly this is why I was confused. In the default theme, both word and word3 are bold navy blue and therefore indistinguishable - in fact I didn't know Geany treated them differently for Verilog until I saw it in filetypes.verilog - whereas word2 is dark red. It makes sense because this way navy blue = keywords but dark red = "standard functions". But it doesn't make sense that some keywords are considered one type and others are another type; I couldn't figure out which criteria was used to make keywords "word" or "word3" (the latter seem to be "stuff for net/variable declaration", but then again so are many of the keywords declared in "word").
All of them are "keywords", according to the standard (Annex B). The only thing about "different" keywords I could find was in section 19.11 of the standard, which states that you can actually "disable" all of the new keywords added in Verilog 2001 and 2005, so if your design is super old and uses variable names that have later become reserved keywords, you can disable those so that you can use them as regular identifiers.
Honestly I don't quite understand what
Personally I think it's good to see
That's the plan, yes. The Verilog lexer also seems to support SystemVerilog, so I've got the two hardest parts covered. I already have a commit that adds the language, and a PR almost ready.
That one only adds keywords though; proper handling of SystemVerilog may require a bit more. (And the parser and the lexer are already made so why not?) |
It's really up to the contributor of filetype support. For instance, java uses primary=abstract assert break case catch class const continue default do else enum exports extends final finally for goto if implements import instanceof interface module native new non-sealed open opens package permits private protected provides public record requires return sealed static strictfp super switch synchronized this throw throws to transient transitive try uses var volatile when while with yield true false null
secondary=boolean byte char double float int long short void
# documentation keywords for javadoc
doccomment=author deprecated exception param return see serial serialData serialField since throws todo version
typedefs=Those "secondary" keywords are normal keywords, just defining primitive types and are highlighted differently which kind of makes sense. But if you feel there's no such analogy in Verilog, it's probably best to have them all in one group.
I have kind of the same feeling ;-). See #4038
Then I'd say leave it as it is. |
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Regarding the keywords: While you are at, Scintilla supports (in the meantime) even more keyword lists: https://github.com/ScintillaOrg/lexilla/blob/master/lexers/LexVerilog.cxx#L1076 Maybe it also helps to have a look at the SciTE configuration: |
There is, but it's complicated. Basically there are a few "data types" proper (think C's char, int, float), and a ton of modifiers/specifiers describing how the signal behaves "physically" (think static, const, volatile, extern, etc). But I think I can make a distinction between "keywords that are used to declare signals/variables/constants" and "keywords that are not used to declare signals/variables/constants". If that's common practice I can give it a try; I think it can be done. Option 2 is what I have now - separate keywords in "old keywords" and "newer keywords from a newer standard that a very old file might be using for something else", but I don't think that'll be that much useful. Option 3 is cram everything into a single category, which I think is what C does. In any case, the default theme uses the same color for both so it's hard for me to see the difference.
On second thought, I think I'll better add those as well. There are a few I use often that aren't listed (
Those look pretty much like what we already have though.
Apparently they cram all the keywords as keywords1 and leave keywords2 blank (my "Option 3"), keywords3 is the $ stuff ( |
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For the sake of "keeping the things the way they were", I've gone with option 1, and tried my best at grouping the keywords into things that are used for declaring signals/constants, and things that are not. I think the result is good. I have also decided to add all the standard system functions/tasks. This is how it looks now (with I've pushed the new version to this PR (and rebased it on top of master, while I was at it). |
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Apart from the |
- Add Verilog-2001 and Verilog-2005 keywords to filetypes.verilog
(right now only Verilog-1995 keywords are highlighted).
These keywords were already included in ctags.
- Add all System tasks and functions as of Verilog-2005 to `word2` list
(right now only a handful appear; perhaps from an older standard).
Details on added/removed keywords:
Add new keywords from Verilog-2001 and Verilog-2005 standard (Annex B)
(right now only Verilog-1995 keywords are listed):
automatic generate endgenerate genvar localparam uwire
config endconfig cell design instance liblist use
library incdir include
pulsestyle_ondetect pulsestyle_onevent showcancelled noshowcancelled
Remove invalid Verilog keywords:
attribute endattribute strength @
Put all "keywords used to declare nets/variables/constants/events"
in `word3` list; leave rest in `word`.
Add all functions/tasks listed under "System tasks and functions"
in the Verilog-2005 standard (chapter 17).
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$ characterMoved all SystemVerilog keywords that are used when declaring signals to a separate `word3` category, as it was done for Verilog in PR geany#4037. The list has been obtained by picking all the keywords marked as K_(EVENT|REGISTER|LOCALPARAM|PORT|PARAMETER|CONSTANT|SPECPARAM|NET) in ctags/parsers/verilog.c, extended with additional keywords from SystemVerilog-2017 section 6.7 "Net declarations" (as it was done for Verilog in PR geany#4037), and with `signed` and `unsigned`. The result is a superset of the `word3` category for Verilog, extended with some keywords such as `logic`, `int`, `ref`, etc.
Moved all SystemVerilog keywords that are used when declaring signals to a separate `word3` category, as it was done for Verilog in PR geany#4037. The list has been obtained by picking all the keywords marked as K_(EVENT|REGISTER|LOCALPARAM|PORT|PARAMETER|CONSTANT|SPECPARAM|NET) in ctags/parsers/verilog.c, extended with additional keywords from SystemVerilog-2017 section 6.7 "Net declarations" (as it was done for Verilog in PR geany#4037), and with `signed` and `unsigned`. The result is a superset of the `word3` category for Verilog, extended with some keywords such as `logic`, `int`, `ref`, etc.
Moved all SystemVerilog keywords that are used when declaring signals to a separate `word3` category, as it was done for Verilog in PR geany#4037. The list has been obtained by picking all the keywords marked as K_(EVENT|REGISTER|LOCALPARAM|PORT|PARAMETER|CONSTANT|SPECPARAM|NET) in ctags/parsers/verilog.c, extended with additional keywords from SystemVerilog-2017 section 6.7 "Net declarations" (as it was done for Verilog in PR geany#4037), and with `signed` and `unsigned`. The result is a superset of the `word3` category for Verilog, extended with some keywords such as `logic`, `int`, `ref`, etc.
Moved all SystemVerilog keywords that are used when declaring signals to a separate `word3` category, as it was done for Verilog in PR geany#4037. The list has been obtained by picking all the keywords marked as K_(EVENT|REGISTER|LOCALPARAM|PORT|PARAMETER|CONSTANT|SPECPARAM|NET) in ctags/parsers/verilog.c, extended with additional keywords from SystemVerilog-2017 section 6.7 "Net declarations" (as it was done for Verilog in PR geany#4037), and with `signed` and `unsigned`. The result is a superset of the `word3` category for Verilog, extended with some keywords such as `logic`, `int`, `ref`, etc.
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...Sorry; I didn't realize I have to RESOLVE the code reviews after I fix them. 😅 |
Nah, it doesn't matter :-) Alright, let's merge this one too. Thanks for your contributions! |
filetypes.verilogonly includes ancient Verilog-1995 keywords (plussignedandunsignedfor some reason), but is missing plenty of the newer Verilog-2001 and the newest Verilog-2005 keywords, some of them very common, such asgenerate/endgenerate,localparam,automatic...I have added all those "new" keywords to the
word3=category to distinguish them from the "classic" keywords from the previous century, although I honestly don't know what's the difference between the two categories.I have also moved all the keywords that used to be in
word3=toword=, since I didn't see any reason to keep those keywords there (they seem to be related to "variable declarations" one way or another, but then again, so are many of the keywords listed inword=). This way,word=will be for the "old" keywords, andword3=for the "new" ones that "might not work in a Verilog tool made in the previous century".Finally, I have added
$to the list ofwordchars=, because Verilog is special and considers $ to be an identifier character like_(so e.g.$finishandgotabout$350are valid identifiers).