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ravenoc Public
RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
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cdc_components Public
Collection of different designs for clock domain crossing
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cocotbext-waves Public
Generate wavedrom figures out of design signals
Python MIT License UpdatedNov 1, 2024 -
cocotbext-ahb Public
Cocotb AHB Extension - AHB VIP
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learn Public
Forked from riscv/learnTracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.
UpdatedOct 21, 2024 -
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cocotb_design_playground Public template
Template repository for Cocotb RTL development
Python MIT License UpdatedSep 4, 2024 -
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vim-header Public
Forked from alpertuna/vim-headerEasily adds brief author info and license headers
Vim Script MIT License UpdatedAug 25, 2024 -
axi_register_slice Public
AXI Register Slice used to break timing path in AXI bus
SystemVerilog MIT License UpdatedAug 22, 2024 -
verilog_systemverilog.vim Public
Forked from vhda/verilog_systemverilog.vimVerilog/SystemVerilog Syntax and Omni-completion
Vim Script UpdatedAug 18, 2024 -
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digital_design_library Public
List of several designs I have been working through the years to avoid re-designing it again
4 UpdatedJun 17, 2024 -
axi_dma Public
General Purpose AXI Direct Memory Access
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pp-sp-reference-design Public
Forked from j-marjanovic/pp-sp-reference-designSystemVerilog UpdatedNov 10, 2023 -
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verilog-axi Public
Forked from alexforencich/verilog-axiVerilog AXI components for FPGA implementation
Verilog MIT License UpdatedOct 13, 2022 -
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riscv-arch-test-nox Public
Forked from riscv-non-isa/riscv-arch-test -
riscv-formal Public
Forked from SymbioticEDA/riscv-formalRISC-V Formal Verification Framework
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