Skip to content
View aignacio's full-sized avatar

Block or report aignacio

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Pinned Loading

  1. digital_design_library digital_design_library Public

    List of several designs I have been working through the years to avoid re-designing it again

    4

  2. ravenoc ravenoc Public

    RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications

    SystemVerilog 148 32

  3. axi_dma axi_dma Public

    General Purpose AXI Direct Memory Access

    SystemVerilog 44 10

  4. nox nox Public

    RISC-V Nox core

    C 61 6

  5. cocotbext-ahb cocotbext-ahb Public

    Cocotb AHB Extension - AHB VIP

    Python 11 7

  6. cocotbext-waves cocotbext-waves Public

    Generate wavedrom figures out of design signals

    Python