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æœ¬å½“ã«ã‚ã‹ã‚‹ Spectre ã¨ Meltdown
1. æœ¬å½“ã«ã‚ã‹ã‚‹ Spectre ã¨ Meltdown å·ç”°è£•è²´ @hktechno 1 ã‚»ã‚ãƒ¥ãƒªãƒ†ã‚£ãƒ»ã‚ãƒ£ãƒ³ãƒ—å…¨å›½å¤§ä¼š2018 è¬›ç¾©è³‡æ–™ URL: https://goo.gl/uTwX2c 2. è‡ªå·±ç´¹ä»‹ @hktechno å·ç”° è£•è²´ (ã‹ã‚ãŸ ã²ã‚ãŸã‹) â— LINE æ ªå¼ä¼šç¤¾ é–‹ç™º1ã‚»ãƒ³ã‚¿ãƒ¼ LINE é–‹ç™º1å®¤ â—‹ ãƒ¡ãƒƒã‚»ãƒ³ã‚¸ãƒ£ãƒ¼ãƒ—ãƒ©ãƒƒãƒˆãƒ•ã‚©ãƒ¼ãƒ ã®é–‹ç™º â—‹ ä¸»ã«ã€ã‚¹ã‚¿ãƒ³ãƒ—ãƒ»çµµæ–‡å—ãƒ»ç€ã›ã‹ãˆã€ãŸã¾ã« IoT â— è‡ªä½œ CPU é–‹ç™ºã«ãƒãƒžã£ã¦ã„ãŸ â—‹ ã‚¢ã‚¦ãƒˆãƒ»ã‚ªãƒ–ãƒ»ã‚ªãƒ¼ãƒ€ãƒ¼å®Ÿè¡Œã§ãã‚‹è‡ªä½œ CPU â—‹ ä¸»ã«ã‚³ãƒ³ãƒ‘ã‚¤ãƒ©ã‚’ä½œã£ã¦ã„ãŸ â—‹ http://open-arch.org/ â—‹ http://amzn.asia/gtThKbh 2 3. çµŒæ´ï¼Ÿ 2008å¹´ ã‚»ã‚ãƒ¥ãƒªãƒ†ã‚£ãƒ»ãƒ—ãƒã‚°ãƒ©ãƒŸãƒ³ã‚°ã‚ãƒ£ãƒ³ãƒ—å‚åŠ 2009, 2010, 2012 ãƒãƒ¥ãƒ¼ã‚¿ãƒ¼, 2015 è¬›å¸« 2009å¹´ ç‘æ³¢å¤§å¦
mooz 2018/08/19
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processor

security
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Intelã€æ·±å±¤å¦ç¿’ç”¨ãƒ—ãƒã‚»ãƒƒã‚µã€ŒNervana NNPã€ ï½žä»Šå¹´ä¸ã«49é‡åãƒ“ãƒƒãƒˆã®é‡åæ¼”ç®—ãƒãƒƒãƒ—è£½é€ ã‚‚äºˆå‘Š
mooz 2017/10/19
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machine_learning
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Google supercharges machine learning tasks with TPU custom chip | Google Cloud Blog
Google supercharges machine learning tasks with TPU custom chip Editor's Update June 27, 2017: We recently announcedÂ Cloud TPUs. Machine learning provides the underlying oomph to many of Googleâ€™s most-loved applications. In fact, more than 100 teams are currently using machine learning at Google today, from Street View, to Inbox Smart Reply, to voice search. But one thing we know to be true at Goo
mooz 2016/05/20
TPU: Tensor Processing Unit

processor

machine_learning
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Hisa Ando ã®è¨˜äº‹ä¸€è¦§(1ãƒšãƒ¼ã‚¸ç›®) | ãƒžã‚¤ãƒŠãƒ“ãƒ‹ãƒ¥ãƒ¼ã‚¹
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mooz 2014/04/17
processor

cpu

gpu

hpc
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Why is a CPU branch instruction slow?
mooz 2014/02/19
branch

processor

cpu
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Xeon Phi - Wikipedia
Xeon Phi[3] is a discontinued series of x86 manycore processors designed and made by Intel. It was intended for use in supercomputers, servers, and high-end workstations. Its architecture allowed use of standard programming languages and application programming interfaces (APIs) such as OpenMP.[4][5] Xeon Phi launched in 2010. Since it was originally based on an earlier GPU design (codenamed "Larr
mooz 2013/06/18
Intel Many Integrated Core Architecture (MIC)

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hpc

processor
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mooz 2013/01/19
SPARC64 X. 16ã‚³ã‚¢. ãƒ‡ãƒ¼ã‚¿ãƒ™ãƒ¼ã‚¹å‡¦ç†ç”¨ã®å‘½ä»¤ã‚’ãƒ“ãƒ«ãƒˆã‚¤ãƒ³. æš—å·ï¼Œãƒãƒƒã‚·ãƒ¥ãªã©ï¼Ž

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processor
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mooz 2012/06/26
cpu

processor

performance
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mooz 2011/11/24
DRP: Dynamic Reconfigurable Processor

processor
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ãƒ¬ã‚¸ã‚¹ã‚¿ãƒ»ãƒªãƒãƒ¼ãƒŸãƒ³ã‚° - Wikipedia
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mooz 2011/11/10
ROB: Reorder Buffer

processor
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mooz 2011/11/03
processor
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ã€ã‚¤ãƒ™ãƒ³ãƒˆãƒ¬ãƒãƒ¼ãƒˆã€‘ ã€AFDSãƒ¬ãƒãƒ¼ãƒˆã€‘ MicrosoftãŒGPGPUé–‹ç™ºå‘ã‘C++ã®æ‹¡å¼µã€ŒC++ AMPã€ã‚’ç™ºè¡¨
mooz 2011/10/31
Heterogeneous computing. User mode dispatch.

processor

gpgpu
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å¾Œè—¤å¼˜èŒ‚ã®Weeklyæµ·å¤–ãƒ‹ãƒ¥ãƒ¼ã‚¹ 2017å¹´ è¨˜äº‹ä¸€è¦§ - PC Watch
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mooz 2011/10/31
processor

hardware
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ãƒˆãƒ©ãƒ³ã‚¹ãƒ¬ãƒ¼ã‚·ãƒ§ãƒ³ãƒ»ãƒ«ãƒƒã‚¯ã‚¢ã‚µã‚¤ãƒ‰ãƒ»ãƒãƒƒãƒ•ã‚¡ï¼ˆè‹±: Translation Lookaside Bufferã€TLBï¼‰ã¨ã¯ã€ãƒ¡ãƒ¢ãƒªç®¡ç†ãƒ¦ãƒ‹ãƒƒãƒˆå†…ã®ã‚ã‚‹ç¨®ã®ã‚ãƒ£ãƒƒã‚·ãƒ¥ã§ã‚ã‚Šã€ä»®æƒ³ã‚¢ãƒ‰ãƒ¬ã‚¹ã‹ã‚‰ç‰©ç†ã‚¢ãƒ‰ãƒ¬ã‚¹ã¸ã®å¤‰æ›ã®é«˜é€ŸåŒ–ã‚’å›³ã‚‹ã‚‚ã®ã§ã‚ã‚‹ã€‚ã“ã‚“ã«ã¡ã®ä»®æƒ³è¨˜æ†¶ã‚’ã‚µãƒãƒ¼ãƒˆã™ã‚‹ãƒžã‚¤ã‚¯ãƒãƒ—ãƒã‚»ãƒƒã‚µã¯ã€ä»®æƒ³ç©ºé–“ã¨ç‰©ç†ç©ºé–“ã®ãƒžãƒƒãƒ”ãƒ³ã‚°ã«TLBã‚’åˆ©ç”¨ã—ã¦ã„ã‚‹ã®ãŒã»ã¨ã‚“ã©ã§ã‚ã‚‹ã€‚ TLBã¯é€šå¸¸ã€é€£æƒ³ãƒ¡ãƒ¢ãƒª (CAM) ã§å®Ÿè£…ã•ã‚Œã¦ã„ã‚‹ã€‚CPUãŒãƒ¡ãƒ¢ãƒªç©ºé–“ã«ã‚¢ã‚¯ã‚»ã‚¹ã™ã‚‹éš›ã€æ¤œç´¢ã‚ãƒ¼ã¨ã—ã¦ä»®æƒ³ã‚¢ãƒ‰ãƒ¬ã‚¹ã‚’ä½¿ã„ã€TLBä¸Šã«ãã®ã‚¢ãƒ‰ãƒ¬ã‚¹ã«å¯¾å¿œã™ã‚‹ã‚¨ãƒ³ãƒˆãƒªãŒã‚ã‚Œã°ã€æ¤œç´¢çµæžœã¨ã—ã¦å¯¾å¿œã™ã‚‹ç‰©ç†ã‚¢ãƒ‰ãƒ¬ã‚¹ãŒè¿”ã‚‹ã€‚ã“ã‚Œã‚’ã€ŒTLBãƒ’ãƒƒãƒˆã€ã¨å‘¼ã¶ã€‚è¦æ±‚ã—ãŸã‚¢ãƒ‰ãƒ¬ã‚¹ãŒTLBå†…ã«ãªã„å ´åˆã¯ã€ŒTLBãƒŸã‚¹ã€ã§ã‚ã‚Šã€ã‚¢ãƒ‰ãƒ¬ã‚¹å¤‰æ›ã®ãŸã‚ã«ãƒšãƒ¼ã‚¸ãƒ†ãƒ¼ãƒ–ãƒ«ã‚’è¾¿ã£ã¦ã„ã‹ãªã‘ã‚Œã°ãªã‚‰ãªã„ã€‚ã“ã‚Œã‚’ã€Œãƒšãƒ¼ã‚¸ã‚¦ã‚©ãƒ¼ã‚¯ã€ã¨å‘¼ã¶ã€‚ãƒšãƒ¼ã‚¸ã‚¦ã‚©ãƒ¼ã‚¯ã¯è¤‡æ•°å€‹æ‰€ã®ãƒ¡ãƒ¢ãƒªã®
mooz 2011/09/08
TLB. TLB miss.

processor

cpu
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NPU - Wikipedia
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