Index

Sl.No: Name of Experiment Date Remarks

Vision and Mission

1 PEO, PO and PSOs of the Program

2 SAFETY PROCEDURES

3 HANDLING ELECTROSTATIC DISCHARGE (ESD)

4 FAMILIARISATION OF KIT

5 STUDY OF LOGIC GATES

6 DEMONSTARION OF UNIVERSAL GATES

7 DE MORGAN’S LAW

8 HALF ADDER AND FULL ADDER

9 HALF SUBTRACTOR AND FULL SUBTRACTOR

10 CODE CONVERTER

11 MULTIPLEXER

12 MULTIPLEXER IC

13 DEMULTIPLEXER

14 SR AND D FLIPFLOP

15 STUDY OF 7474 IC AND 7473 IC

16 ASYNCHRONOUS DECADE COUNTER

17 RING COUNTER

18 JOHNSON COUNTER

19 SYNCHRONOUS DECADE COUNTER

VISION AND MISSION

Government Polytechnic College, Meppadi

Vision

To be a premier institute in pursuit of excellence in technical education by molding

socially committed technicians and entrepreneurs bringing sustainable development of
the society.

Mission
• To provide industry-oriented technical education to rural students through
excellent teaching and learning.
• To provide high-quality education, a respectful and inclusive environment
that builds lifelong learning.
• To inspire students to make a positive social impact through education,
creativity and entrepreneurship.
• To provide an innovative environment to learn, innovate and create new
ideas for the betterment of oneself and society.

Department of Electronics Engineering

Vision

To be a Centre for quality technical education in the field of electronics engineering for the
empowerment of society.

Mission
➢ Provide quality education through an outcome-based curriculum and effective teaching-
learning process to face the challenges of the Electronics Engineering field
➢ Impart value-based education by promoting activities that benefit the rural upliftment of
society.
➢ Inculcate social responsibility and ethics through curricular, co-curricular, and extra-
curricular activities.
➢ To provide a platform for inculcating entrepreneurship by exposing them to the latest
advancements in the industry.
Exp No. 1 Date: D D - M M - Y Y
PEO, PO and PSOs of the Program
Program Outcomes (POs)

PO1
Basic and Discipline specific knowledge: Apply knowledge of basic mathematics,
science and engineering fundamentals and engineering specialization to solve the
engineering Problems

PO2
Problem analysis: Identify and analyse well-defined engineering problems using codified
standard methods.

PO3
Design/ development of solutions: Design solutions for well-defined technical problems
and assist with the design of systems components or processes to meet specified needs.

PO4
Engineering Tools, Experimentation and Testing: Apply modern engineering tools and
appropriate technique to conduct standard tests and measurements.

PO5
Engineering practices for society, sustainability and environment: Apply appropriate
technology in context of society, sustainability, environment and ethical practices.

PO6
Project Management: Use engineering management principles individually, as a team
member or a leader to manage projects and effectively communicate about well-
defined engineering activities.

PO7
Life-long learning: Ability to analyse individual needs and engage in updating in the
context of technological changes.
Program Educational Outcome (PEOs)

▪ Excel in professional career and /or higher education by acquiring knowledge in

the area of Electronics Engineering.
▪ Mold the students with good scientific and engineering concepts so as to enable
them to analyses, design & create new products and solutions for real-life needs.
▪ Equip responsible electronics engineers with professionalism, ethical attitudes,
communication skills, self-learning & teamwork in their profession.

Program Specific Outcome (PSO)

▪ Good Knowledge and competence to solve real-world problems related to the

electronics engineering field.

▪ Demonstrate a sense of professional ethics, recognize the importance of

continued learning, and be able to carry out their professional and
entrepreneurial responsibilities in the electronics engineering field giving due
consideration to environmental protection and sustainability.
Exp No. 2 Date: D D - M M - Y Y

SAFETY PROCEDURES
Problem Statement:

The safety instructions are presented to the attention of the students as a mean of preventing
accidents while performing experiments and activities in the communication lab of the
department. The purpose is to draw attention to the risks involved in lab activities to prevent
human suffering and damage to equipment.

Safety in the laboratory:

• Working in the lab is not allowed without following electricity precautions displayed.
• No individual work is allowed in the lab.
• Laboratory in charge is responsible for the arrangements of your lab activities; Listen
carefully to his/her instructions and follow them.

To do and not to do:

• Inform the lab in charge about dangerous conditions and faults in the lab or nearby
environment.
•
Do not do any action that may harm people or equipments in the lab.
•
Do not misuse any of the tools or instruments belong to the lab.

• Strict discipline should be maintained in the laboratory.

• Turn off cell phones before entering the lab.

•
At the end and beginning of laboratory, follow 5S procedures and leave the work table
clean and tidy.

Electrical Safety:

• Consult Electrical Engineering section available in the campus for electrical safety
queries.
• The lab equipment is powered from electrical sockets installed on the tables. Do not use
equipment that is powered from a damaged socket.
• Do not use equipment that is powered from flexible cable with damaged insulation or if
it’s plug is not assembled properly.
• Do not repair or disassemble electrical equipment including replacement of fuses
installed in the equipment.

• Do not open the main fuse box, unless it is an emergency and you need to switch off
main circuit breaker.

Emergency Switches:

The laboratory has circuit breakers, which is located in the main panel. Identify the place.
In an emergency condition, switch off circuit breakers immediately.

Result

Familiarization of safety precautions performed.

Exp No. 3 Date: D D - M M - Y Y

HANDLING ELECTROSTATIC DISCHARGE (ESD)

Problem Statement

Familiarize ESD handling procedures in the laboratory

Theory

In handling electronic devices, datasheets cautions about ESD (Electrostatic Discharge)

precautions. These devices are prone to damage because of electrostatic charges made by
human body. These charges may be up to 4000 volts and cause damage without being noticed.
It is recommended to follow ESD precautions on handling of these devices.

Points for the elimination of ESD damage to electronic components

1. Make sure you have a reliable ground point available near the table.
2. Do not wear clothing which generates static electric charges every time you move.
3. Do not handle static generating objects while working on electronics.
4. Store all chips and other components in appropriate anti-static containers.
5. Keep all ESD sensitive components and spares in anti-static envelopes for storage.
6. Be sure to turn off the power and remove the power plug from all equipment before
working repairing or assembling.
7. Do not plug in or remove equipment while the power is on.
Result

Familiarization of ESD protection procedures performed.

For Office use only Signature of Lab in charge Remarks

Readiness to do experiment

Completion of Experiment
Exp No. 4 Date: D D - M M - Y Y

DIGITAL IC TRAINER KIT

Problem Statement

Familiarize Digital IC trainer kit for the Lab experiments

Theory

Electronics is most effectively and to grab from concept to concrete the knowledge of
electronics. Digital IC Trainer provides you hands on practical experience on Digital and
TTL Electronics at one place and saver the time and money without compromising the
quality standards. This trainer kit is specially designed for the use in engineering for
students to study and set up a different experiment.
Technical specification:
Input 230V ±10% 50 Hz;
Power supply :5V, 2A, ±12V,500mA;
Pulse Generator 1Hz to 100 KHz;
Pulse switches for providing Logic H/L Pulse;
7 Segment Display BCD 2 Digit Decoder;
12 Logic input switches for Provided H/L Signal;
12 Logic status indicating LED Indicator;
Connecting provision BS2 socket with 25 Patch cords;
2 Nos. of Bread Boards;
16 pin Zip socket 2 Nos.;
Overload LED indicator with buzzer indicator and short circuit protection;
Closed type Wooden Case
Result

Familiarized with Digital IC trainer kit

Digital Trainer Kit
Exp No. 5 Date: D D - M M - Y Y

STUDY OF LOGIC GATES

AIM:

Verify the truth tables of logic gates – NOT, OR, AND, NAND, NOR, XOR

OBJECTIVES

• To familiarize with the basic logic gate ICs commonly used in digital electronics.
• To study the working of logic gates using digital ICs.
• To understand the concept of Truth table verification using digital ICs.
• They will understand the universal property of NAND and NOR gates.

COMPONENTS REQUIRED

Sl No COMPONENTS SPECIFICATION QTY

1 NOT GATE IC 7404 1
2 AND GATE IC 7408 1
3 OR GATE IC 7432 1
4 NAND GATE IC 7400 1
5 NOR GATE IC 7402 1
6 XOR GATE IC 7486 1
7 IC TRAINER KIT - 1
8 CONNECTING WIRES - AS REQUIRED

THEORY

Circuit that takes the logical decision and the process are called logic gates. Each gate has one
or more input and only one output. OR, AND and NOT are basic gates. NAND, NOR are known
as universal gates.

NOT GATE: The NOT gate is called an inverter. The output is high when the input is low. The
output is low when the input is high. Output Y= NOT(A) where A is the input.
AND GATE: The AND gate performs a logical multiplication commonly known as AND function.
The output is high when both the inputs are high. The output is low level when any one of the
inputs is low. Output Y= A.B where A and B are the inputs.

OR GATE: The OR gate performs a logical addition commonly known as OR function. The output
is high when any one of the inputs is high. The output is low level when both the inputs are low.
Output Y= A+B where A and B are the inputs.

NAND GATE: The NAND gate is a combination of AND-NOT. The output is high when any one of
the input is low or both inputs are low. The output is low level only when both inputs are high.

NOR GATE: The NOR gate is a combination of OR-NOT. The output is high when both inputs are
low. The output is low when one or both inputs are high.

X-OR GATE: The output is high when any one of the inputs is high. The output is low when both
the inputs are low and both the inputs are high.

PROCEDURE

1. Check all the ICs using a digital IC tester.

2. Connect the circuit as per the circuit diagram.
3. Apply Vcc and Ground.
4. Logical inputs are given as per truth table using switches provided.
5. Observe the output on LEDs and verify the truth table.

RESULT

Familiarized with basic logic gate ICs and verified their truth tables.
OUTPUT
Exp No. 6 Date: D D - M M - Y Y

DEMONSTRATION OF UNIVERSAL GATES

AIM:

To implement basic gates using universal gates(NAND and NOR)

OBJECTIVES

• To study the design and implementation of logic gates (NOT, AND, OR, NOR, XOR) using
universal property of NAND and NOR gates.
• To verify their truth tables.

COMPONENTS REQUIRED

Sl No COMPONENTS SPECIFICATION QTY

1 NAND GATE IC 7400 1
2 NOR GATE IC 7402 2
3 IC TRAINER KIT - 1
4 CONNECTING WIRES - AS REQUIRED

THEORY
A universal gate is a logic gate which can implement any Boolean function without the need to
use any other type of logic gate. The NOR gate and NAND gate are universal gates. This means
that you can create any logical Boolean expression using only NOR gates or only NAND gates.
These gates can be used to generate NOT, AND, OR and XOR operation.

A NAND gate (short for NOT-AND) is the same as AND followed by NOT. You can see how the
symbols together,

NAND GATE
̅̅̅̅̅
The equation for a NAND gate is 𝑌 = 𝐴. 𝐵 where A and B are input to the NAND gate and Y is
the output. The truth table for NAND is the opposite of AND.
A NOR gate (short for NOT-OR) is the same as OR followed by NOT. You can see how the
symbols together,

The equation for a NAND gate is 𝐶 = ̅̅̅̅̅̅̅̅

𝐴 + 𝐵 where A and B are input to the NOR gate and C is
the output. The truth table for NAND is the opposite of AND.

PROCEDURE

1. Check all the ICs using a digital IC tester.

2. Connect the circuit as per the circuit diagram.
3. Apply Vcc and Ground.
4. Logical inputs are given as per truth table using switches provided.
5. Observe the output on LEDs and verify the truth table.

RESULT

NOT, OR, AND and XOR gates are implemented using NAND and NOR gates.
OUTPUT
UNIVERSAL PROPRERTY OF NAND GATE

NOT gate using NAND gate

AND gate using NAND gate

OR gate using NAND gate

XOR gate using NAND gate

UNIVERSAL PROPRERTY OF NOR GATE

NOT gate using NOR gate

AND gate using NOR gate

OR gate using NOR gate

XOR gate using NOR gate

Exp No. 7 Date: D D - M M - Y Y

DE MORGAN’S THEOREM
AIM:

To verify De Morgan’s theorems using logic gates.

OBJECTIVES
• Students will study how to interconnect different gates in a circuit.
• To study about De Morgan’s theorem.

COMPONENTS REQUIRED

Sl No COMPONENTS SPECIFICATION QTY

1 AND GATE IC 7408 1
2 OR GATE IC 7432 1
3 NOT GATE IC 7404 1
4 NAND GATE IC 7400 1
5 NOR GATE IC 7402 1
6 IC TRAINER KIT - 1
7 CONNECTING WIRES - AS REQUIRED

THEORY
The de Morgan’s theorem for two variables A and B ca be stated as follows,

̅̅̅̅̅
𝐀. 𝐁 = 𝐀̅+𝐁 ̅
̅̅̅̅̅̅̅
𝐀+𝐁=𝐀 ̅. 𝐁
̅
DE Morgan’s First theorem proves that when two input variables are AND’ed and negated, they
are equivalent to the OR of the complements of the individual variables. DE Morgan’s second
theorem proves that when two input variables are OR’ed and negated, they are equivalent to
the AND of the complements of the individual variables.
PROCEDURE

1. Check all the ICs using a digital IC tester.

2. Connect the circuit as per the circuit diagram.
3. Apply Vcc and Ground.
4. Logical inputs are given as per truth table using switches provided.
5. Observe the output on LEDs and verify the truth table.

RESULT
De Morgan’s theorem is verified using truth table.
OUTPUT

̅̅̅̅̅ ̅+𝑩
𝑨. 𝑩 = 𝑨 ̅

TRUTH TABLE

̅̅̅̅̅̅̅
𝑨+𝑩=𝑨 ̅. 𝑩
̅

TRUTH TABLE
Exp No. 8 Date: D D - M M - Y Y

HALF ADDER AND FULL ADDER

AIM:

To construct half adder and full adder circuits and verify the truth table using logic gates.

OBJECTIVES
• Students will study how to interconnect different gates in a circuit.
• They can differentiate Half adder from Full adder.
COMPONENTS REQUIRED

Sl No COMPONENTS SPECIFICATION QTY

1 AND GATE IC 7408 1
2 OR GATE IC 7432 1
3 XOR GATE IC 7486 1
4 IC TRAINER KIT - 1
5 CONNECTING WIRES - AS REQUIRED

THEORY
HALF ADDER: A half adder has two inputs for the two bits to be added, no carry from previous
stage is considered. Hence half adder may be considered for adding LSB. It has two outputs one
from the sum S and other from the carry C. The Sum is obtained from the X-OR Gate and the
Carry out from the AND gate. Sum, 𝑆 = 𝐴. 𝐵̅ + 𝐴.
̅ 𝐵 and Carry 𝐶 = 𝐴. 𝐵

FULL ADDER: A combinational logic circuit that can add two binary digits (bits) and a carry bit,
and produces a sum bit and a carry bit as output is known as a full-adder. It is a combinational
circuit which is designed to add three binary digits and produces two outputs (sum and carry) is
known as a full adder.
DESIGN
HALF ADDER
From above truth table, the expressions for carry and sum can be derived using the sum
product terms.

FULL ADDER

PROCEDURE

1. Check all the ICs using a digital IC tester.

2. Connect the circuit as per the circuit diagram.
3. Apply Vcc and Ground.
4. Logical inputs are given as per truth table using switches provided.
5. Observe the output on LEDs and verify the truth table.

RESULT

Designed and constructed half adder and full adder circuits and verified the truth table using
logic gates.
OUTPUT

HALF ADDER

FULL ADDER
Exp No. 9 Date: D D - M M - Y Y

HALF SUBTRACTOR AND FULL SUBSTRACTOR

AIM:

To construct half subtractor and full subtractor circuits and verify the truth table using logic
gates.

OBJECTIVES

• Students will study how to interconnect different gates in a circuit.

• They can differentiate Half subtractor from Full subtractor.
COMPONENTS REQUIRED

Sl No COMPONENTS SPECIFICATION QTY

1 AND GATE IC 7408 1
2 OR GATE IC 7432 1
3 XOR GATE IC 7486 1
4 NOT GATE IC 7404 1
4 IC TRAINER KIT - 1
5 CONNECTING WIRES - AS REQUIRED

THEORY
HALF SUBTRACTOR: A half subtractor has two inputs for the two bits to be subtracted, no
borrow from previous stage is considered. Hence half a may be considered for subtracting LSBs.
It has two outputs one from the Difference D and other is Borrow B. The difference is obtained
from the X-OR Gate and the Borrow out from the AND gate. Difference, D= 𝐴. 𝐵̅ + 𝐴. ̅ 𝐵 and
Borrow 𝐵 = 𝐴.̅𝐵

FULL SUBTRACTOR: A combinational logic circuit that can subtract two binary digits (bits) and a
borrow bit, and produces a difference bit and a borrow bit as output is known as a full-
subtractor. It is a combinational circuit which is designed to subtract three binary digits and
produces two outputs (Difference and borrow) is known as a full subtractor.

DESIGN

HALF ADDER
From above truth table, the expressions for difference and carry can be derived using the sum
of product terms.

FULL SUBTRACTOR

From the truth table, taking the sum of product terms, we get
PROCEDURE

1. Check all the ICs using a digital IC tester.

2. Connect the circuit as per the circuit diagram.
3. Apply Vcc and Ground.
4. Logical inputs are given as per truth table using switches provided.
5. Observe the output on LEDs and verify the truth table.

RESULT

Designed and constructed half Subtractor and full subtractor circuits and verified the truth
table using logic gates.
OUTPUT
HALF SUBTRACTOR
FULL SUBTRACTOR
Exp No. 10 Date: D D - M M - Y Y

CODE CONVERTER
AIM:

To construct and verify the truth tables of

(i) 4 bit Binary to gray code converter
(ii) 4 bit Gray to binary code converter

OBJECTIVES

• Students will study how to construct a Binary to Gray and Gray to binary code
converters.

COMPONENTS REQUIRED

Sl No COMPONENTS SPECIFICATION QTY

1 XOR GATE IC 7486 1
2 IC TRAINER KIT - 1
3 CONNECTING WIRES - AS REQUIRED

THEORY

The gray code is a very light weighted code because it doesn't depend on the value of the digit
specified by the position. This code is also called a cyclic variable code as the transition of one
value to its successive value carries a change of one bit only. The MSB in gray code is same as
the MSB in binary code.

The input variables for a Binary to Gray converter are designated as B3, B2, B1, and B0 and the
output variables are designated as G3, G2, G1,and G0. Meanwhile the inputs for a Gray to
Binary converter is G3, G2, G1,and G0 and its output generates B3, B2, B1, and B0.
PROCEDURE

1.Check all the ICs using a digital IC tester.

2.Connect the circuit as per the circuit diagram.
3.The circuit connections are made as shown in figure.
4.Pin (14) is connected to +Vcc and Pin (7) to ground.
5.In the case of binary to gray conversion, the inputs B0, B1, B2 and B3 are given at respective
pins and outputs G0, G1, G2, G3 are taken for all the 16 combinations of the input.
6.In the case of gray to binary conversion, the inputs G0, G1, G2 and G3 are given at respective
pins and outputs B0, B1, B2, and B3 are taken for all the 16 combinations of inputs.
7.The values of the outputs are tabulated.

RESULT

Designed and implemented a 4 bit Binary to gray code converter and 4bit Gray to binary code
converter
OUTPUT
Exp No. 11 Date: D D - M M - Y Y

MULTIPLEXER
AIM:

To setup a 4 :1 MUX using basic gates.

OBJECTIVES
After completion of experiment

• To learn about various applications of multiplexer.

• To learn and understand the working of MUX
COMPONENTS REQUIRED

Sl No COMPONENTS SPECIFICATION QTY

1 3 I/P AND GATE IC 7411 2
2 OR GATE IC 7432 1
3 NOT GATE IC 7404 1
4 IC TRAINER KIT - 1
5 CONNECTING WIRES - AS REQUIRED

THEORY

Multiplexer means many to one. A multiplexer is a circuit with many inputs but only one
output. By using control signals (select lines) we can select any input to the output. Multiplexer
is also called as data selector because the output bit depends on the input data bit that is
selected. The general multiplexer circuit has 2n input signals, n control/select signals and 1
output signal.

PROCEDURE:
1. Test all the ICs manually/ using IC tester.
2. Connections are made as in the logic circuit diagram and give Vcc and the ground.
3. Connect the appropriate pins to the input switches and output LEDs.
4. Give various combinations of the inputs and observe the output and verify the truth table.
5. Similarly verify the mux circuit with truth table.

RESULT

Realized 4:1 Multiplexer using basic gates

OUTPUT
Exp No. 12 Date: D D - M M - Y Y

MULTIPLEXER IC
AIM:

To study the multiplexer IC 74151.

OBJECTIVES

Students will study about multiplexer IC 74151.

COMPONENTS REQUIRED

Sl No COMPONENTS SPECIFICATION QTY

1 8 X 1 MUX IC 7411 1
2 IC TRAINER KIT - 1
3 CONNECTING WIRES - AS REQUIRED

THEORY

In most of the electronic systems, the digital data is available on more than one line. It is
necessary to route this data over a single line. Under such circumstances we require a circuit
which selects one of the many inputs at a time.

An 8:1 Multiplexer has eight data inputs D0 to D7, three select inputs S0 to S2, an enable input
and one output. Depending upon the digital code applied at the select inputs one out of n data
input is selected & transmitted to a single o/p channel. Normally strobe (G) input is
incorporated which is generally active low which enables the multiplexer when it is LOW.
Strobe i/p helps in cascading. IC 74151A is an 8: 1 multiplexer which provides two
complementary outputs Y & ̅ Y The o/p Y is same as the selected i/p & Y̅ is its complement.

PROCEDURE:

1. Test the IC74151.

2. Connections are made as per circuit diagram.
3. Keep Enable pin HIGH to see that the output is always 0 for all input combinations.
4. Keep Enable pin LOW and verify the truth table for various combinations of inputs.
RESULT

Studied about 8x1 MUX 74151 and verified its truth table.
OUTPUT

Note: Pin No.7 Enable pin is ACTIVE LOW input. So should be 0 to enable the IC
Exp No. 13 Date: D D - M M - Y Y

DEMULTIPLEXER
AIM:

To setup a 1:4 DEMUX using basic gates.

COMPONENTS REQUIRED

Sl No COMPONENTS SPECIFICATION QTY

1 3 I/P AND GATE IC 7411 2
2 NOT GATE IC 7404 1
3 IC TRAINER KIT - 1
4 CONNECTING WIRES - AS REQUIRED
THEORY

De-multiplexer means one to many. A de-multiplexer is a circuit with only one input but many
outputs. By using control signals (select lines) we can select input to any outputs. The general
de-multiplexer circuit has 1 input signals, n control/select signals and 2n output signals.

DESIGN

1:4 DEMUX FUNCTION TABLE

From the truth table, when S1=0 and S0= 0, the data input is connected to output Y0 and when
S1= 0 and S0=1, then the data input is connected to output Y1. Similarly, other outputs are
connected to the input for other two combinations of select lines.
From the table, the output logic can be expressed as min terms and are given below.
Where D is the input data, Y0 to Y3 are output lines and S0 & S1 are select lines.

PROCEDURE:
1. Test all the ICs manually/ using IC tester.
2. Connections are made as in the logic circuit diagram and give Vcc and the ground.
3. Connect the appropriate pins to the input switches and output LEDs.
4. Give various combinations of the inputs and observe the output and verify the truth table.
5. Similarly verify the demux circuit with truth table.

RESULT

Realized 1:4 Demultiplexer using basic gates.

OUTPUT
Exp No. 14 Date: D D - M M - Y Y

SR FLIPFLOP AND D FLIPFLOP

AIM:

Construct SR flip flop using NAND gates and convert it into D flip flop.

OBJECTIVES
• Students will study how to construct flip flops using NAND gates.
• To convert SR to D flipflop
COMPONENTS REQUIRED
Sl No COMPONENTS SPECIFICATION QTY
1 NAND GATE IC 7400 1
2 NOT GATE IC 7404 1
3 IC TRAINER KIT - 1
4 CONNECTING WIRES - AS REQUIRED

THEORY
SR Flip-Flop
An SR Flip-Flop can be considered as a basic one-bit memory device that has two inputs, one
which will "SET" the device and another which will "RESET" the device and an output Q that will
be either at a logic level "1" or logic "0" depending upon this Set/Reset condition. A basic NAND
Gate SR flip flop circuit provides feedback from its outputs to its inputs and is commonly used in
memory circuits to store data bits. The term "Flip-flop" relates to the actual operation of the
device, as it can be "Flipped" into one logic state or "Flopped" back into another. Flipflop is
basically a Bistable Multivibrator.
D Flip-Flop
The D-type Flip-flop overcomes one of the main disadvantages of the basic SR NAND Gate
Bistable circuit in that the indeterminate input condition of SET = “0” and RESET = “0” is
forbidden. This state will force both outputs to be at logic “1”, over-riding the feedback latching
action and whichever input goes to logic level “1” first will lose control, while the other input
still at logic “0” controls the resulting state of the latch.But in order to prevent this from
happening an inverter can be connected between the “SET” and the “RESET” inputs to produce
another type of flip flop circuit known as a Data Latch, Delay flip flop, D-type Bistable, D-type
Flip Flop or just simply a D Flip Flop as it is more generally called.
PROCEDURE
1. Connections are made as per circuit diagram.
2. Verify the truth table for various combinations of inputs.
RESULT

Constructed SR flipflop using NAND gate and verified the truth table. Converted it to D flipflop.
OUTPUT
BLOCK DIAGRAM OF SR FLIPFLOP

CONVERT SR FLIPFLOP TO D FLIPFLOP

Exp No. 15 Date: D D - M M - Y Y

STUDY OF 7474 IC AND 7473 IC

AIM:

Demonstrate the use of D Flip Flop IC 7474, JK Flip Flop IC 7473

OBJECTIVES

• Students will study how to use 7474 IC and 7473 IC.

COMPONENTS REQUIRED

Sl No COMPONENTS SPECIFICATION QTY

1 D FLIPFLOP IC 7474 1
2 J K FLIPFLOP IC 7473 1
3 IC TRAINER KIT - 1
4 CONNECTING WIRES - AS REQUIRED

THEORY

7474 l D Flip-Flop
IC 7474 or mostly known as IC 74LS74 is a dual D Flip Flop positive edge-triggered IC. It has two
independent D Flip Flops with complementary outputs. It has D input and Q output. The data in
the D input may be changed during the high or low clock but it does not affect the output and
the delay times also do not affect. The IC 7474 can be operated up to 7V voltage and 0 to +70
degrees centigrade temperature. The main features of the IC 74LS74 are, it provides very fast
switching, low propagation delay, large operating mode, etc. It is used to Create delay-lines

7473 DUAL JK FLIPFLOP

The 74LS73 device contains two independent negative-edge-triggered J-K flip-flops with
complementary outputs. The J and K data is processed by the flip-flops on the falling edge of
the clock pulse. A low logic level on the clear input will reset the outputs regardless of the levels
of the other inputs.

74LS73 Features

• Two Individual Flip-Flops with J,K Clock, Set and Clear Inputs
• Input Data is Transferred to the Outputs on HIGH-LOW Clock Transition
• Fast Switching Speed
• Operating Temperature up to 70°C
• Standard TTL Switching Voltages
Applications
• Event Detectors
• Data Synchronizers
• Frequency Divider

PROCEDURE
1. Connections are made as per circuit diagram.

2. Verify the truth table for various combinations of inputs.

RESULT

Familiarised with 7474 IC and 7473 IC

OUTPUT

NOTE: Preset and clear pins are active low

7473 Pin diagram Truth table of 7473

Exp No. 16 Date: D D - M M - Y Y

ASYNCHRONOUS DECADE COUNTER

AIM:

To construct asynchronous (ripple) mod-10 counter using flip-flops with 7 segment display.

OBJECTIVES

Students will study how to construct a MOD 10 ripple counter and show it to 7 segment display.

COMPONENTS REQUIRED

Sl No. COMPONENTS SPECIFICATION QTY

1 JK FLIPFLOP IC 7473 2

2 NAND GATE IC 7400 1

3 IC TRAINER KIT - 1
4 Connecting wires - As required

THEORY

In a digital circuit, counters are used to do 3 main functions: timing, sequencing and counting.
Counters are generally made up of flip-flops and logic gates. Digital counters are classified as
sequential circuits. The main types of flip-flops used are J-K flip-flops or T flip-flops, which are J-
K flip-flops with both J and K inputs tied together.
Counter represents the number of clock pulses arrived. A specified sequence of states appears
as counter output. This is the main difference between a register and a counter. There are two
types of counter, synchronous and asynchronous. In synchronous common clock is given to all
flip flop and in asynchronous first flip flop is clocked by external pulse and then each successive
flip flop is clocked by Q or 𝑄̅ output of previous stage ie the clock of second stage is triggered by
output of first stage. Because of inherent propagation delay time all flip flops are not activated
at same time which results in asynchronous operation.

The modulus is the number of unique states through which the counter will sequence. The
maximum possible number of states of a counter is 2n where ‘n’ is the number of flip-flops.
Counters can be designed to have a number of states in their sequence that is less than the
maximum of 2n . This type of sequence is called a truncated sequence. One common modulus
for counters with truncated sequences is 10 (Modules10). A decade counter with a count
sequence of zero (0000) through 9 (1001) is a BCD decade counter because its 10-state
sequence produces the BCD code. To obtain a truncated sequence, it is necessary to force the
counter to recycle before going through all of its possible states. A decade counter requires 4
flip-flops. If we take the modulo-16 ripple counter and modified it with additional logic gates it
can be made to give a decade (divide-by-10) counter output for use in standard decimal
counting and arithmetic circuits. Such counters are generally referred to as Decade Counters. A
decade counter requires resetting to zero when the output count reaches the decimal value of
10, ie. when DCBA = 1010 . One way to make the counter recycle after the count of 9 (1001) is
to decode the count ‘10’ (1010) with a NAND gate and connect the output of the NAND gate to
the clear (CLR) inputs of the flip-flops.

This type of asynchronous counter counts upwards on each leading edge of the input clock
signal starting from "0000" until it reaches an output "1010" (decimal 10). Both outputs Q1 and
Q3 are now equal to logic "1" and the output from the NAND gate changes state from logic "1"
to a logic "0" level and whose output is also connected to the CLEAR (CLR) inputs of all the J-K
Flip-flops. This causes all of the Q outputs to be reset back to binary "0000" on the count of 10.
Once QB and QD are both equal to logic "0" the output of the NAND gate returns back to a logic
level "1" and the counter restarts again from "0000". We now have a decade or Modulo-10
counter.

PROCEDURE

1. Connections are given as per circuit diagram.

2. Logical inputs are given as per truth table.
3. Observe the output and verify the truth table.

RESULT

A MOD 10 RIPPLE/ASYNCHRONOUS counter is constructed with 7 segment display and verified

the truth table.
OUTPUT
Exp No. 17 Date: D D - M M - Y Y
RING COUNTER
AIM:

To construct a Ring Counter and verify the truth table.

OBJECTIVES
• To construct a Ring counter

COMPONENTS REQUIRED

THEORY

A ring counter is formed by feeding the output of a shift register to its own input. Here
the last output ie. QD in a shift register is connected back to the serial input. The data pattern
enclosed within the shift register will re-circulate with respect to the clock pulse. Ring counter is
one of the shift register applications. A ring counter has N states where ‘N’ is the number of
flip-flops.
The synchronous Ring Counter is preset so that exactly one data bit in the register is set to logic
“1” with all the other bits reset to “0”. To achieve this, a “CLEAR” signal is firstly applied to all
the flip-flops together in order to “RESET” their outputs to a logic “0” level and then a “PRESET”
pulse is applied to the input of the first flip-flop ( FFA ) before the clock pulses are applied. This
then places a single logic “1” value into the circuit of the ring counter.

So on each successive clock pulse, the counter circulates the same data bit between the
four flip-flops over and over again around the “ring” every fourth clock cycle. But in order to
cycle the data correctly around the counter we must first “load” the counter with a suitable
data pattern as all logic “0’s” or all logic “1’s” outputted at each clock cycle would make the ring
counter invalid.

PROCEDURE

1. Connections are made as per the circuit diagram.

2. Apply the data 1000 at flipflop A, B, C and D respectively.
3. In the beginning, clear all flip flops using ̅̅̅̅̅̅
𝐶𝐿𝑅 input by applying ‘0’ to all clear inputs. After
that, keep it at logic state ‘1’. In order to make QA high to begin, we should keep 𝑃𝑅𝐸 ̅̅̅̅̅̅ of
̅̅̅̅̅̅ =
flipflop A at “ 0 “ for a time period which is less than the clock duration. After that keep 𝑃𝑅𝐸
1 for proper working
For this,keep the mode input M = 1, apply one clock pulse. (<16Hz).
4. Now the mode M is made 0 and clock pulses are applied one by one and
the truth table is verified.
5.Observe the output and verify the truth table.

RESULT

Constructed a Ring counter and the truth table is verified.

OUTPUT

IC 7474(positive edge triggered dual D flipflop with active LOW, PRESET and CLEAR inputs)
Exp No. 18 Date: D D - M M - Y Y

JOHNSON COUNTER

AIM:

To construct a Johnson Counter and verify the truth table.

OBJECTIVES

• To construct a Johnson counter

COMPONENTS REQUIRED

THEORY

A shift register counter is basically a shift register with the serial output connected back to the
serial input to produce special sequences. These devices are often classified as counters
because they exhibit a specified sequence of states. Two of the most common types of shift
register counters, the Johnson counter and the ring counter.
Johnson Counter
The Johnson digital counter or Twisted Ring Counter is a synchronous shift register with
feedback from the inverted output (𝑄̅ ) of the last flip-flop. 𝑄̅ of the last flip flop is connected
back to the input D of the first flip-flop. This inversion of Q before it is fed back to input D
causes the counter to “count” in a special way. The main benefit of this type of counter is that it
only needs half the number of flip flops compared to that of standard ring counter to represent
many states. So an n-stage Johnson counter gives a sequence of 2n different states and can
therefore be treated as a “Mod 2n counter” whereas an n-stage ring counter has only n states
that is “Mod n counter”.
It can be implemented using D-type flip-flops (or JK-type flip-flops). The output of each flip flop
is connected to the input of the next. The complementary output 𝑄̅ of the last flipflop is
connected to the first input.
In order to make Q1 high to begin, we should keep ̅̅̅̅̅̅̅̅𝑃𝑅𝐸1 = 0 for a time period which is less
̅̅̅̅̅̅̅̅ = 1 for proper working.
than the clock duration. After that keep 𝑃𝑅𝐸1
PROCEDURE

Connections are given as per circuit diagram.

1. In the beginning, clear all flip flops using CLR input.

̅̅̅̅̅̅̅̅ = 0 for a time period which is less

2. In order to make Q1 high to begin, we should keep 𝑃𝑅𝐸1
̅̅̅̅̅̅̅̅
than the clock duration. After that keep 𝑃𝑅𝐸1 = 1 for proper working

3.Observe the output and verify the truth table

RESULT

Constructed a Johnson counter and the truth table is verified.

OUTPUT

LOGIC DIAGRAM FOR JOHNSON COUNTER

Exp No. 19 Date: D D - M M - Y Y

SYNCHRONOUS COUNTERS
AIM:

To construct synchronous mod-8 counters using JK flipflops .

OBJECTIVES

Students will get an idea about

• Understanding the operation and characteristics of synchronous counters
• Analyse counter circuits
• Determine the sequence of a counter
• Determine the modulus of a counter sequences
• Understand different applications of flip flops.
• Realize the frequency division of signals.

COMPONENTS REQUIRED

THEORY

A synchronous counter, in contrast to an asynchronous counter, is one whose output bits

change state simultaneously, in synchronous with the clock signal with no ripple. The” clock"
pulses are applied to all the flip-flops in counter simultaneously. Depending on the way in which
the counting progresses ,the synchronous and asynchronous counters are classified into (i)up
counters (ii)down counters(iii) up/down counters
A synchronous binary counter counts from 0 to 2n-1, where ‘n’ is the number of bits/flip-flops in
the counter. Each flip-flop is used to represent one bit.
Modulus (MOD) is the number of states it counts in a complete cycle before it goes back to the
initial state.
Up Counter:
The binary output is taken from the Q outputs of the flip-flops. In FF0 the J and K inputs are
permanently wired to logic 1, so Q0 will change state (toggle) on each clock pulse. This provides
the ‘ones’ count for the least significant bit (LSB).
On FF1 the J1 and K1 inputs are both connected to Q0 so that FF1 output will only be in toggle
mode when Q0 is also at logic 1. As this only happens on alternate clock pulses, Q1 will only
toggle on even numbered clock pulses giving a ‘twos’ count on the Q1 output.
FF2 is put into toggle mode by making J2 and K2 logic 1,only when Q0 and Q1 are at logic 1.
In the first flip-flop, J = K = 1 .In subsequent flipflops, J = K, but the logical value is determined
by an AND gate. Thus,J1=K1=Q0 and J2=K2 = Q1·Q0
Down Counter
As every Q output on the JK flip-flops has its complement on 𝑄̅ , to convert the up counter into
the down counter, take the JK inputs for FF1 from the 𝑄̅ output of FF0 instead of the Q output.
The AND gate takes its inputs from the 𝑄̅ outputs of FF0 and FF1.

PROCEDURE

1. Test all the ICs manually/ using IC tester.

2. Connections are made as in the logic circuit diagram and give VCC and the ground.
3. Connect the clock signal (<16Hz) input and output to LEDs.
4. Observe the count and verify the truth table.

RESULT

1. Studied 3 bit synchronous up counter .

2. Studied 3 bit synchronous down counter.
OUTPUT