DDC 232

DDC232

www.ti.com SBAS331D – AUGUST 2004 – REVISED APRIL 2010

32-Channel, Current-Input
Analog-to-Digital Converter
Check for Samples: DDC232

1FEATURES The DDC232 uses a +5V analog supply and a +2.7V

2• Single-Chip Solution to Directly Measure 32 to +3.6V digital supply. Operating over the
temperature range of 0°C to +70°C, the DDC232
Low-Level Currents
BGA-64 package is offered in two versions: the
• High-Precision, True Integrating Function DDC232C for low-power applications, and the
• Integral Linearity: DDC232CK when higher speeds are required.
±0.025% of Reading ±1.0ppm of FSR
• Very Low Noise: 5.3ppm of FSR AVDD VREF DVDD
• Low Power: 7mW/channel 0.1mF

0.1mF 0.1mF
• Adjustable Full-Scale Range
• Adjustable Speed
Dual
– Data Rate up to 6kSPS Switched CLK
IN1 Integrator
– Integration Times as low as 166.5ms DS CONV

ADC Configuration
DIN_CFG
• Daisy-Chainable Serial Interface Dual
and
Switched Control
IN2 CLK_CFG
• In-Package Bypass Capacitors Simplify PCB Integrator
Design RESET
Dual
APPLICATIONS IN3 Switched

Integrator
DS
• CT Scanner DAS ADC
• Photodiode Sensors Dual DVALID
Switched
IN4
• X-Ray Detection Systems Integrator
DESCRIPTION
DCLK
The DDC232 is a 20-bit, 32-channel, current-input IN29
Dual
Switched
Integrator
analog-to-digital (A/D) converter. It combines both DS
Serial
current-to-voltage and A/D conversion so that 32 ADC
Interface
separate low-level current output devices, such as Dual
Switched
photodiodes, can be directly connected to its inputs IN30 Integrator DOUT
and digitized.
For each of the 32 inputs, the DDC232 provides a Dual
Switched
dual-switched integrator front-end. This configuration IN31 Integrator
DIN
allows for continuous current integration: while one DS
ADC
integrator is being digitized by the onboard A/D
Dual
converter, the other is integrating the input current. IN32 Switched
Integrator
Adjustable integration times range from 166ms to 1s,
allowing currents from fAs to mAs to be continuously
measured with outstanding precision. AGND DGND
The DDC232 has a serial interface designed for Protected by US Patent #5841310
daisy-chaining in multi-device systems. Simply
connect the output of one device to the input of the
next to create the chain. Common clocking feeds all
the devices in the chain so that the digital overhead
in a multi-DDC232 system is minimal.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2004–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
DDC232
SBAS331D – AUGUST 2004 – REVISED APRIL 2010 www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DEVICE FAMILY COMPARISON

MAXIMUM DATA PACKAGE-
PRODUCT # OF CHANNELS FULL-SCALE RATE POWER/CHANNEL LEAD
DDC112 2 1000pC (1) 20kSPS 40mW SO-28
DDC112K 2 1000pC (1) 3.3kSPS 40mW TQFP-32
DDC114 4 350pC 3.3kSPS 13mW QFN-48
DDC118 8 350pC 3.3kSPS 13mW QFN-48
DDC316 16 12pC 100kSPS 28mW BGA-64
DDC232C 32 350pC 3.1kSPS 7mW BGA-64
DDC232CK 32 350pC 6.2kSPS 10mW BGA-64
(1) Using external integration capacitors.
PACKAGE/ORDERING INFORMATION
For the most current package and ordering information see the Package Option Addendum at the end of this
document, or visit the device product folder on www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)

AVDD to AGND –0.3V to +6V
DVDD to DGND –0.3V to +3.6V
AGND to DGND ±0.2V
VREF Input to AGND 2.0V to AVDD + 0.3V
Analog Input to AGND –0.3V to +0.7V
Digital Input Voltage to DGND –0.3V to DVDD + 0.3V
Digital Output Voltage to DGND –0.3V to AVDD + 0.3V
Operating Temperature 0°C to +70°C
Storage Temperature –60°C to +150°C
Junction Temperature (TJ) +150°C
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
2 Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): DDC232

DDC232
ELECTRICAL CHARACTERISTICS
At TA = +25°C, AVDD = +5V, DVDD = +3.0V, VREF = +4.096V, tINT = 333ms for DDC232C or 166ms for DDC232CK,
Range 7, and continuous mode operation, unless otherwise noted.
DDC232C DDC232CK
PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNIT
ANALOG INPUT RANGE
Range 0 12.5 12.5 pC
Range 1 45 50 55 45 50 55 pC
Range 2 90 100 110 90 100 110 pC
Range 3 135 150 165 135 150 165 pC
Range 4 180 200 220 180 200 220 pC
Range 5 225 250 275 225 250 275 pC
Range 6 270 300 330 270 300 330 pC
Range 7 315 350 385 315 350 385 pC
Negative Full-Scale Range –0.4% of Positive Full-Scale Range –0.4% of Positive Full-Scale Range pC
DYNAMIC CHARACTERISTICS
Data Rate 3 3.125 6 6.2 kSPS
Integration Time, tINT Continuous Mode 320 1,000,000 160 1,000,000 ms
Noncontinuous Mode 50 50 ms
System Clock (CLK) Clk_4x = 0 1 5 1 10 MHz
Clk_4x = 1 4 20 4 40 MHz
Data Clock (DCLK) 20 20 MHz
Configuration Clock (CLK_CFG) 20 20 MHz
ACCURACY
Noise, Low-Level Input (1) CSENSOR (2)
= 50pF 5.3 7 5.3 7 ppm of FSR (3), rms
Integral Linearity Error (4) ±0.025% Reading ± 1.0ppm FSR, typ ±0.025% Reading ± 1.0ppm FSR, typ
±0.05% Reading ± 1.5ppm FSR, max ±0.05% Reading ± 1.5ppm FSR, max
Resolution No Missing Codes, Format = 1 20 19 (5) Bits
No Missing Codes, Format = 0 16 16 Bits
Input Bias Current ±0.1 ±10 ±0.1 ±10 pA
Range Error Match (6) 0.1 0.5 0.1 0.5 % of FSR
Range Sensitivity to VREF VREF = 4.096 ±0.1V 1:1 1:1
Offset Error ±200 ±1000 ±200 ±1000 ppm of FSR
Offset Error Match (6) ±100 ±100 ppm of FSR
DC Bias Voltage (7) Low-Level Input (< 1% FSR) ±0.1 ±2 ±0.1 ±2 mV
Power-Supply Rejection Ratio at DC 100 ±800 100 ±800 ppm of FSR/V
(1) Input is less than 1% of full-scale.

(2) CSENSOR is the capacitance seen at the DDC232 inputs from wiring, photodiode, etc.
(3) FSR is Full-Scale Range.
(4) A best-fit line is used in measuring nonlinearity.
(5) Output word is 20 bits with 19 bits no missing codes.
(6) Matching between side A and side B of the same input.
(7) Voltage produced by the DDC232 at its input that is applied to the sensor.
Copyright © 2004–2010, Texas Instruments Incorporated Submit Documentation Feedback 3

DDC232
ELECTRICAL CHARACTERISTICS (continued)

At TA = +25°C, AVDD = +5V, DVDD = +3.0V, VREF = +4.096V, tINT = 333ms for DDC232C or 166ms for
DDC232CK,
Range 7, and continuous mode operation, unless otherwise noted.
DDC232C DDC232CK
PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNIT
PERFORMANCE OVER TEMPERATURE
Offset Drift ±0.5 5 (8) ±0.5 5 (8) ppm of FSR/°C
Offset Drift Stability ±0.2 2 (8) ±0.2 2 (8) ppm of FSR/minute
DC Bias Voltage Drift (9) ±3 ±3 mV/°C
Input Bias Current Drift TA = +25°C to +45°C 0.01 1 (8) 0.01 1 (8) pA/°C
Range Drift (10) 25 50 25 50 ppm/°C
Range Drift Match (11) ±5 ±5 ppm/°C
REFERENCE
Voltage 4.000 4.096 4.200 4.000 4.096 4.200 V
Input Current (12) Average Value with tINT = 333ms 325 mA
Average Value with tINT = 166.5ms 650 mA
DIGITAL INPUT/OUTPUT
Logic Levels
VIH 0.8 DVDD DVDD + 0.1 0.8 DVDD DVDD + 0.1 V
VIL –0.1 0.2 DVDD –0.1 0.2 DVDD V
VOH IOH = –500mA DVDD – 0.4 DVDD – 0.4 V
VOL IOL = 500mA 0.4 0.4 V
Input Current (IIN) 0 < VIN < DVDD ±10 ±10 mA
Data Format (13) Straight Binary Straight Binary
POWER-SUPPLY REQUIREMENTS
Analog Power-Supply Voltage (AVDD) 4.75 5.0 5.25 4.9 5.0 5.1 V
Digital Power-Supply Voltage (DVDD) 2.7 3.0 3.6 2.7 3.0 3.6 V
Supply Current
Analog Current 41 60 mA
Digital Current 3.7 8.0 mA
Total Power Dissipation 224 288 290 mW
Per Channel Power Dissipation 7 9 10 mW/Channel
(8) Ensured by design, not production tested.

(9) Voltage produced by the DDC232 at its input that is applied to the sensor.
(10) Range drift does not include external reference drift.
(11) Matching between side A and side B of the same input.
(12) Input reference current decreases with increasing tINT (see the Voltage Reference section, page 10).
(13) Data format is Straight Binary with a small offset. The number of bits in the output word is controlled by the Format bit.

DDC232
PIN CONFIGURATION
Top View BGA

Columns
H G F E D C B A
IN21 IN22 IN23 IN24 IN25 IN26 IN27 IN28

1

2

3

4
Rows
QGND AGND AGND AGND AGND AGND AGND AGND
5
AGND AVDD AVDD AVDD AGND DGND VREF VREF

6
DVALID DIN_CFG CLK_CFG DGND DGND RESET DVDD DGND

7
DCLK DGND CLK NC DOUT DGND DIN CONV

8
PIN DESCRIPTIONS
PIN LOCATION FUNCTION DESCRIPTION
IN1–32 Rows 1–4 Analog Input Analog Inputs for Channels 1 to 32
QGND H5 Analog Quiet Analog Ground
AGND G5, F5, E5, D5, C5, B5, A5, D6, H6 Analog Analog Ground
DGND A7, C6, D7, E7, C8, G8 Digital Digital Ground
AVDD E6, F6, G6 Analog Analog Power Supply, +5V Nominal
VREF A6, B6 Analog Input External Voltage Reference Input, +4.096V Nominal
DVALID H7 Digital Output Data Valid Output, Active Low
DIN_CFG G7 Digital Input Configuration Register Data Input
CLK_CFG F7 Digital Input Configuration Register Clock Input
RESET C7 Digital Input Digital Reset, Active Low
DVDD B7 Digital Digital Power Supply, 3.3V Nominal
CONV A8 Digital Input Conversion Control Input; 0 = Integrate on Side B, 1 = Integrate on Side A
DIN B8 Digital Input Serial Data Input
DOUT D8 Digital Output Serial Data Output
NC E8 No Connect Do not connect; must be left floating.
CLK F8 Digital Input Master Clock Input
DCLK H8 Digital Input Serial Data Clock Input

DDC232
TYPICAL CHARACTERISTICS
At TA = +25°C, unless otherwise indicated.
NOISE vs CSENSOR
150
140
130
120
Noise (ppm of FSR, rms)

110 Range 1
100
90
80
70
60 Range 2
50
40
30
20
10 Range 7
0
0 100 200 300 400 500 600 700 800 900 1000
CSENSOR (pF)
Figure 1.
Table 1. NOISE vs CSENSOR (ppm of FSR, rms)

NOISE (ppm of FSR, rms)
CSENSOR
(pF) Range 0 Range 1 Range 2 Range 3 Range 4 Range 5 Range 6 Range 7
0 27 9.1 6.3 5.5 5.2 5 4.9 4.8
22 38 12 7.9 6.5 5.8 5.5 5.3 5.1
47 51 15 9.8 7.7 6.7 6.1 5.8 5.5
68 59 18 11 8.5 7.3 6.6 6.1 5.8
100 74 22 13 9.9 8.3 7.4 6.8 6.3
150 100 29 16 12 10 8.7 7.8 7.2
330 180 50 27 19 15 13 11 10
470 250 67 36 25 19 16 14 12
1000 520 130 57 49 37 30 26 22
Table 2. NOISE vs CSENSOR (fC, rms)

NOISE (fC, rms)
CSENSOR
0 0.34 0.46 0.63 0.83 1.04 1.25 1.47 1.68
22 0.48 0.60 0.79 0.98 1.16 1.38 1.59 1.79
47 0.64 0.75 0.98 1.16 1.34 1.53 1.74 1.93
68 0.74 0.90 1.10 1.28 1.46 1.65 1.83 2.03
100 0.93 1.10 1.30 1.49 1.66 1.85 2.04 2.21
150 1.25 1.45 1.60 1.80 2.00 2.18 2.34 2.52
330 2.25 2.50 2.70 2.85 3.00 3.25 3.30 3.50
470 3.13 3.35 3.60 3.75 3.80 4.00 4.20 4.20
1000 6.50 6.50 5.70 7.35 7.40 7.50 7.80 7.70
Table 3. NOISE vs CSENSOR (electrons, rms)

NOISE (electrons, rms)
CSENSOR
0 2100 2840 3930 5140 6490 7800 9170 10400
22 2960 3740 4930 6080 7240 8580 9920 11100
47 3970 4680 6110 7200 8360 9510 10800 12000
68 4600 5610 6860 7950 9110 10200 11400 12600
100 5770 6860 8110 9260 10300 11500 12700 13700
150 7800 9050 9980 11200 12400 13500 14600 15700
330 14000 15600 16800 17700 18700 20200 20500 21800
470 19500 20900 22400 23400 23700 24900 26200 26200
1000 40500 40500 35500 45800 46100 46800 48600 48000

DDC232
THEORY OF OPERATION
GENERAL DESCRIPTION
converters via multiplexers. With the DDC232 in the
The block diagram of the DDC232 is shown in continuous integration mode, the output of the
Figure 2. The device contains 32 identical input integrators from one side of the inputs will be digitized
channels that perform the function of while the other 32 integrators are in the integration
current-to-voltage integration followed by a mode. This integration and A/D conversion process is
multiplexed A/D conversion. Each input has two controlled by the system clock, CLK. The results from
integrators so that the current-to-voltage integration side A and side B of each signal input are stored in a
can be continuous in time. The output of the 64 serial output shift register. The DVALID output goes
integrators are switched to 16 delta-sigma (∆Σ) low when the shift register contains valid data.
AVDD VREF DVDD
0.1mF
0.1mF 0.1mF
Dual
Switched CLK
IN1 Integrator
DS CONV
ADC Configuration
and DIN_CFG
Dual
Switched Control
IN2 Integrator CLK_CFG
RESET
Dual
Switched
IN3 Integrator
DS
ADC
Dual DVALID
Switched
IN4 Integrator
Dual
DCLK
Switched
IN29 Integrator
Serial
DS
Interface
ADC
Dual
Switched
IN30 Integrator DOUT
Dual
Switched
IN31 Integrator
DS DIN
ADC
Dual
Switched
IN32 Integrator
AGND DGND
Figure 2. DDC232 Block Diagram

DDC232
DEVICE OPERATION operational amplifier. At the beginning of a

conversion, the switches SA/D, SINTA, SINTB, SREF1,
Basic Integration Cycle SREF2, and SRESET are set (see Figure 4).
The topology of the front end of the DDC232 is an At the completion of an A/D conversion, the charge
analog integrator as shown in Figure 3. In this on the integration capacitor (CF) is reset with SREF1
diagram, only input IN1 is shown. The input stage and SRESET (see Figure 4 and Figure 5a). This is
consists of an operational amplifier, a selectable done during reset. In this manner, the selected
feedback capacitor network (CF), and several capacitor is charged to the reference voltage, VREF.
switches that implement the integration cycle. The Once the integration capacitor is charged, SREF1 and
timing relationships of all of the switches shown in SRESET are switched so that VREF is no longer
Figure 3 are illustrated in Figure 4. Figure 4 connected to the amplifier circuit while it waits to
conceptualizes the operation of the integrator input begin integrating (see Figure 5b). With the rising
stage of the DDC232 and should not be used as an edge of CONV, SINTA closes, which begins the
exact timing tool for design. integration of side A. This process puts the integrator
stage into its integrate mode (see Figure 5c).
See Figure 5 for the block diagrams of the reset,
integrate, wait, and convert states of the integrator Charge from the input signal is collected on the
section of the DDC232. This internal switching integration capacitor, causing the voltage output of
network is controlled externally with the convert pin the amplifier to decrease. The falling edge of CONV
(CONV) and the system clock (CLK). For the best stops the integration by switching the input signal
noise performance, CONV must be synchronized with from side A to side B (SINTA and SINTB). Prior to the
the rising edge of CLK. It is recommended that CONV falling edge of CONV, the signal on side B was
toggle within ±10ns of the rising edge of CLK. converted by the A/D converter and reset during the
time that side A was integrating. With the falling edge
The noninverting inputs of the integrators are of CONV, side B starts integrating the input signal. At
connected to ground. Consequently, the DDC232 this point, the output voltage of the side A operational
analog ground should be as clean as possible. In amplifier is presented to the input of the ∆Σ A/D
Figure 3, the feedback capacitors (CF) are shown in converter (see Figure 5d).
parallel between the inverting input and output of the
Adjustable Feedback Capacitors (CF)

SREF1
3pF VREF
50pF
Range[2] Bit
25pF
Range[1] Bit
12.5pF
Range[0] Bit
Input SINTA SREF2

Current IN1 SADC1A
SRESET To Converter
ESD
Protection Integrator B (same as A)
SINTB
Photodiode Diodes
Integrator A
Figure 3. Basic Integration Configuration for Input 1

DDC232
CONV
CLK
SINTA
SINTB
SREF1
SREF2
SRESET
SA/D1A
Configuration of
Reset
Reset
W a it
W a it
Convert Wait Integrate Convert Wait
Integrator A
VREF
Integrator A
Voltage Output
Figure 4. Integration Timing (see Figure 3)
CF SREF1
VREF
SINT
SREF2 SREF1
IN CF
SRESET To Converter VREF

SA/D SINT
SREF2
IN
SRESET To Converter
a) Reset Configuration SA/D
CF SREF1
VREF b) Wait Configuration
SINT SREF2
CF SREF1
IN
To Converter VREF
SRESET
SA/D SINT
SREF2
IN
SRESET To Converter
c) Integrate Configuration SA/D
d) Convert Configuration
Figure 5. Four Configurations of the Front-End Integrators

DDC232
charge needed by the ∆Σ converter. For an

Integration Capacitors integration time of 333ms, this charge translates to an
There are seven different capacitors available on-chip average VREF current of approximately 325mA. The
for both sides of every channel in the DDC232. These amount of charge needed by the ∆Σ converter is
internal capacitors are trimmed in production to independent of the integration time; therefore,
achieve the specified performance for range error of increasing the integration time lowers the average
the DDC232. The range control bits (Range[2:0]) current. For example, an integration time of 800ms
change the capacitor value for all integrators. lowers the average VREF current to 135mA.
Consequently, all inputs and both sides of each input It is critical that VREF be stable during the different
will always have the same full-scale range. Table 4 modes of operation (see Figure 5). The ∆Σ converter
shows the capacitor value selected for each range measures the voltage on the integrator with respect
selection. to VREF. Since the integrator capacitors are initially
reset to VREF, any drop in VREF from the time the
Table 4. Range Selection capacitors are reset to the time when the converter
RANGE CONTROL BITS INPUT measures the integrator output will introduce an
CF RANGE offset. It is also important that VREF be stable over
RANGE Range[2] Range[1] Range[0] (pF, typ) (pC, typ)
longer periods of time because changes in VREF
0 0 0 0 3 –0.04 to 12.5 correspond directly to changes in the full-scale range.
1 0 0 1 12.5 –0.2 to 50 Finally, VREF should introduce as little additional
2 0 1 0 25 –0.4 to 100 noise as possible.
3 0 1 1 37.5 –0.6 to 150
For these reasons, it is strongly recommended that
4 1 0 0 50 –0.8 to 200
the external reference source be buffered with an
5 1 0 1 62.5 –0.1 to 250 operational amplifier, as shown in Figure 6. In this
6 1 1 0 75 –1.2 to 300 circuit, the voltage reference is generated by a
7 1 1 1 87.5 –1.4 to 350 +4.096V reference. A low-pass filter to reduce noise
connects the reference to an operational amplifier
Voltage Reference configured as a buffer. This amplifier should have low
noise and input/output common-mode ranges that
The external voltage reference is used to reset the support VREF. Even though the circuit in Figure 6
integration capacitors before an integration cycle might appear to be unstable due to the large output
begins. It is also used by the ∆Σ converter while the capacitors, it works well for most operational
converter is measuring the voltage stored on the amplifiers. It is not recommended that series
integrators after an integration cycle ends. During this resistance be placed in the output lead to improve
sampling, the external reference must supply the stability since this can cause a drop in VREF, which
produces large offsets.
+5V
+5V
0.10mF
0.47mF
7
2
1
6 To VREF Pin on
10kW OPA350
2 3 the DDC232
REF3140 +
+ 10mF
10mF 0.10mF 4
3
Figure 6. Recommended External Voltage Reference Circuit for Best Low-Noise Operation

DDC232
Frequency Response CONFIGURATION REGISTER

The frequency response of the DDC232 is set by the Some aspects of device operation are controlled by
front-end integrators and is that of a traditional the onboard configuration register. The DIN_CFG,
continuous time integrator, as shown in Figure 7. By CLK_CFG, and RESET pins are used to write to this
adjusting tINT, the user can change the 3dB register. When beginning a write operation, hold
bandwidth and the location of the notches in the CONV low and strobe RESET; see Figure 8. Then
response. The frequency response of the ∆Σ begin shifting in the configuration data on DIN_CFG.
converter that follows the front-end integrator is of no Data are written to the configuration register most
consequence because the converter samples a held significant bit first. The data are internally latched on
signal from the integrators. That is, the input to the the falling edge of CLK_CFG. Partial writes to the
∆Σ converter is always a DC signal. Since the output configuration register are not allowed—make sure to
of the front-end integrators are sampled, aliasing can send all 12 bits when updating the register.
occur. Whenever the frequency of the input signal
exceeds one-half of the sampling rate, the signal will Optional readback of the configuration register is
fold back down to lower frequencies. available immediately after the write sequence.
During readback, the 12-bit configuration data
0
followed by a 4-bit revision ID and the test pattern are
shifted out on the DOUT pin on the rising edge of
DCLK.
−10
NOTE: Wth Format = 1, the test pattern is 304 bits,
with only the last 72 bits non-zero. This sequence of
Gain (dB)
−20
outputs is repeated twice for each DDC232 and
daisy-chaining is supported in configuration readback.
−30 Table 5 shows the test pattern configuration during
readback. Table 6 shows the timing for the
−40 configuration register read and write operations.
Strobe CONV to begin normal operation.
−50
0.1 1 10 100 Table 5. Test Pattern During Readback
tINT tINT tINT tINT
TEST PATTERN TOTAL
Frequency Format BIT (Hex) READBACK BITS
0 30F066012480F6h 512
Figure 7. Frequency Response 1 30F066012480F69055h 640

DDC232
tRST
RESET Configuration Register Operations Normal Operation
tWTRST
tWTWR
CLK_CFG
t STCF
t HDCF
DIN_CFG MSB LSB
Read Configuration Register

Write Configuration Register Data and Test Pattern
DCLK
DOUT MSB LSB
Configuration Test Pattern

Register
Data
CONV
NOTE: CLK must be running during Configuration Register write and read operations.
Figure 8. Configuration Register Write and Read Operations
Table 6. Timing for the Configuration Register Read/Write

SYMBOL DESCRIPTION MIN TYP MAX UNITS
tWTRST Wait Required from Reset High to First Rising Edge of CLK_CFG 2 ms
Wait Required from Last CLK-CFG of Write Operation to
tWTWR 2 ms
First CLK_CFG of Read Operation
tSTCF Set-Up Time from DIN_CFG to Falling Edge of CLK_CFG 10 ns
tHDCF Hold Time for DIN_CFG After Falling Edge of CLK_CFG 10 ns
tRST Pulse Width for RESET Active 1 ms

DDC232
Table 7. Configuration Register

Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Range[2] Range[1] Range[0] Format Version Clk_4x 0 0 0 0 0 Test
Bits 11–9 Range[2:0]. Full-scale range.

000: 12.5pC 100: 200pC
001: 50pC 101: 250pC
010: 100pC 110: 300pC
011: 150pC 111: 350pC (default)
Bit 8 Format. Data output format. This bit selects how many bits are used in the data output word.
0: 16-Bit Output
1: 20-Bit Output (default)
Bit 7 Version. Device version setting.
Must be set to '0' for DDC232C
Must be set to '1' for DDC232CK
Bit 6 Clk_4x. System clock divider. The Clk_4x input enables an internal divider on the system clock.
When Clk_4x = 1, the system clock is divided by 4. This allows a 4X faster system clock, which
in turn provides a finer quantization of the integration time because the CONV signal needs to be
synchronized with the system clock for the best performance.
0: Internal Clock Divider = 1 (default)
1: Internal Clock Divider = 4
Clk_4x BIT CLK DIVIDER VALUE CLK FREQUENCY INTERNAL CLOCK FREQUENCY
0 1 5MHz 5MHz
1 4 20MHz 5MHz
Bits 5–1 These bits must be set to '0'.

Bit 0 Test. Diagnostic test mode enable. When Test mode is used, the inputs (IN1 through IN32) are
disconnected from the DDC232 integrators to enable the user to measure a zero input signal
regardless of the current supplied to the inputs. Test mode works with both Continuous and
Noncontinuous modes.
0: Test Mode Off (default)
1: Test Mode On

DDC232
DIGITAL INTERFACE DVALID eliminates any concern about this

relationship. If the data read back is timed from
The digital interface of the DDC232 outputs the digital CONV, make sure to wait for the required amount of
results via a synchronous serial interface consisting time. For Continuous mode, this time is given by
of a data clock (DCLK), a valid data pin (DVALID), a tCMDR. For Noncontinuous mode, use tNCDR1 or tNCDR2,
serial data output pin (DOUT), and a serial data input as appropriate. See Table 9 for details.
pin (DIN). The integration and conversion process is
fundamentally independent of the data retrieval Reset (RESET)
process. Consequently, the CLK and DCLK
frequencies need not be the same, though for best The DDC232 is reset asynchronously by taking the
performance, it is highly recommended that they be RESET input low, as shown in Figure 9. Make sure
derived from the same clocking source to keep the the release pulse is at least 1ms wide. After resetting
phase relationship constant. DIN is only used when the DDC232, wait at least four conversions before
multiple converters are cascaded and should be tied using the data. It is very important that RESET is
to DGND otherwise. Depending on tINT, CLK, and glitch-free to avoid unintentional resets.
DCLK, it is possible to daisy-chain multiple
converters. This greatly simplifies the interconnection
and routing of the digital outputs in those applications
where a large number of converters are needed. RESET > 1µs
Configuration of the DDC232 is set by a dedicated
register addressed using the DIN_CFG and
CLK_CFG pins.
Figure 9. Reset Timing
System and Data Clocks (CLK and CONV)
The system clock is supplied to CLK and the data Conversion Rate
clock is supplied to DCLK. It is recommended that the
CLK pin be driven by a free-running clock source The conversion rate of the DDC232 is set by a
(that is, do not start and stop CLK between combination of the integration time (determined by
conversions). Make sure the clock signals are the user) and the speed of the A/D conversion
clean—avoid overshoot or ringing. For best process. The A/D conversion time is primarily a
performance, generate both clocks from the same function of the system clock (CLK) speed. One A/D
clock source. DCLK should be disabled by taking it conversion cycle encompasses the conversion of two
low after the data has been shifted out or while signals (one side of each dual integrator feeding the
CONV is transitioning. modulator) and the reset time for each of the
integrators involved in the two conversions. In most
When using multiple DDC232s, pay close attention to situations, the A/D conversion time is shorter than the
the DCLK distribution on the printed circuit board integration time. If this condition exists, the DDC232
(PCB). In particular, make sure to minimize skew in will operate in the continuous mode. When the
the DCLK signal because this can lead to timing DDC232 is in the continuous mode, the sensor output
violations in the serial interface specifications. See is continuously integrated by one of the two sides of
the Cascading Multiple Converters section for more each input.
details.
In the event that the A/D conversion takes longer
Data Valid (DVALID) than the integration time, the DDC232 will switch into
a Noncontinuous mode. In Noncontinuous mode, the
The DVALID signal indicates that data are ready. A/D converter is not able to keep pace with the speed
Data retrieval may begin after DVALID goes low. This of the integration process. Consequently, the
signal is generated using an internal clock divided integration process is periodically halted until the
down from the system clock, CLK. The phase digitizing process catches up. These two basic modes
relationship between this internal clock and CLK is of operation for the DDC232—Continuous and
set when power is first applied and is random. Since Noncontinuous modes—are described below.
the user must synchronize CONV with CLK, the
DVALID signal will have a random phase relationship
with CONV. This uncertainty is ±1/fCLK. Polling

DDC232
Continuous and Noncontinuous Operational Four signals are used to control progression around
Modes the state diagram: CONV, mbsy, and their
Figure 10 shows the state diagram of the DDC232. In complements. The state machine uses the level as
all, there are eight states. Table 8 provides a brief opposed to the edges of CONV to control the
explanation of each state. progression. mbsy is an internally-generated signal
not available to the user. It is active whenever a
measurement/reset/auto-zero (m/r/az) cycle is in
progress.
During the Continuous (Cont) mode, mbsy is not
CONV|mbsy active when CONV toggles. The nonintegrating side
1 2 is always ready to begin integrating when the other
CONV • mbsy
side finishes its integration. Consequently, monitoring
Ncont Ncont the current status of CONV is all that is needed to
know the current state. Cont mode operation
CONV corresponds to states 3 to 6. Two of the states, 3 and
3 6, only perform an integration (that is, no m/r/az
CONV • mbsy
Int A cycle).
CONV Cont
mbsy becomes important when operating in the
4 5 Noncontinuous (Ncont) mode (states 1, 2, 7, and 8).
CONV • mbsy
Whenever CONV is toggled while mbsy is active, the
Int B/Meas A Int A/Meas B DDC232 will enter or remain in either Ncont state 1
Cont CONV • mbsy Cont
(or 8). After mbsy goes inactive, state 2 (or 7) is
entered. This state prepares the appropriate side for
CONV
6 integration. In the Ncont states, the inputs to the
CONV • mbsy DDC232 are grounded.
Int B
Cont
CONV One interesting observation from the state diagram is
that the integrations always alternate between sides
7 8 A and B. This relationship holds for any CONV
Ncont
pattern and is independent of the mode. States 2 and
CONV • mbsy Ncont
7 ensure this relationship during the Ncont mode.
CONV|mbsy When power is first applied to the DDC232, the
beginning state is either 1 or 8, depending on the
State Diagram Notation: initial level of CONV. For CONV held high at
CONV • mbsy = CONV high AND mbsy active. power-up, the beginning state is 1. Conversely, for
CONV|mbsy = CONV high OR mbsy active. CONV held low at power-up, the beginning state is 8.
In general, there is a symmetry in the state diagram
between states 1–8, 2–7, 3–6, and 4–5. Inverting
Figure 10. Integrate/Measure State Diagram CONV results in the states progressing through their
symmetrical match.
Table 8. State Descriptions

STATE MODE DESCRIPTION
Complete m/r/az of side A, then side B (if previous state is state 4). Initial power-up state
1 Ncont
when CONV is initially held high.
2 Ncont Prepare side A for integration.
3 Cont Integrate on side A.
4 Cont Integrate on side B; m/r/az on side A.
5 Cont Integrate on side A; m/r/az on side B.
6 Cont Integrate on side B.
7 Ncont Prepare side B for integration.
Complete m/r/az of side B, then side A (if previous state is state 5). Initial power-up state
8 Ncont
when CONV is initially held low.

DDC232
TIMING EXAMPLES
top signal is CONV and is supplied by the user. The
Continuous Mode next line indicates the current state in the state
A few timing diagrams help illustrate the operation of diagram. The following two traces show when
the integrate/measure state machine. These integrations and measurement cycles are underway.
diagrams are shown in Figure 11 through Figure 16. The internal signal mbsy is shown next. Finally,
Table 9 gives generalized timing specifications in DVALID is given. As described in the data sheet,
units of CLK periods for Clk_4x = 0. If Clk_4x = 1, DVALID goes active low when data are ready to be
these values increase by a factor of 4 because of the retrieved from the DDC232. It stays low until DCLK is
internal clock divider. Values (in ms) for Table 9 can taken high and then back low by the user. The text
be easily found for a given CLK. below the DVALID pulse indicates the side of the
data available to be read and arrows help match the
Figure 11 shows a few integration cycles beginning data to the corresponding integration.
with initial power-up for a Cont mode example. The
CONV
State 8 7 6 5 4 5
Integration
Integrate B Integrate A Integrate B Integrate A
Status
m/r/az
Status m/r/az B m/r/az A m/r/az B
tMRAZ
mbsy
DVALID tCMDR
t=0
Side B Side A Side B
Power−Up
Data Data Data
Figure 11. Continuous Mode Timing
Table 9. Timing Specifications Generalized in CLK Periods

VALUE
(CLK Periods with Clk_4x = 0)
SYMBOL DESCRIPTION DDC232C DDC232CK
tMRAZ Continuous mode, m/r/az cycle 1552 ± 2 1612 ± 2
tCMDR Continuous mode, data ready 1382 ± 2 1382 ± 2

DDC232
In Figure 11, the first state is Ncont state 8. The Ncont modes described earlier in the Continuous and
DDC232 always powers up in the Ncont mode. In this Noncontinuous Operational Modes section. DVALID
case, the first state is 8 because CONV is initially goes low after CONV toggles in time tCMDR, indicating
low. After the first two states, Cont mode operation is that data are ready to be retrieved.
reached and the states begin toggling between 4 and
See Figure 12 for the timing diagram of the internal
5. From now on, the input is being continuously
operations occurring during Continuous mode
integrated, either on side A or side B. The time
operation. Table 10 gives the timing specifications of
needed for the m/r/az cycle, tMRAZ, is the same time
the internal operations occurring during Continuous
that determines the boundary between the Cont and
mode operation.
End Integration Side A End Integration Side B End Integration Side A

Start Integration Side B Start Integration Side A Start Integration Side B
tINT
CONV t INT
Side A Side B Side A

A/D Conversion
tADCONV
Odd Channels (Internal)
Side A tADRST Side B

A/D Conversion
Even Channels (Internal) tADCONV
tADRST tIRST t IRST
DVALID
Side A Side B
Data Ready Data Ready
Figure 12. Internal Operation in Continuous Mode Timing
Table 10. Timing Characteristics for the Internal Operation in Continuous Mode
DDC232C DDC232CK
(CLK = 5MHz, Clk_4x = 0) (CLK = 10MHz, Clk_4x = 0)
SYMBOL DESCRIPTION MIN TYP MAX MIN TYP MAX UNITS
tINT Integration Period (continuous mode) 320 1,000,000 160 1,000,000 ms
tADCONV A/D Conversion Time (internally controlled) 135.6 68 ms
tADRST A/D Conversion Reset Time (internally controlled) 3.2 2.2 ms
tIRST Integrator Reset Time (internally controlled) 36 21.8 ms

DDC232
Noncontinuous Mode
Figure 13 and Figure 14 illustrate operation in Noncontinuous mode.
Start Integration Side A Start Integration Side A

End Integration Side A
Start Integration Side B
End Integration Side B Release
Wait State State
tINT
CONV
tINT tNCRL
A/D Conversion
Odd Channels tADCONV
A/D Conversion
Even Channels tADCONV
tADRST tNCIRST
DVALID
Side A Data Ready Side B Data Ready
t NCDR1 tNCDR2
Figure 13. Conversion Detail for the Internal Operation of Noncontinuous Mode
with Side A Integrated First
Table 11. Timing Characteristics for the Internal Operation in Noncontinuous Mode
DDC232C DDC232CK
(CLK = 5MHz, Clk_4x = 0) (CLK = 10MHz, Clk_4x = 0)
SYMBOL DESCRIPTION MIN TYP MAX MIN TYP MAX UNITS
tINT Integration Time (Noncontinuous mode) 50 1,000,000 50 1,000,000 ms
tADCONV A/D Conversion Time (internally controlled) 135.6 67.8 ms
tADRST A/D Conversion Reset Time (internally controlled) 3.2 1.6 ms
Noncontinuous Mode Integrator Reset Time (internally ms
tNCIRST 30.4 15.2
controlled)
tNCRL Release Time 0.4 0.2 ms
tNCDR1 1st Noncontinuous Mode Data Ready 276.5 138.2 ms
tNCDR2 2nd Noncontinuous Mode Data Ready 304.8 152.4 ms
BLANKSPACE
Start Integration Side B Start Integration Side B

End Integration Side B
Start Integration Side A
Release
End Integration Side A
State
Wait State
tINT
CONV
tINT
tNCRL
A/D Conversion
Odd Channels tADCONV
A/D Conversion
Even Channels t ADCONV
t ADRST tNCIRST
DVALID
Side B Data Ready Side A Data Ready
Figure 14. Internal Operation Noncontinuous Mode Timing with Side B Integrated First

DDC232
is increased so that tINT is always ≥ tMRAZ as shown in

Changing Between Modes Figure 16 (see Figure 13 and Table 11, page 18).
Changing from Cont to Ncont mode occurs whenever With a longer tINT, the m/r/az cycle has enough time
tINT < tMRAZ. Figure 15 shows an example of this to finish before the next integration begins and
transition. In this figure, Cont mode is entered when continuous integration of the input signal is possible.
the integration on side A is completed before the For the special case of the very first integration when
m/r/az cycle on side B is complete. The DDC232 changing to the Cont mode, tINT can be < tMRAZ. This
completes the measurement on sides B and A during is allowed because there is no simultaneous m/r/az
states 8 and 7 with the input signal shorted to ground. cycle on the side B during state 3—therefore, there is
Ncont integration begins with state 6. no need to wait for it to finish before ending the
integration on side A.
Changing from Ncont to Cont mode occurs when tINT
CONV
State 5 4 5 8 7 6 5
Continuous Noncontinuous
Integration
Status Integrate A Integrate B Int A Int B Int A
m/r/az
m/r/az B m/r/az A m/r/az B m/r/az A m/r/az B
Status
mbsy
Figure 15. Changing from Continuous Mode to Noncontinuous Mode
CONV
State 3 4 1 2 3 4
Noncontinuous Continuous
Integration
Int A Int B Integrate A Integrate B
Status
m/r/az
Status m/r/az A m/r/az B m/r/az A
mbsy
Figure 16. Changing from Noncontinuous Mode to Continuous Mode

DDC232
DATA FORMAT Table 12. Ideal Output Code (1) vs Input Signal
The serial output data are provided in an offset binary INPUT IDEAL OUTPUT CODE IDEAL OUTPUT CODE
SIGNAL FORMAT = 1 FORMAT = 0
code as shown in Table 12. The Format bit in the
≥ 100% FS 1111 1111 1111 1111 1111 1111 1111 1111 1111
configuration register selects how many bits are used
in the output word. When Format = 1, 20 bits are 0.001531% FS 0000 0001 0000 0001 0000 0000 0001 0000 0001
used. When Format = 0, the lower 4 bits are 0.001436% FS 0000 0001 0000 0000 1111 0000 0001 0000 0000
truncated so that only 16 bits are used. Note that the 0.000191% FS 0000 0001 0000 0000 0010 0000 0001 0000 0000
LSB size is 16 times bigger when Format = 0. An 0.000096% FS 0000 0001 0000 0000 0001 0000 0001 0000 0000
offset is included in the output to allow slightly 0% FS 0000 0001 0000 0000 0000 0000 0001 0000 0000
negative inputs (for example, from board leakages) –0.3955% FS 0000 0000 0000 0000 0000 0000 0000 0000 0000
from clipping the reading. This offset is approximately
0.4% of the positive full-scale. (1) Excludes the effects of noise, INL, offset, and gain errors.
BLANKSPACE
DATA RETRIEVAL
Make sure not to retrieve data around changes in
In both the Continuous and Noncontinuous modes of CONV because this can introduce noise. Stop activity
operation, the data from the last conversion are on DCLK at least 10ms before or after a CONV
available for retrieval on the falling edge of DVALID transition.
(see Figure 17 and Table 13). Data are shifted out on
Setting the Format bit = 0 (16-bit output word) will
the falling edge of the data clock, DCLK.
reduce the time needed to retrieve data by 20% since
there are fewer bits to shift out. This can be useful in
multichannel systems requiring only 16 bits of
resolution.
CLK
tPDCDV
DVALID
tHDDODV tPDDCDV
DCLK
tHDDODC tPDDCDO
Input Input
Input 32 Input 5 Input 4 Input 2 Input 1 Input 1 Input 32
DOUT 32 31
MSB LSB MSB LSB MSB LSB MSB
LSB MSB
Figure 17. Digital Interface Timing for Data Retrieval From a Single DDC232
Table 13. Timing for DDC232 Data Retrieval

tPDCDV Propagation Delay from Falling Edge of CLK to DVALID Low 10 ns
tPDDCDV Propagation Delay from Falling Edge of DCLK to DVALID High 5 ns
tHDDODV Hold Time that DOUT is Valid Before the Falling Edge of DVALID 400 ns
tHDDODC Hold Time that DOUT is Valid After Falling Edge of DCLK 4 ns
(1)
tPDDCDO Propagation Delay from Falling Edge of DCLK to Valid DOUT 25 ns
(1) With a maximum load of one DDC232 (4pF typical) with an additional load of 5pF.

DDC232
Cascading Multiple Converters Figure 19 shows the timing diagram when the DIN
input is used to daisy-chain several devices. Table 14
Multiple DDC232 units can be connected in serial
gives the timing specification for data retrieval using
configuration; see Figure 18.
DIN.
DOUT can be used with DIN to daisy-chain multiple
DDC232 devices together to minimize wiring. In this
mode of operation, the serial data output is shifted
through multiple DDC232s; see Figure 18.
Data Clock
DVALID
DVALID
DVALID
DVALID
DCLK
DCLK
DCLK
DCLK
Data
Retrieval DOUT DDC232 DIN DOUT DDC232 DIN DOUT DDC232 DIN DOUT DDC232 DIN
Output
IN32
IN31
IN30
IN29
IN32
IN31
IN30
IN29
IN32
IN31
IN30
IN29
IN32
IN31
IN30
IN29
IN4
IN3
IN2
IN1
IN4
IN3
IN2
IN1
IN4
IN3
IN2
IN1
IN4
IN3
IN2
IN1
128
127
126
125
100
99
98
97
96
95
94
93
68
67
66
65
64
63
62
61
36
35
34
33
32
31
30
29
4
3
2
1
Sensor
Figure 18. Daisy-Chained DDC232s
CLK
DVALID
DCLK
tSTDIDC tHDDIDC
DIN
Input Input Input Input

Input 3 Input 2 Input 2 Input 1 Input 1
DOUT 128 128 127 128
LSB MSB LSB MSB LSB
MSB LSB MSB MSB
Figure 19. Timing When Using DDC232 DIN Function; See Figure 18
Table 14. Timing for DDC232 Data Retrieval Using DIN

tSTDIDC Set-Up Time from DIN to Falling Edge of DCLK 10 ns
tHDDIDC Hold Time for DIN After Falling Edge of DCLK 10 ns

DDC232
RETRIEVAL BEFORE CONV TOGGLES t INT * ǒt CMDR ) t SDCVǓ

(CONTINUOUS MODE) (20 32)t DCLK (1)
Data retrieval before CONV toggles is the most
straightforward method. Data retrieval begins soon NOTE: (16 × 32)tDCLK is used for Format = 0, where
after DVALID goes low and finishes before CONV tDCLK is the period of the data clock. For example, if
toggles, as shown in Figure 20. For best tINT = 1000ms and DCLK = 10MHz, the maximum
performance, data retrieval must stop tSDCV before number of DDC232s with Format = 1 is shown in
CONV toggles. This method is most appropriate for Equation 2:
longer integration times. The maximum time available 1000ms * 286.8ms
+ 11.14 ³ 11 DDC232
for readback is tINT – tCMDR – tSDCV. (640)(100ns) (2)
For DCLK = 10MHz and CLK = 5MHz, the maximum (or 13 for Format = 0)
number of DDC232s that can be daisy-chained
together (Format = 1) is calculated by Equation 1:
CONV tINT tINT
DVALID t CMDR
tSDCV
DCLK … …
DOUT … …
Side B Side A
Data Data
Figure 20. Readback Before CONV Toggles
Table 15. Timing Characteristics for Readback

tSDCV Data Retrieval Shutdown Before or After Edge of CONV 10 ms

DDC232
RETRIEVAL AFTER CONV TOGGLES 266ms

(CONTINUOUS MODE) (20 32)t DCLK (3)
For shorter integration times, more time is available if NOTE: (16 × 32)tDCLK is for Format = 0.
data retrieval begins after CONV toggles and ends
before the new data are ready. Data retrieval must For DCLK = 10MHz, the maximum number of
wait tSDCV after CONV toggles before beginning. See DDC232s is four (or five for Format = 0).
Figure 21 for an example of this. The maximum time
available for retrieval is tCMDR – (tSDCV + tHDDODV),
regardless of tINT. The maximum number of DDC232s
that can be daisy-chained together with Format = 1 is
calculated by Equation 3:
CONV tINT tINT tINT
DVALID
tCMDR
tSDCV tHDDODV
DCLK … … …
DOUT … … …
Side A Side B Side A
Data Data Data
Figure 21. Readback After CONV Toggles

DDC232
RETRIEVAL BEFORE AND AFTER CONV t INT * ǒt SDCV ) t SDCV ) t HDDODVǓ

TOGGLES (CONTINUOUS MODE) (20 32)t DCLK (4)
For the absolute maximum time for data retrieval,
data can be retrieved before and after CONV toggles. NOTE: (16 × 32)tDCLK is used for Format = 0.
Nearly all of tINT is available for data retrieval. For tINT = 400ms and DCLK = 10MHz, the maximum
Figure 22 illustrates how this is done by combining number of DDC232s is five (or seven for
the two previous methods. Pause the retrieval during Format = 0).
CONV toggling to prevent digital noise, as discussed
previously, and finish before the next data are ready.
The maximum number of DDC232s that can be
daisy-chained together with Format = 1 is:
CONV tINT tINT tINT
DVALID t SDCV
tHDDODV
t SDCV
DCLK … … … … … …
DOUT … … … … … …
Side B Side A
Data Data
Figure 22. Readback Before and After CONV Toggles

DDC232
RETRIEVAL: NONCONTINUOUS MODE until the second integration completes, leaving less
time available for retrieval. The time available is
Retrieving in Noncontinuous mode is slightly different tNCDR2 – (tINT – tNCDR1). Data from the second
as compared with the Continuous mode. As integration must be retrieved before the next round of
illustrated in Figure 23, DVALID goes low in time integration begins. This time is highly dependent on
tNCDR1 after the first integration completes. If tINT is the pattern used to generate CONV. As with the
shorter than this time, all of tNCDR2 is available to continuous mode, data retrieval must halt before and
retrieve data before the other side data are ready. For after CONV toggles (tSDCV) and be completed before
tINT > tNCDR1, the first integration data are ready new data are ready (tHDDODV).
before the second integration completes. Data
retrieval must be delayed
t IN T t IN T
CO NV
t IN T t IN T
D VALID
tNCDR 1 tN C D R 2
DC LK … …
DO UT … …
Side A Side B
Data Data
Figure 23. Readback in Noncontinuous Mode

DDC232
POWER-UP SEQUENCING LAYOUT

Prior to power-up, all digital and analog inputs must POWER SUPPLIES AND GROUNDING
be low. At the time of power-up, all of these signals
should remain low until the power supplies have Both AVDD and DVDD should be as quiet as
stabilized, as shown in Figure 24. At this time, begin possible. It is particularly important to eliminate noise
supplying the master clock signal to the CLK pin. from AVDD that is nonsynchronous with the DDC232
Wait for time tPOR, then give a RESET pulse. After operation. Figure 25 illustrates how to supply power
releasing RESET, the configuration register must be to the DDC232. Each supply of the DDC232 should
programmed. Table 16 shows the timing for the be bypassed with 10mF solid tantalum capacitors. It is
power-up sequence. recommended that both the analog and digital
grounds (AGND and DGND) be connected to a single
tPOR ground plane on the printed circuit board (PCB).
Power Supplies
VA
0.1mF
tRST AVDD AGND
RESET 10mF
DDC232
VD
0.1mF
CONV DVDD DGND
10mF
Figure 24. DDC232 Timing at Power-Up

Figure 25. Power-Supply Connections
Table 16. Timing Characteristics for DDC232
Power-Up Sequence Shielding Analog Signal Paths
SYMBOL DESCRIPTION MIN TYP MAX UNITS As with any precision circuit, careful PCB layout will
tPOR
Wait After Power-Up
250 ms
ensure the best performance. It is essential to make
Until Reset short, direct interconnections and avoid stray wiring
tRST Reset Low Width 1 ms capacitance—particularly at the analog input pins and
QGND. These analog input pins are high-impedance
BLANKSPACE and extremely sensitive to extraneous noise. The
BLANKSPACE QGND pin should be treated as a sensitive analog
signal and connected directly to the supply ground
BLANKSPACE with proper shielding. Leakage currents between the
PCB traces can exceed the input bias current of the
BLANKSPACE
DDC232 if shielding is not implemented. Digital
signals should be kept as far as possible from the
analog input signals on the PCB.

DDC232
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (September 2006) to Revision D Page
• Revised document format to meet current standards ........................................................................................................... 1

• Updated data sheet to include new DDC232CK information ................................................................................................ 1

PACKAGE OPTION ADDENDUM
www.ti.com 22-Dec-2020
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
201-000795 ACTIVE NFBGA ZXG 64 1000 RoHS & Green SNAGCU Level-3-260C-168 HR 0 to 70 DDC232
DDC232CKZXGR ACTIVE NFBGA ZXG 64 1000 RoHS & Green SNAGCU Level-3-260C-168 HR 0 to 70 DDC232K
DDC232CKZXGT ACTIVE NFBGA ZXG 64 250 RoHS & Green SNAGCU Level-3-260C-168 HR 0 to 70 DDC232K
DDC232CZXGR ACTIVE NFBGA ZXG 64 1000 RoHS & Green SNAGCU Level-3-260C-168 HR 0 to 70 DDC232
DDC232CZXGT ACTIVE NFBGA ZXG 64 250 RoHS & Green SNAGCU Level-3-260C-168 HR 0 to 70 DDC232
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
TAPE AND REEL INFORMATION
REEL DIMENSIONS TAPE DIMENSIONS

K0 P1
B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2 Q1 Q2
Q3 Q4 Q3 Q4 User Direction of Feed
Pocket Quadrants
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DDC232CKZXGR NFBGA ZXG 64 1000 330.0 16.4 8.3 8.3 2.25 12.0 16.0 Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DDC232CKZXGR NFBGA ZXG 64 1000 350.0 350.0 43.0
Pack Materials-Page 2
PACKAGE OUTLINE
ZXG0064A SCALE 1.500
NFBGA - 1.45 mm max height
PLASTIC BALL GRID ARRAY
8.1 B
A
7.9
BALL A1 CORNER
8.1
7.9
1.45
1.27
C
SEATING PLANE
0.41
TYP BALL TYP 0.12 C
0.31
5.6 TYP
(1.2) TYP
SYMM
(1.2) TYP
H
5.6 E SYMM
TYP D
C 0.51
64X
0.41
B 0.15 C A B
A 0.08 C
0.8 TYP
1 2 3 4 5 6 7 8
BALL A1 CORNER
0.8 TYP
4220377/A 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is lead-free.
www.ti.com
EXAMPLE BOARD LAYOUT
ZXG0064A NFBGA - 1.45 mm max height
(0.8) TYP
64X ( 0.4)
1 2 3 4 5 6 7 8
A
(0.8) TYP
D
SYMM
SYMM
LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:12X
0.05 MAX METAL UNDER

( 0.4) 0.05 MIN
SOLDER MASK
METAL
EXPOSED EXPOSED
SOLDER MASK METAL METAL ( 0.4)
OPENING SOLDER MASK
OPENING
NON-SOLDER MASK SOLDER MASK
DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS

NOT TO SCALE
4220377/A 03/2023
NOTES: (continued)
4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99).
www.ti.com
EXAMPLE STENCIL DESIGN
ZXG0064A NFBGA - 1.45 mm max height
(0.8) TYP
( 0.4) TYP
1 2 3 4 5 6 7 8
A
(0.8) TYP
D
SYMM
SYMM
SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:12X
4220377/A 03/2023
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
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TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023, Texas Instruments Incorporated

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DDC232

www.ti.com SBAS331D – AUGUST 2004 – REVISED APRIL 2010

1FEATURES The DDC232 uses a +5V analog supply and a +2.7V

• Low Power: 7mW/channel 0.1mF

– Integration Times as low as 166.5ms DS CONV

APPLICATIONS IN3 Switched

SBAS331D – AUGUST 2004 – REVISED APRIL 2010 www.ti.com

DEVICE FAMILY COMPARISON

(1) Using external integration capacitors.

ABSOLUTE MAXIMUM RATINGS (1)

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(1) Input is less than 1% of full-scale.

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ELECTRICAL CHARACTERISTICS (continued)

(8) Ensured by design, not production tested.

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Product Folder Link(s): DDC232

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Top View BGA

IN21 IN22 IN23 IN24 IN25 IN26 IN27 IN28

IN5 IN6 IN7 IN8 IN9 IN10 IN11 IN12

IN17 IN18 IN19 IN20 IN29 IN30 IN31 IN32

IN1 IN2 IN3 IN4 IN13 IN14 IN15 IN16

AGND AVDD AVDD AVDD AGND DGND VREF VREF

DVALID DIN_CFG CLK_CFG DGND DGND RESET DVDD DGND

DCLK DGND CLK NC DOUT DGND DIN CONV

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Noise (ppm of FSR, rms)

Table 1. NOISE vs CSENSOR (ppm of FSR, rms)

Table 2. NOISE vs CSENSOR (fC, rms)

Table 3. NOISE vs CSENSOR (electrons, rms)

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Product Folder Link(s): DDC232

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AVDD VREF DVDD

Figure 2. DDC232 Block Diagram

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SBAS331D – AUGUST 2004 – REVISED APRIL 2010 www.ti.com

DEVICE OPERATION operational amplifier. At the beginning of a

Adjustable Feedback Capacitors (CF)

Input SINTA SREF2

Figure 3. Basic Integration Configuration for Input 1

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Figure 4. Integration Timing (see Figure 3)

SRESET To Converter VREF

Figure 5. Four Configurations of the Front-End Integrators

SBAS331D – AUGUST 2004 – REVISED APRIL 2010 www.ti.com

charge needed by the ∆Σ converter. For an

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Frequency Response CONFIGURATION REGISTER

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