ADE Syllabus

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Analog and Digital Electronics Semester III

Course Code BUE303 CIE Marks 50


Teaching Hours/Week (L:T:P:S) 3:0:2:0 SEE Marks 50
Total Hours of Pedagogy 40 hours Theory + 8-10 Lab slots Total Marks 100
Credits 04 Exam Hours
Examination nature (SEE) Theory

Course objectives:
 To Illustrate simplification of Algebraic equations using Karnaugh Maps and Quine-Mc Clusky
Techniques.
 To know design of Decoders, Encoders, Digital Multiplexers, Adders, Subtractors, Look ahead
carry, Binary Comparators.
 To Describe Latches, Flip-flops, Registers and Counters.
 To Understand concept of signal generators such as Phase Shift Oscillators, Colpitts
Oscillators, Hartley Oscillators, Wein Bridge Oscillator.

Teaching Learning Process (General Instructions)


These are sample Strategies, which teacher can use to accelerate the attainment of the various
course outcomes.
1. Explain the fundamental concepts required for the module in the introduction phase of the
module.
2. Conducting quiz after completion of every module in class and evaluate.
3. Asking questions about completed previous topic, will aid to assess the student understanding.
4. Evaluate the internals answer booklet by correcting the mistakes if any.
5. Modules revision at the end as well use practical lab sessions and demonstrate the concepts if
applicable and feasible.
In addition to the traditional lecture method, different types of innovative teaching methods may
be adopted so that the delivered lessons shall develop students theoretical and programming skills.

MODULE-1
BJT Biasing : DC Load Line and Bias Point, Base Bias, Collector-to- Base Bias, Voltage-Divider Bias,
Comparision of Basic Bias Circuits, Troubleshooting BJT Bias Circuits, Bias Circuit Design, More
Bias Circuits, Thermal Stability of Bias Circuits, Biasing BJT Switching Circuits.(Text 1- Chapter5)
MODULE-2
Signal Generators : Phase Shift Oscillators, Colpitts Oscillators, Hartley Oscillators, Wein Bridge
Oscillator, Oscillator Amplitude Stabilization, Square Wave Generator, 555 Pulse Generator,
Triangular Wave Generator, Oscillator Frequency Stabilization.(Text 1- Chapter16)
MODULE-3
Principles of Combinational Logic : Introduction ,Definition of Combinational Logic, Canonical
Forms, Generation of Switching Equations from Truth Tables, Karnaugh Maps, Quine-Mc Clusky
Minimization Techniques(3,4 variables).(Text 2- 3.1, 3.2, 3.3, 3.4, 3.5)

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MODULE-4
Analysis and Design of Combinational Logic: Decoders, Encoders, Digital Multiplexers, Adders
and Subtractors, Cascading Full Adder, Look ahead carry, Binary Comparators.
(Text 2- 4.3, 4.4, 4.5, 4.6(4.6.1, 4.6.2), 4.7)
Flip-Flops and its Applications: Basic Bistable elements, Latches, Timming Considerations.
(Text 3 - 6.1, 6.2, 6.3)

MODULE-5
Flip-Flops and its Applications : The master slave flip-flops (pulse-triggered flip-flops): SR flip-
flops, JK flip-flops, 0’s and 1’s Catching, Additional Types of Master-Slave Flip-Flops, Edge –
Triggered Flip-Flops, Characteristics equations, Registers, Counters, Design of Synchronous
Counters.
(Text 3 - 6.4, 6.5, 6.6, 6.7, 6.8, 6.9)

PRACTICAL COMPONENT OF IPCC


Sl.NO Experiments
1 Half wave rectifier and Full wave rectifier with and without filter and measure the ripple
factor.
2 Characteristics of Zener diode and design a Simple Zener voltage regulator determine line
and load.
3 Design and set up the BJT common emitter voltage amplifier with and without feedback and
determine the gain- bandwidth product, input and output impedances.
4 Design and set-up BJT/FET
i)Colpitts Oscillator, ii)RC Phase shift Oscillator
5 Design and set up the circuits using Opamp:
i)Inverting, ii)Non Inverting, iii)Differentiator and iv)Integrator
6 Design and implement
(a) Half Adder & Full Adder using basic gates and NAND gates,
(b) Half subtractor & Full subtractor using NAND gates
7 Realize the following
i) Realize a decoder circuit using basic gates
ii) Verify 8:1 encoder using 74LS148.
iii) Realize 4:1 Multiplexer using NAND gates
iv) Realization of 7485 magnitude comparator
8 Realize using NAND Gates:
i) Master-Slave JK Flip-Flop, ii) D Flip-Flop and iii) T Flip-Flop
9 b) Realize the shift registers using IC7474/7495:
(i) SISO (ii) SIPO (iii) PISO (iv) PIPO
10 Design Mod – N Synchronous Up Counter & Down Counter using 7476 JK Flip-flop.

11 Demo Experiment: Design and simulation of Regulated power supply.

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12 Demo Experiment: Design and test Monostable and Astable Multivibrator using 555 Timer.

Course outcomes (Course Skill Set):


At the end of the course, the student will be able to:
 Explain the concept of combinational logic circuits.
 Describe and characterize flip-flops and its applications.
 Analyze and Design of ALUs, Multiplexers, adders and subtractors, look ahead carry, binary
Comparators.
 Generation of Square Wave Generator, 555 Pulse Generator, Triangular Wave Generator,
Oscillator Frequency Stabilization,555 Timers.
 Describe Latches, Flip-flops, Registers and Counters.
Assessment Details (both CIE and SEE)
The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is
50%. The minimum passing mark for the CIE is 40% of the maximum marks (20 marks out of 50) and
for the SEE minimum passing mark is 35% of the maximum marks (18 out of 50 marks). A student
shall be deemed to have satisfied the academic requirements and earned the credits allotted to each
subject/ course if the student secures a minimum of 40% (40 marks out of 100) in the sum total of
the CIE (Continuous Internal Evaluation) and SEE (Semester End Examination) taken together.

CIE for the theory component of the IPCC (maximum marks 50)
 IPCC means practical portion integrated with the theory of the course.
 CIE marks for the theory component are 25 marks and that for the practical component is 25
marks.
 25 marks for the theory component are split into 15 marks for two Internal Assessment Tests
(Two Tests, each of 15 Marks with 01-hour duration, are to be conducted) and 10 marks for
other assessment methods mentioned in 22OB4.2. The first test at the end of 40-50% coverage
of the syllabus and the second test after covering 85-90% of the syllabus.
 Scaled-down marks of the sum of two tests and other assessment methods will be CIE marks for
the theory component of IPCC (that is for 25 marks).
 The student has to secure 40% of 25 marks to qualify in the CIE of the theory component of IPCC.
CIE for the practical component of the IPCC
 15 marks for the conduction of the experiment and preparation of laboratory record, and 10
marks for the test to be conducted after the completion of all the laboratory sessions.
 On completion of every experiment/program in the laboratory, the students shall be evaluated
including viva-voce and marks shall be awarded on the same day.
 The CIE marks awarded in the case of the Practical component shall be based on the continuous
evaluation of the laboratory report. Each experiment report can be evaluated for 10 marks.
Marks of all experiments’ write-ups are added and scaled down to 15 marks.
 The laboratory test (duration 02/03 hours) after completion of all the experiments shall be
conducted for 50 marks and scaled down to 10 marks.
 Scaled-down marks of write-up evaluations and tests added will be CIE marks for the laboratory

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component of IPCC for 25 marks.
 The student has to secure 40% of 25 marks to qualify in the CIE of the practical component of the
IPCC.
SEE for IPCC
Theory SEE will be conducted by University as per the scheduled timetable, with common question
papers for the course (duration 03 hours)
1. The question paper will have ten questions. Each question is set for 20 marks.
2. There will be 2 questions from each module. Each of the two questions under a module (with a
maximum of 3 sub-questions), should have a mix of topics under that module.
3. The students have to answer 5 full questions, selecting one full question from each module.
4. Marks scored by the student shall be proportionally scaled down to 50 Marks
The theory portion of the IPCC shall be for both CIE and SEE, whereas the practical portion will
have a CIE component only. Questions mentioned in the SEE paper may include questions from
the practical component.
Suggested Learning Resources:
Books
1. DAVID A. BELL “Electronic Devices and Circuits” 5th Edition, OXFORD University Press.
2. JOHN M.YARBROUGH., Digital logic applications and Design, Thomson Learning.
3. Donald D.Givone., Digital Principles and Design, Tata McGraw-Hill Edition-2002.

Web links and Video Lectures (e-Resources):


 nptel.ac.in

Activity Based Learning (Suggested Activities in Class)/ Practical Based learning


 Quizzes
 Assignments
 Group Discussion
 Seminars

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