130-15ikb Compal Dlid4 Dlid5 La-G202p

A B C D E

1 1

Compal LA-G202P
DLID4 / D5
2 2

Vinafix.com
DIS M/B Schematic Document
Intel KabyLake U/KabyLake R Processor with DDR4
3
REV 1.0 3
2018-03-09
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.

2018/03/09 2019/03/09 Tiitl e
Issued Date Decipherii ed Dae
t Cover Page
THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIS THE PROPRIIETARY PROPERTY OF COMPAL ELECTRONIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
TRADE SECRET IIINFORMATIIION.. THIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIVIIISIIION OF R&D DEPARTMENT Siiize Documentt Number R ev
EXCEPT AS AUTHORIIZED BY COMPAL ELECTRONIIICS,,, IIINC.. NEIIITHER THIS SHEET NOR THE IIINFORMATIIION IIT CONTAIIINS Custtom 1..0
MAY BE USED BY OR DIISCLOSED TO ANY THIIRD PARTY WIIITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,,, IIINC. LA-G202P
Date: Friiiday,,, March 09,,,2018 Sheett 1 o ff 55
A B C D E
A B C D E
Memory Bus (Channel A)

DDR4 (On Board) X4
NVIDIA MX110 *KBL-U: DDR4 (2133MHz, 1.2V)
(2GB GDDR5 VRAM)
PCIe X4 Gen3
*KBL-R: DDR4 (2400MHz, 1.2V)
1 (256 x 32 x 2 PCS) 1
Memory Bus (Channel B)

DDR4 (SO DIMM) X1
eDP X1 (2 Lanes)
eDP Conn. PCIe X1 (1 Lanes)
USB 2.0 X1
WLAN / BT
DDI X1 (4 Lanes)
HDMI Conn. Intel KabyLake-U USB3.0 x1
Intel KabyLake-R Left USB3.0 x1
USB2.0 x1
2 SOC 2
LAN PCIe X1 (1 Lane) 1356 Pin BGA

RJ45 Conn. RTL8106E-CG USB3.0 x1
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10/100
USB2.0 x1
Left USB3.0 x1
ODD Conn. SATA X1

(14" -> On Mother Board)
(15" -> On Sub/B through FFC)
USB2.0 x1
Int. Camera
HDD Conn. SATA X1 USB2.0 x1 Card Reader

3
(On Sub/B through FFC) Realtek SD Card Conn. 3
RTS5146-GR
HDA I2C x1
Audio Codec Touch Pad
Realtek
ALC3240 SPI LPC
SPI ROM EC
Audio Combo Jack 8MB, 3.3V ENE
Int. Speaker Conn. Headphone / Mic KB9022QD
4 4
LED Int. KBD Hall Sensor
Securiiity Clllassiiifiiicatiiion Compal Secret Data Compal Electronics, Inc.

Issued Date Tiiitttllle
Decipherii ed Date
THISI SHEET OF ENGINI EERINI G DRAWINIIG ISITHE PROPRIEII TARY PROPERTY OF COMPAL ELECTRONICII S,,, INIC... AND CONTAINII S CONFIDII ENTIAI L AND TRADE
Block Diagram
SECRET INIFORMATIONII ..THISI SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIISIIONIOF R&D DEPARTMENT EXCEPT AS Siiize Documenttt Number Rev
AUTHORIZEII D BY COMPAL ELECTRONICII S,,,INIC...NEITHII ER THISI SHEET NOR THE INIFORMATIONII ITICONTAINII S C 1..0
MAY BE USED BY OR DISICLOSED TO ANY THIRI D PARTY WITHI OUT PRIORIIWRITTEII N CONSENT OF COMPAL ELECTRONICII S,,,INIC... LA-G202P
Dattte::: Friiiday,,, March 09,,, 2018 Sheettt 2 o ff55
A B C D E
5 4 3 2 1
-PowerMap_KBL_DDR4_Volume_NON CS]
B+
D D
C C
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B B
A A
Securiiirr tyt Classiiil fffiicatiitton Compalll Secrettt Dattta Compal Electronics, Inc.
IIIssued Dattte 2018/03/09//// Deciiipherrred Dattte 2019/03/09//// Tiittllle
THISISHEET OF ENGINEIIERINGIIDRAWINGIIISTI HE PROPRIEII TARY PROPERTY OF COMPAL ELECTRONICII S,,,INCI..AND CONTAINSII CONFIDII ENTIAI L AND TRADE SECRET INFI
Power MAP
ORMATION...II THISISHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIISIONIOF R&D DEPARTMENT EXCEPT AS AUTHORIZEII D
BY COMPAL ELECTRONICII S,,,INCI..NEITHEIIR THISISHEET NOR THE INFIORMATIONII ITICONTAINSII
Siiize Documenttt Numberrr
LA-C071P Re v
1..0
MAY BE USED BY OR DISICLOSED TO ANY THIRDIIPARTY WITHOUTII PRIORIIWRITTEIIN CONSENT OF COMPAL ELECTRONICII S,,,INCI..
Dattte::: Frrriiiday,,,Marrrch09,,, 2018 Sheettt 4 o fff55
5 4 3 2 1
5 4 3 2 1
G3->S0 S0->S3/DS3 S0/DS3->S0 S0->S5

+3VL_RTC +3VL_RTC
tPCH01_Min : 9 ms
SOC_RTCRST# SOC_RTCRST#
B+ B+
D D
+3VLP/+5VLP +3VLP/+5VLP
EC_ON EC_ON
tPCH04_Min : 9 ms
+5VALW/+3VALW/+3VALW_DSW +5VALW/+3VALW/+3VALW_DSW
Pull-up to DSW well if not implemented.
PM_BATLOW# PM_BATLOW#
PCH_PWR_EN (SLP_SUS#) PCH_PWR_EN (SLP_SUS#)
+3V_PRIM +3V_PRIM
+1.8V_PRIM +1.8V_PRIM
EXT_PWR_GATE# If EXT_PWR_GATE# Toffmin is too small, Pwr EXT_PWR_GATE#

gate may choose to completely ignore it
+1.0V_MPHYPLL +1.0V_MPHYPLL
+1.0V_PRIM_CORE +1.0V_PRIM_CORE
tPCH34_Max : 20 ms
+1.0V_PRIM tPCH06_Min : 200 us +1.0V_PRIM
SUSACK# SUSACK#
tPCH02_Min : 10 ms
PCH_DPWROK PCH_DPWROK
tPCH03_Min : 10 ms
EC_RSMRST# EC_RSMRST#
tPLT02_Min : 0 ms Max : 90 ms
C C
AC_PRESENT AC_PRESENT
ON/OFF ON/OFF
tPCH43_Min : 95 ms
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PBTN_OUT# PBTN_OUT#
Minimum duration of PWRBTN# assertion = 16mS. PWRBTN# can assert before or after RSMRST#
PM_SLP_S5# PM_SLP_S5#
tPCH18_Min : 90 us
ESPI_RST# ESPI_RST#
SYSON SYSON
+1.0V_VCCST/+1.0V_VCCSFR +1.0V_VCCST/+1.0V_VCCSFR
+1.35V_VDDQ/+1.35V_VCCSFR_OC +1.35V_VDDQ/+1.35V_VCCSFR_OC
SUSP# SUSP#
tCPU04 Min : 100 ns
+1.0VS_VCCSTG +1.0VS_VCCSTG
tCPU10 Min : 1 ms
B
+1.0VS_VCCIO +1.0VS_VCCIO B
T <=10msec
+5VS/+3VS/+1.5VS/+1.05VS
+5VS/+3VS/+1.5VS/+1.05VS
T = 10msec
EC_VCCST_PG EC_VCCST_PG
VR_ON VR_ON
tCPU19 Max : 100 ns
SM_PG_CTRL SM_PG_CTRL
tCPU18 Max : 35 us
+0.675VS_VTT +0.675VS_VTT
tCPU09 Min : 1 ms
+VCC_SA +VCC_SA
+VCC_CORE +VCC_CORE
+VCC_GT +VCC_GT
VR_PWRGD VR_PWRGD
tCPU16 Min : 0 ns
PCH_PWROK PCH_PWROK
H_CPUPWRGD H_CPUPWRGD
SYS_PWROK SYS_PWROK
A A
SUS_STAT# SUS_STAT#
SOC_PLTRST#
SOC_PLTRST#
Securiiittty Clllassiifffiiicatttiiion Compalll Secret Data Compal Electronics,Inc.

2018///03///09 2019///03///09 Tiittle
IsI sued Datett Deciiiphererr d Dattte
THISII SHEET OF ENGINEERINGIIII DRAWINGIIISITHE PROPRIETII ARY PROPERTY OF COMPAL ELECTRONICS,,,II INC...IIAND CONTAINSII CONFIDENTI IALIIAND TRADE
Power Sequence
SECRET INFIIORMATION...II THISII SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISIONIIIIIIOF R&D DEPARTMENT EXCEPT AS Siiize Documenttt Numberrr Re v
AUTHORIZII ED BY COMPAL ELECTRONICS,,,II INC...IINEITIIHER THISII SHEET NOR THE INFIIORMATIONII ITICONTAINSII 1..0
MAY BE USED BY OR DISCLIIOSED TO ANY THIRDII PARTY WITIIHOUT PRIORII WRITIITEN CONSENT OF COMPAL ELECTRONICS,,,II INC...II
Dattte::: Frrriiday,,,Marrrch 09,,, 2018 Sheettt 5 o ff55
5 4 3 2 1
1 2 3 4 5
Voltage Rails BOM Structure Table

Item BOM Structure Item BOM Structure
DIS Only Components DIS@ X4E_U22_14@ USB 2.0 Port Table
+5VS
UMA Only Components UMA@ X4E_U22_15@
X4E
power 14" Only Components 14@ X4E_U42_14@ Port External USB Port
plane +3VS
+1.35VS
15" Only Components 15@ X4E_U42_15@
1
HDMI Logo 45@ On Board RAM (Hynix 4GB) H4G_MD@
+5VALW +1.2V +VCC_CORE 2 USB2/3 Port (MB-1)
+VGA_CORE
GIGA LAN Reserved Items 8111GLDO@ On Board RAM (Micron 4GB) M4G_MD@
B+ 3 USB2/3 Port (MB-2)
Memory Down - SDP Package SDP@ On Board RAM (Samsung 4GB) S4G_MD@
+3VALW +VCC_GFXCORE_AXG 4
A
Memory Down - DDP Package DDP@ On Board RAM X76 Resistors X76RAM@ A
+1.8VS 5 Camera
GPU GC6 Components GC6@ Realtek Card Reader RTK_CR@
State +0.6VS 6 Card Reader
Un-Mount GPU GC6 Components NOGC6@ Genesys Card Reader GNS_CR@
+1.0VALW 7 NGFF WLAN+BT
N16S_R1@ H2G_VRAM@
N16S_R3@ H2G@
GPU VRAM (Hynix 2GB)
N16V_R1@ H2G_R1@
USB 3.0 Port Table
N16V_R3@ H2G_R3@
EMI Category EMI@ H4G_VRAM@ Port
S0 ESD Category ESD@ H4G@ 1
O O O O RF Category RF@
VRAM (Hynix 4GB)
H4G_R1@ 2 USB2/3 Port (MB-1) PCIE Port Table
EMI Un-Mount Items @EMI@ H4G_R3@ 3 USB2/3 Port (MB-2)
ESD Un-Mount Items @ESD@ M2G_VRAM@ 4 Lane Port
S3 O O O X RF Un-Mount Items @RF@ M2G@ 5 1
VRAM (Micron 2GB)
Connectors ME@ M2G_R1@ 6 2
S5 S4/AC O O X X Test Point TP@ M2G_R3@ 3
1 GPU
Intel Debug Components @DCI@ M4G_VRAM@ 4
S5 S4/ Battery only O X X X Un-Mount Components @ M4G@
SATA Port Table
5 LAN
VRAM (Micron 4GB)
CPU Components - U22 Only U22@ M4G_R1@ Port 6
S5 S4/AC & Battery
don't exist X X X X CPU Components - U42 Only U42@ M4G_R3@
NGFF WLAN+BT
0 HDD 7
EMI U22 Components U22_EMI@ S2G_VRAM@ 1 ODD 8
EMI U42 Components U42_EMI@ S2G@ 9
B VRAM (Samsung 2GB) B
i3_7020U_R1@ S2G_R1@ 10
i5_8250U_R1@ S2G_R3@ 11
i5_8250U_R3@ S4G_VRAM@ 12
CPU
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i7_8550U_R1@ S4G@
EC SM Bus1 address EC SM Bus2 address VRAM (Samsung 4GB)
i7_8550U_R3@ S4G_R1@
i3_8130U_R1@ S4G_R3@
Device Address Device Address
Smart Battery 0001 011x 16h NCT7718W 1001 100x 98h
X4E ON BOARD RAM * 4 HDMI Logo
PCH SM Bus address GPU SM Bus address ZZZ S4G_MD@ ZZZ M4G_MD@ ZZZ H4G_MD@ ZZZ 45@
Device Address Device Address
D D R _ JDIM M 1 1010 000x A0h Internal thermal sensor 1001 111x 9Eh
Touch Pad
U42 U22 X76 SAMSUNG 4GB MD X76 MICRON 4GB MD X76 HYNIX 4GB MD
X7677538L13 X7677538L14 X7677538L15 HDMI Logo
ZZZ X4E_U42@ ZZZ X4E_U22@ RO0000003HM
SMBUS Control Table

X4E U42
X4EABQ38L01
X4E U22
X4EABQ38L02 CARD READER PCB
*Main Source - Realtek
SOURCE VGA BATT CHARGER NECP388 SODIMM Sensor
Thermal
DGPU G- *Substitute - Genesys
TP PCH SENSOR
C SMB_EC_CK1
NECP388 X V V X X X X X X X
ZZZ 14_DAZ@ C
SMB_EC_DA1 +3VALW +3VALW +19 V_VIN X X

SMB_EC_CK2
NECP388 V X X V X V X X X X
SMB_EC_DA2 +3VS +3VGS + 3VS + 3VS X V
+ 3VS GDDR5 VRAM * 2 PCB
DAZ29900201
SMB_EC_CK4
SMB_EC_DA4
NECP388
+3VALW
X X X X X X X X X X X V
+ 3VS 2GB ZZZ 15_DAZ@
PCH_SMBCLK
PCH_SMBDATA
PCH
+3VALW
X X X X V
+ 3VS
X X X X V X X ZZZ H2G_VRAM@ ZZZ M2G_VRAM@ ZZZ S2G_VRAM@
+ 3VS
SML0CLK
PCH X X X X X X X X X X X PCB
SML0DATA +3VALW +3VS
V DAZ29A00201
SML1CLK
X X X V X X V X X
X76 HYNIX 2GB
X X
X76 MICRON 2GB X76 SAMSUNG 2GB
PCH
X
X7677538L06
+ 3VS + 3VS
X7677538L05 X7677538L04
SML1DATA +3VALW
*N16V - MX110 Device ID:0x174E

GPU *N16S - MX130 ( Device ID: 0x174D) CPU
( )
SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock UV1 N16S_R1@ UV1 N16V_R1@ KBL U22 (= U22@) KBL U42 (= U42@)
UC1 i3_7020U_R1@ UC1 i5_8250U_R1@ UC1 i7_8550U_R1@ UC1 i3_8130U_R1@
Full ON HIGH HIGH HIGH HIGH ON ON ON ON
S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW N16S-GTR-S-A2 BGA 595P N16V-GMR1-S-A2 BGA 595P
SA00009FP00 SA00009IT00
QNZU H02.3G SR3LA Y0 1.6G FCBGA SR3LC Y0 1.8G FCBGA QP8K Y02.2G
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF UV1 N16S_R3@ UV1 N16V_R3@ SA0000BLH10 SA0000AWB20 SA0000AWC20 SA0000BKN20
D D
UC1 i3_7020U_U22@ UC1 i5_8250U_R3@ UC1 i7_8550U_R3@ UC1 i3_8130U_R3@ UC1 i3_7020U_U42@
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF N16S-GTR-S-A2 BGA 595P N16V-GMR1-S-A2 BGA 595P
SA00009FP30 SA00009IT30
SR3TK H02.3G SR3LA Y0 1.6G FCBGA SR3LC Y0 1.8G FCBGA SR3W 0 Y02.2G SR3LD Y0 2.3G
SA0000BLH50 SA0000AWB50 SA0000AWC50 SA0000BKN30 SA0000BLD60
Securiiity Clllassiiifiiicatiiion Compalll Secret Data

Tiitttlle
Compal Electronics, Inc.
Issued Date 2018/03/09 Deciiiphered Date 2019/03/09
THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIISTHE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
Notes List
Siiize Documenttt Numberrr Rev
TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D DEPARTMENT
Custttom 1..0
EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC...NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIITCONTAIIINS
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IIINC...
Dattte:::
LA-G202P
Frrriiday,,, Marrrch 09,,, 2018 Sheettt 3 o ff55
1 2 3 4 5
A B C D E
1 1
UC1A SKL-U
Rev_1.0
E55 C47
F55 DDI1_TXN[0] EDP_TXN[0] C46 EDP_TXN0 <28>
E58 DDI1_TXP[0] EDP_TXP[0] D46 EDP_TXP0 <28>
F58 DDI1_TXN[1] EDP_TXN[1] C45 EDP_TXN1 <28> <eDP>
DDI1_TXP[1] EDP_TXP[1] EDP_TXP1 <28>
F53 A45
G53 DDI1_TXN[2] EDP_TXN[2] B45
F56 DDI1_TXP[2] EDP_TXP[2] A47
G56 DDI1_TXN[3] EDP_TXN[3] B47
DDI1_TXP[3] EDP_TXP[3]
C50 E45
<29> HDMI_TX2-_CK D50 DDI2_TXN[0] DDI EDP_AUXN F45 EDP_AUXN <28>
EDP
<29> HDMI_TX2+_CK C52 DDI2_TXP[0] EDP_AUXP EDP_AUXP <28>
<29> HDMI_TX1-_CK D52 DDI2_TXN[1] B52
<29> HDMI_TX1+_CK A50 DDI2_TXP[1] EDP_DISP_UTIL
<HDMI> <29> HDMI_TX0-_CK B50 DDI2_TXN[2] G50
<29> HDMI_TX0+_CK D51 DDI2_TXP[2] DDI1_AUXN F50
<29> HDMI_CLK-_CK C51 DDI2_TXN[3] DDI1_AUXP E48
<29> HDMI_CLK+_CK DDI2_TXP[3] DDI2_AUXN
F48
DDI2_AUXP G46
DISPLAY SIDEBANDS RSVD F46
L13 RSVD
L12 GPP_E18/DDPB_CTRLCLK L9
GPP_E19/DDPB_CTRLDATA GPP_E13/DDPB_HPD0 L7
N7 GPP_E14/DDPC_HPD1 L6 TMDS_B_HPD <29> From HDMI
<29> HDMICLK_NB N8 GPP_E20/DDPC_CTRLCLK GPP_E15/DDPD_HPD2 N9
HDMI DDC (Port C) <29> HDMIDAT_NB GPP_E21/DDPC_CTRLDATA GPP_E16/DDPE_HPD3 L10 EC_SCI# <10,36>
N11 GPP_E17/EDP_HPD EDP_HPD <28> From eDP
N12 GPP_E22 R12
GPP_E23 EDP_BKLTEN R11 ENBKL <36>
EDP_COMP EDP_BKLTCTL U13 INVPWM <28>
E52 1 OF 20
2 EDP_RCOMP EDP_VDDEN PCH_ENVDD <28> 2
SKL-U_BGA1356 @
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< Compensation PU For eDP >
+1.0VS_VCCIO
1 2 EDP_COMP
RC3 24.9_0402_1%
Trace width=20 mils, Spacing=25mil, Maxlength=100mils

+1.0VS_VCCIO
1
If routed MS, PECI requires 18 mils spacing to other signals

+1.0V_VCCST RC4 UC1D SKL-U
1K_0402_5% Rev_1.0
SOC_CATERR# D63
T99 TP@ H_PECI A54
CATERR# < PU/PD for CMC Debug > +1.0VS_VCCIO
<36> H_PECI
2
1 2 H_THERMTRIP# 1 2 H_PROCHOT#_R C65 PECI

<36> H_PROCHOT# PROCHOT#
JTAG
RC5 1K_0402_5% RC6 499_0402_1% H_THERMTRIP# C63
T100 TP@
SOC_OCC# A65 THERMTRIP# SOC_XDP_TMS RC11 1 @ 2 51_0402_5%
SKTOCC# B61 CPU_XDP_TCK0
XDP_BPM#0 CPU MISC PROC_TCK D60 SOC_XDP_TDI SOC_XDP_TDI
C55 RC12 1 @ 2 51_0402_5%
T103 TP@ XDP_BPM#1 D55 BPM#[0] PROC_TDI A61 SOC_XDP_TDO
T105 TP@
3 XDP_BPM#2 B54 BPM#[1] PROC_TDO C60 SOC_XDP_TMS SOC_XDP_TDO RC13 1 @DCI@ 2 51_0402_5% 3
T107 TP@ PROC_TMS B59
XDP_BPM#3 C56 BPM#[2] SOC_XDP_TRST#
T109 TP@ BPM#[3] PROC_TRST#
A6 B56 PCH_JTAG_TCK1
A7 GPP_E3/CPU_GP0 PCH_JTAG_TCK D59 SOC_XDP_TDI CPU_XDP_TCK0 RC14 1 @DCI@ 2 51_0402_5%
BA5 GPP_E7/CPU_GP1 PCH_JTAG_TDI A56 SOC_XDP_TDO
AY5 GPP_B3/CPU_GP2 PCH_JTAG_TDO C59 SOC_XDP_TMS PCH_JTAG_TCK1 RC15 1 @ 2 51_0402_5%
GPP_B4/CPU_GP3 PCH_JTAG_TMS C61 SOC_XDP_TRST#
PCH_TRST# A59 T116 TP@
RC7 2 1 49.9_0402_1% CPU_POPIRCOMP AT16 CPU_XDP_TCK0
RC8 2 1 49.9_0402_1% PCH_OPIRCOMP AU16 PROC_POPIRCOMP JTAGX
RC9 2 @ 1 49.9_0402_1% EDRAM_OPIO_RCOMP H66 PCH_OPIRCOMP
RC10 2 @ 1 49.9_0402_1% EOPIO_RCOMP H65 OPCE_RCOMP
OPC_RCOMP SOC_XDP_TRST# RC23 1 @ 2 51_0402_5%
4 OF 20
SKL-U_BGA1356 @
4 4

Issued Date 2018/03/09 Decipii hered Date 2019/03/09 Tiiitllle
THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
SKL-U(1/12)DDI,EDP,MISC,CMC
TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D Siiize Document Number R ev
LA-G202P
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIT CONTAIIINS Custttom 1..0
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IINC...
Date: Friiiday,,, March 09,,,2018 Sheet 6 o f 55
A B C D E
5 4 3 2 1
Interleaved Memory
@
DDR_A_CLK0 1 2 DDR_A_CLK#0
D D
CC110
3300P_0402_50V7-K
SKL-U
UC1B SKL-U UC1C
Rev_1.0 Rev_1.0
<18> DDR_A_D[0..15] DDR_A_D0 AL71 DDR_A_CLK#0
AU53
DDR0_DQ[0] DDR0_CKN[0] DDR_A_CLK#0 <18> <19> DDR_B_D[0..15] Interleave / Non-Interleaved
DDR_A_D1 AL68 AT53 DDR_A_CLK0 DDR_B_D0 AF65 AN45 DDR_B_CLK#0
DDR0_DQ[1] DDR0_CKP[0] DDR_A_CLK#1 DDR_A_CLK0 <18> DDR1_DQ[0]/DDR0_DQ[16] DDR1_CKN[0] DDR_B_CLK#1 DDR_B_CLK#0 <19>
DDR_A_D2 AN68 AU55 DDR_B_D1 AF64 AN46
DDR0_DQ[2] DDR0_CKN[1] TP@ T186 DDR1_DQ[1]/DDR0_DQ[17] DDR1_CKN[1] DDR_B_CLK0 DDR_B_CLK#1 <19>
DDR_A_D3 AN69 AT55 DDR_A_CLK1 TP@ T189 DDR_B_D2 AK65 AP45 DDR_B_CLK0 <19>
DDR_A_D4 AL70 DDR0_DQ[3] DDR0_CKP[1] DDR_B_D3 AK64 DDR1_DQ[2]/DDR0_DQ[18] DDR1_CKP[0] AP46 DDR_B_CLK1
DDR0_DQ[4] DDR_A_CKE0 DDR1_DQ[3]/DDR0_DQ[19] DDR1_CKP[1] DDR_B_CLK1 <19>
DDR_A_D5 AL69 BA56 DDR_B_D4 AF66
DDR0_DQ[5] DDR0_CKE[0] DDR_A_CKE0 <18,20> DDR1_DQ[4]/DDR0_DQ[20] DDR_B_CKE0
DDR_A_D6 AN70 BB56 DDR_A_CKE1 DDR_B_D5 AF67 AN56
DDR0_DQ[6] DDR0_CKE[1] TP@ T190 DDR1_DQ[5]/DDR0_DQ[21] DDR1_CKE[0] DDR_B_CKE0 <19>
DDR_A_D7 AN71 AW 56 DDR_B_D6 AK67 AP55 DDR_B_CKE1
DDR0_DQ[7] DDR0_CKE[2] DDR1_DQ[6]/DDR0_DQ[22] DDR1_CKE[1] DDR_B_CKE1 <19>
DDR_A_D8 AR70 AY56 DDR_B_D7 AK66 AN55
DDR_A_D9 AR68 DDR0_DQ[8] DDR0_CKE[3] DDR_B_D8 AF70 DDR1_DQ[7]/DDR0_DQ[23] DDR1_CKE[2] AP53
DDR_A_D10 AU71 DDR0_DQ[9] AU45 DDR_A_CS#0 DDR_B_D9 AF68 DDR1_DQ[8]/DDR0_DQ[24] DDR1_CKE[3]
DDR_A_D11 AU68 DDR0_DQ[10] DDR0_CS#[0] AU43 DDR_A_CS#1 DDR_A_CS#0 <18,20> DDR_B_D10 AH71 DDR1_DQ[9]/DDR0_DQ[25] BB42 DDR_B_CS#0
DDR_A_D12 AR71 DDR0_DQ[11] DDR0_CS#[1] DDR_A_ODT0 TP@ T187 DDR_B_D11 AH68 DDR1_CS#[0] DDR_B_CS#0 <19>
AT45 DDR1_DQ[10]/DDR0_DQ[26] AY42 DDR_B_CS#1
DDR_A_D13 AR69 DDR0_DQ[12] DDR0_ODT[0] DDR_A_ODT1 DDR_A_ODT0 <18,20> DDR_B_D12 AF71 DDR1_CS#[1] DDR_B_CS#1 <19>
AT43 DDR1_DQ[11]/DDR0_DQ[27] BA42 DDR_B_ODT0
DDR_A_D14 AU70 DDR0_DQ[13] DDR0_ODT[1] TP@ T188 DDR_B_D13 AF69 DDR_B_ODT0 <19>
DDR1_DQ[12]/DDR0_DQ[28] DDR1_ODT[0] AW 42 DDR_B_ODT1
DDR_A_D15 AU69 DDR0_DQ[14] DDR_B_D14 AH70 DDR1_DQ[13]/DDR0_DQ[29] DDR1_ODT[1] DDR_B_ODT1 <19>
DDR0_DQ[15] DDR3L / LPDDR3 / DDR4 BA51 DDR_A_MA5 DDR_B_D15 AH69 DDR1_DQ[14]/DDR0_DQ[30]
DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDR_A_MA5 <18,20> <19> DDR_B_D[16..31] DDR3L / LPDDR3 / DDR4
BB54 DDR_A_MA9 DDR_B_D16 AT66 DDR1_DQ[15]/DDR0_DQ[31] AY48 DDR_B_MA5
<18> DDR_A_D[16..31] DDR_A_D16 Interleave / Non-Interleaved DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDR_A_MA9 <18,20> DDR_B_MA5 <19>
BB65 BA52 DDR_A_MA6 DDR_B_D17 AU66 DDR1_DQ[16]/DDR0_DQ[48] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] AP50 DDR_B_MA9
DDR_A_D17 DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDR_A_MA6 <18,20> DDR_B_MA9 <19>
AW 65 DDR0_DQ[16]/DDR0_DQ[32] AY52 DDR_A_MA8 DDR_B_D18 AP65 DDR1_DQ[17]/DDR0_DQ[49] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] BA48 DDR_B_MA6
DDR_A_D18 DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] DDR_A_MA8 <18,20> DDR_B_MA6 <19>
AW 63 DDR0_DQ[17]/DDR0_DQ[33] AW 52 DDR_A_MA7 DDR_A_MA7 <18,20>
DDR_B_D19 AN65 DDR1_DQ[18]/DDR0_DQ[50] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] BB48 DDR_B_MA8
DDR_A_D19 DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] DDR_B_MA8 <19>
AY63 DDR0_DQ[18]/DDR0_DQ[34] AY55 DDR_A_BG0 DDR_A_BG0 <18,20>
DDR_B_D20 AN66 DDR1_DQ[19]/DDR0_DQ[51] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] AP48 DDR_B_MA7 DDR_B_MA7 <19>
DDR_A_D20 BA65 DDR0_DQ[19]/DDR0_DQ[35] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] AW 54 DDR_A_MA12 DDR_B_D21 AP66 DDR1_DQ[20]/DDR0_DQ[52] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] AP52 DDR_B_BG0
DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDR_A_MA12 <18,20> DDR_B_BG0 <19>
DDR_A_D21 AY65 DDR0_DQ[20]/DDR0_DQ[36] BA54 DDR_A_MA11 DDR_B_D22 AT65 DDR1_DQ[21]/DDR0_DQ[53] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] AN50 DDR_B_MA12
DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] DDR_A_MA11 <18,20> DDR_B_MA12 <19>
DDR_A_D22 BA63 DDR0_DQ[21]/DDR0_DQ[37] BA55 M_A_ACT# DDR_B_D23 AU65 DDR1_DQ[22]/DDR0_DQ[54] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] AN48 DDR_B_MA11
M_A_ACT# <18,20> DDR_B_MA11 <19>
DDR_A_D23 BB63 DDR0_DQ[22]/DDR0_DQ[38] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# AY54 DDR_A_BG1 DDR_B_D24 AT61 DDR1_DQ[23]/DDR0_DQ[55] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] AN53 M_B_ACT#
DDR_A_BG1 <18> M_B_ACT# <19>
DDR_A_D24 BA61 DDR0_DQ[23]/DDR0_DQ[39] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] AU46 DDR_A_MA13 DDR_B_D25 AU61 DDR1_DQ[24]/DDR0_DQ[56] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# AN52 DDR_B_BG1
DDR_A_MA13 <18,20> DDR_B_BG1 <19>
DDR_A_D25 AW 61 DDR0_DQ[24]/DDR0_DQ[40] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] AU48 DDR_A_MA15 DDR_B_D26 AP60 DDR1_DQ[25]/DDR0_DQ[57] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] BA43 DDR_B_MA13
DDR_A_MA15 <18,20> DDR_B_MA13 <19>
C DDR_A_D26 BB59 DDR0_DQ[25]/DDR0_DQ[41] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] AT46 DDR_A_MA14 DDR_B_D27 AN60 DDR1_DQ[26]/DDR0_DQ[58] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] AY43 DDR_B_MA15 C
DDR_A_MA14 <18,20> DDR_B_MA15 <19>
DDR_A_D27 AW 59 DDR0_DQ[26]/DDR0_DQ[42] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] AU50 DDR_A_MA16 DDR_B_D28 AN61 DDR1_DQ[27]/DDR0_DQ[59] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] AY44 DDR_B_MA14
DDR_A_MA16 <18,20> DDR_B_MA14 <19>
DDR_A_D28 BB61 DDR0_DQ[27]/DDR0_DQ[43] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] AU52 DDR_A_BA0 DDR_A_BA0 <18,20> DDR_B_D29 AP61 DDR1_DQ[28]/DDR0_DQ[60] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] AW 44 DDR_B_MA16 DDR_B_MA16 <19>
DDR_A_D29 AY61 DDR0_DQ[28]/DDR0_DQ[44] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] AY51 DDR_A_MA2 DDR_A_MA2 <18,20> DDR_B_D30 AT60 DDR1_DQ[29]/DDR0_DQ[61] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] BB44 DDR_B_BA0 DDR_B_BA0 <19>
DDR_A_D30 BA59 DDR0_DQ[29]/DDR0_DQ[45] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] AT48 DDR_A_BA1 DDR_A_BA1 <18,20> DDR_B_D31 AU60 DDR1_DQ[30]/DDR0_DQ[62] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] AY47 DDR_B_MA2 DDR_B_MA2 <19>
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DDR_A_D31 AY59 DDR0_DQ[30]/DDR0_DQ[46] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] AT50 DDR_A_MA10 DDR_A_MA10 <18,20> <19> DDR_B_D[32..47] DDR_B_D32 AU40 DDR1_DQ[31]/DDR0_DQ[63] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] BA44 DDR_B_BA1 DDR_B_BA1 <19>
<18> DDR_A_D[32..47] DDR_A_D32 AY39 DDR0_DQ[31]/DDR0_DQ[47] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] BB50 DDR_A_MA1 DDR_A_MA1 <18,20> DDR_B_D33 AT40 DDR1_DQ[32]/DDR1_DQ[16] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] AW 46 DDR_B_MA10 DDR_B_MA10 <19>
DDR_A_D33 AW 39 DDR0_DQ[32]/DDR1_DQ[0] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] AY50 DDR_A_MA0 DDR_A_MA0 <18,20> DDR_B_D34 AT37 DDR1_DQ[33]/DDR1_DQ[17] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] AY46 DDR_B_MA1 DDR_B_MA1 <19>
DDR_A_D34 AY37 DDR0_DQ[33]/DDR1_DQ[1] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] DDR_B_D35 AU37 DDR1_DQ[34]/DDR1_DQ[18] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] BA46 DDR_B_MA0 DDR_B_MA0 <19>
DDR_A_D35 AW 37 DDR0_DQ[34]/DDR1_DQ[2] BA50 DDR_A_MA3 DDR_B_D36 AR40 DDR1_DQ[35]/DDR1_DQ[19] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]
DDR_A_D36 DDR0_MA[3] DDR_A_MA3 <18,20>
BB39 DDR0_DQ[35]/DDR1_DQ[3] BB52 DDR_A_MA4 DDR_B_D37 AP40 DDR1_DQ[36]/DDR1_DQ[20] BB46 DDR_B_MA3
DDR_A_D37 DDR0_MA[4] DDR_A_MA4 <18,20> DDR_B_MA3 <19>
BA39 DDR0_DQ[36]/DDR1_DQ[4] AM70 DDR_A_DQS#0 DDR_B_D38 AP37 DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[3] BA47 DDR_B_MA4
DDR_A_D38 DDR0_DQSN[0] DDR_A_DQS0 DDR_A_DQS#0 <18> DDR_B_D39 AR37 DDR1_MA[4] DDR_B_MA4 <19>
BA37 DDR0_DQ[37]/DDR1_DQ[5] AM69 DDR1_DQ[38]/DDR1_DQ[22]
DDR_A_D39 DDR0_DQSP[0] DDR_A_DQS#1 DDR_A_DQS0 <18> DDR_B_D40 AT33
BB37 DDR0_DQ[38]/DDR1_DQ[6] AT69 DDR1_DQ[39]/DDR1_DQ[23]
DDR_A_D40 DDR0_DQSN[1] DDR_A_DQS#1 <18> Interleave / Non-Interleaved
AY35 DDR0_DQ[39]/DDR1_DQ[7] AT70 DDR_A_DQS1
DDR_A_DQS1 <18>
DDR_B_D41 AU33 DDR1_DQ[40]/DDR1_DQ[24] AH66 DDR_B_DQS#0
DDR_A_D41 DDR0_DQSP[1] DDR1_DQSN[0]/DDR0_DQSN[2] DDR_B_DQS#0 <19>
AW 35 DDR0_DQ[40]/DDR1_DQ[8] DDR_B_D42 AU30 DDR1_DQ[41]/DDR1_DQ[25] AH65 DDR_B_DQS0
DDR_A_D42 DDR_B_D43 AT30 DDR1_DQSP[0]/DDR0_DQSP[2] DDR_B_DQS0 <19>
AY33 DDR0_DQ[41]/DDR1_DQ[9] DDR1_DQ[42]/DDR1_DQ[26] AG69 DDR_B_DQS#1
DDR_A_D43 Interleave / Non-Interleaved DDR_A_DQS#2 DDR_B_D44 AR33 DDR_B_DQS#1 <19>
AW 33 DDR0_DQ[42]/DDR1_DQ[10] BA64 DDR1_DQ[43]/DDR1_DQ[27] DDR1_DQSN[1]/DDR0_DQSN[3] AG70 DDR_B_DQS1
DDR_A_D44 DDR_A_DQS2 DDR_A_DQS#2 <18> DDR_B_D45 AP33 DDR_B_DQS1 <19>
BB35 DDR0_DQ[43]/DDR1_DQ[11] DDR0_DQSN[2]/DDR0_DQSN[4] AY64 DDR1_DQ[44]/DDR1_DQ[28] DDR1_DQSP[1]/DDR0_DQSP[3] AR66 DDR_B_DQS#2 DDR_B_DQS#2 <19>
DDR_A_D45 DDR0_DQSP[2]/DDR0_DQSP[4] DDR_A_DQS2 <18> DDR_B_D46 AR30 DDR1_DQSN[2]/DDR0_DQSN[6]
BA35 DDR0_DQ[44]/DDR1_DQ[12] AY60 DDR_A_DQS#3 DDR1_DQ[45]/DDR1_DQ[29] AR65 DDR_B_DQS2 DDR_B_DQS2 <19>
DDR_A_D46 DDR0_DQSN[3]/DDR0_DQSN[5] DDR_A_DQS#3 <18> DDR_B_D47 AP30 DDR1_DQSP[2]/DDR0_DQSP[6]
BA33 DDR0_DQ[45]/DDR1_DQ[13] BA60 DDR_A_DQS3 DDR1_DQ[46]/DDR1_DQ[30] AR61 DDR_B_DQS#3 DDR_B_DQS#3 <19>
DDR_A_D47 DDR0_DQSP[3]/DDR0_DQSP[5] DDR_A_DQS3 <18>
BB33 DDR0_DQ[46]/DDR1_DQ[14] BA38 DDR_A_DQS#4
DDR_A_DQS#4 <18>
DDR1_DQ[47]/DDR1_DQ[31] DDR1_DQSN[3]/DDR0_DQSN[7] AR60 DDR_B_DQS3 DDR_B_DQS3 <19>
<18> DDR_A_D[48..63] DDR_A_D48 AY31 DDR0_DQ[47]/DDR1_DQ[15] DDR0_DQSN[4]/DDR1_DQSN[0] AY38 DDR_A_DQS4 <19> DDR_B_D[48..63] DDR_B_D48 AU27 DDR1_DQSP[3]/DDR0_DQSP[7] AT38 DDR_B_DQS#4
DDR_A_DQS4 <18> DDR_B_DQS#4 <19>
DDR_A_D49 AW 31 DDR0_DQ[48]/DDR1_DQ[32] DDR0_DQSP[4]/DDR1_DQSP[0] AY34 DDR_A_DQS#5 DDR_B_D49 AT27 DDR1_DQ[48] DDR1_DQSN[4]/DDR1_DQSN[2] AR38 DDR_B_DQS4
DDR_A_DQS#5 <18> DDR_B_DQS4 <19>
DDR_A_D50 AY29 DDR0_DQ[49]/DDR1_DQ[33] DDR0_DQSN[5]/DDR1_DQSN[1] BA34 DDR_A_DQS5 DDR_B_D50 AT25 DDR1_DQ[49] DDR1_DQSP[4]/DDR1_DQSP[2] AT32 DDR_B_DQS#5
DDR_A_DQS5 <18> DDR_B_DQS#5 <19>
DDR_A_D51 AW 29 DDR0_DQ[50]/DDR1_DQ[34] DDR0_DQSP[5]/DDR1_DQSP[1] BA30 DDR_A_DQS#6 DDR_B_D51 AU25 DDR1_DQ[50] DDR1_DQSN[5]/DDR1_DQSN[3] AR32 DDR_B_DQS5
DDR_A_DQS#6 <18> DDR_B_DQS5 <19>
DDR_A_D52 BB31 DDR0_DQ[51]/DDR1_DQ[35] DDR0_DQSN[6]/DDR1_DQSN[4] AY30 DDR_A_DQS6 DDR_B_D52 AP27 DDR1_DQ[51] DDR1_DQSP[5]/DDR1_DQSP[3]
DDR_A_DQS6 <18>
DDR_A_D53 BA31 DDR0_DQ[52]/DDR1_DQ[36] DDR0_DQSP[6]/DDR1_DQSP[4] AY26 DDR_A_DQS#7 DDR_B_D53 AN27 DDR1_DQ[52] AR25 DDR_B_DQS#6
DDR_A_DQS#7 <18> DDR_B_DQS#6 <19>
DDR_A_D54 BA29 DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQSN[7]/DDR1_DQSN[5] BA26 DDR_A_DQS7 DDR_B_D54 AN25 DDR1_DQ[53] DDR1_DQSN[6] AR27 DDR_B_DQS6
DDR_A_DQS7 <18> DDR_B_DQS6 <19>
DDR_A_D55 BB29 DDR0_DQ[54]/DDR1_DQ[38] DDR0_DQSP[7]/DDR1_DQSP[5] DDR_B_D55 AP25 DDR1_DQ[54] DDR1_DQSP[6] AR22 DDR_B_DQS#7
DDR_A_D56 DDR_B_D56 DDR1_DQ[55] DDR1_DQSN[7] DDR_B_DQS7 DDR_B_DQS#7 <19>
AY27 DDR0_DQ[55]/DDR1_DQ[39] AW 50 DDR_A_ALERT# AT22 AR21
DDR_A_D57 DDR_A_ALERT# <18> DDR_B_D57 DDR1_DQ[56] DDR1_DQSP[7] DDR_B_ALERT# DDR_B_DQS7 <19>
AW 27 DDR0_DQ[56]/DDR1_DQ[40] DDR0_ALERT# AT52 DDR_A_PARITY AU22 AN43
DDR_B_ALERT# <19>
DDR_A_D58 AY25 DDR0_DQ[57]/DDR1_DQ[41] DDR0_PAR DDR_A_PARITY <18,20> DDR_B_D58 AU21 DDR1_DQ[57] DDR1_ALERT# AP43 DDR_B_PARITY
DDR_A_D59 DDR1_DQ[58] DDR1_PAR DDR_DRAMRST# DDR_B_PARITY <19>
AW 25 DDR0_DQ[58]/DDR1_DQ[42] DDR CH -A AY67 +0.6V_A_VREFCA DDR_B_D59 AT21 AT13
DDR_VREF_CA +0.6V_A_VREFCA <18> @ DDR1_DQ[59] DRAM_RESET# DDR_DRAMRST# <18,19>
DDR_A_D60 BB27 DDR0_DQ[59]/DDR1_DQ[43] AY68 DDR_B_D60 AN22 DDR CH - B AR18
DDR_A_D61 BA27 DDR0_DQ[60]/DDR1_DQ[44] DDR0_VREF_DQ +0.6V_B_VREFDQ T25 DDR_B_D61 AP22 DDR1_DQ[60] DDR_RCOMP[0]
B BA67 AT18 B
DDR_A_D62 BA25 DDR0_DQ[61]/DDR1_DQ[45] DDR1_VREF_DQ +0.6V_B_VREFDQ <19> DDR_B_D62 AP21 DDR1_DQ[61] DDR_RCOMP[1] SM_RCOMP0
AU18 RC16 1 SDP@ 2 200_0402_1%
DDR_A_D63 BB25 DDR0_DQ[62]/DDR1_DQ[46] 2 OF 20 AW 67 DDR_PG_CTRL DDR_B_D63 AN21 DDR1_DQ[62] 3 OF 20 DDR_RCOMP[2] SM_RCOMP1 RC17 1 2 80.6_0402_1%
DDR0_DQ[63]/DDR1_DQ[47] DDR_VTT_CNTL DDR1_DQ[63] SM_RCOMP2 RC18 1 2 100_0402_1%
SKL-U_BGA1356 @ SKL-U_BGA1356 @
Trace width/Spacing >= 20mils #543016 PDG0.9 P.117
Place componment near SODIMM W=12-15 Space= 20/25 L=500mil
#543016 PDG0.9 P.163 RC place near SODIMM
Recommended By Intel Max

+1.2V
+1.2V +3VS
< For ODT & VTT Power Control >
DDR_VTT_CNTL to DDR
VTT supplied ramped
1
1
<35uS 1 RC20
(tCPU18) CC1 RC132 470_0402_5%
0.1U_0201_10V6K 100K_0402_5% @ RC16
@ SD034121090
2
UC2 2 121_0402_1%
2
1 5 DDR_DRAMRST#
NC DDP@
VCC
DDR_PG_CTRL 2
A 1
4 CC96
Y DDR_VTT_PG_CTRL <45>
3 100P_0402_50V8J
GND ESD@
74AUP1G07SE-7 SOT353 5P LOW PW BUFF 2
SA00007WE00 Close to CPU
A A

Issued Date 2018/03/09 Decipherii ed Dae
t 2019/03/09 Tiitl e
THIS SHEET OF ENGIIINEERIIING DRAWIIING IIS THE PROPRIIETARY PROPERTY OF COMPAL ELECTRONIICS,,, IIINC. AND CONTAIIINS CONFIIIDENTIIIAL AND
SKL-U(2/12)DDR3L
TRADE SECRET IIINFORMATIIION. THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIIISIIION OF R&D Siiize Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONICS,,, IIINC. NEIIITHER THIS SHEET NOR THE IIINFORMATIIION IIT CONTAIIINS
MAY BE USED BY OR DIISCLOSED TO ANY THIRD PARTY WIIITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IIINC.
Custtom
LA-G202P 1..0
Dattte::: Friiiday,,, March 09, 2018 Sheet 7 off 55

5 4 3 2 1
5 4 3 2 1
SML0ALERT# (Internal Pull Down):
eSPI or LPC
0 = LPC is selected for EC ==> Default

+3VALW
1 = eSPI is selected for EC
D D
RC21 1 @ 2 1K_0402_5% SOC_SPI_IO2 +3VS
RPC12
SOC_SML0CLK 1 8
SOC_SML0DATA 2 7
RC22 1 @ 2 1K_0402_5% SOC_SPI_IO3 3 6
4 5
RC24 1 @ 2 1K_0402_5%
499_0804_8P4R_1%
+3VS
UC1E SKL-U
Rev_1.0
SPI - FLASH
SMBUS, SMLINK
SOC_SML1ALERT# RC113 1 @ 2 150K_0402_5%
+3VS SOC_SPI_CLK AV2 R7 SOC_SMBCLK
SOC_SPI_SO AW 3 SPI0_CLK GPP_C0/SMBCLK R8 SOC_SMBDATA SOC_SMBCLK <19> SMB
SOC_SMBDATA <19> RPC2
SOC_SPI_SI AV3 SPI0_MISO GPP_C1/SMBDATA R10 SOC_SMBALERT# (Link to DDR) SOC_SMBCLK 1 8
SOC_SPI_IO2 AW 2 SPI0_MOSI GPP_C2/SMBALERT# TP@ T124 SOC_SMBDATA 2 7
RC112 1 2 10K_0402_5% KB_RST# SOC_SPI_IO3 AU4 SPI0_IO2 R9 SOC_SML0CLK EC_SMB_CK2 3 6
SOC_SPI_CS#0 SPI0_IO3 GPP_C3/SML0CLK SOC_SML0DATA EC_SMB_DA2
AU3 W2 4 5
SPI0_CS0# GPP_C4/SML0DATA SOC_SML0ALERT#
AU2 W1
SPI0_CS1# GPP_C5/SML0ALERT# TP@ T125
AU1 1K_0804_8P4R_5%
SPI0_CS2# W3
+3VS GPP_C6/SML1CLK V3
EC_SMB_CK2 <24,36> SML1
GPP_C7/SML1DATA EC_SMB_DA2 <24,36>
SPI - TOUCH AM7 SOC_SML1ALERT# (Link to EC,DGPU,Thermal Sensor) +3VS
M2 GPP_B23/SML1ALERT#/PCHHOT#
RC25 1 2 8.2K_0402_5% SERIRQ M3 GPP_D1/SPI1_CLK
J4 GPP_D2/SPI1_MISO PM_CLKRUN# RC31 1 2 8.2K_0402_5%
V1 GPP_D3/SPI1_MOSI
V2 GPP_D21/SPI1_IO2 AY13 LPC_AD0
C GPP_D22/SPI1_IO3 GPP_A1/LAD0/ESPI_IO0 BA13 LPC_AD1 LPC_AD0 <36> C
M1 LPC
GPP_A2/LAD1/ESPI_IO1 LPC_AD1 <36>
GPP_D0/SPI1_CS# BB13 LPC_AD2
LPC_AD2 <36>
Follow 543016_SKL_U_Y_PDG_0_9
GPP_A3/LAD2/ESPI_IO2 AY12 LPC_AD3
GPP_A4/LAD3/ESPI_IO3 LPC_AD3 <36>
C LINK BA12 LPC_FRAME#
GPP_A5/LFRAME#/ESPI_CS# LPC_FRAME# <36>
G3 BA11
GPP_A14/SUS_STAT#/ESPI_RESET#
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G2 CL_CLK
G1 CL_DATA
CL_RST# AW 9 LPC_CLK0 RC26 1 EMI@ 2 22_0402_5%
GPP_A9/CLKOUT_LPC0/ESPI_CLK AY9 CLK_LPC_EC <36>
KB_RST# AW 13 GPP_A10/CLKOUT_LPC1 AW 11 PM_CLKRUN#
GPP_A0/RCIN# GPP_A8/CLKRUN# PM_CLKRUN# <36>
SERIRQ AY11
<36> SERIRQ GPP_A6/SERIRQ
5 OF 20
SKL-U_BGA1356 @
RPC1, RPC3 and RC30 are close to UC3

RPC1
SOC_SPI_SO 1 8 SOC_SPI_SO_0_R
SOC_SPI_CLK 2 7 SOC_SPI_CLK_0_R
SOC_SPI_SI 3 6 SOC_SPI_SI_0_R
B SOC_SPI_IO3 4 5 SOC_SPI_IO3_0_R B
From SOC
33_0804_8P4R_5%
EMI@
SOC_SPI_IO2 1 2 SOC_SPI_IO2_0_R
RC30 EMI@ 33_0402_5%
RPC3
EC_SPI_CLK 1 8 SOC_SPI_CLK_0_R
<36> EC_SPI_CLK EC_SPI_MOSI 7 SOC_SPI_SI_0_R
2
<36> EC_SPI_MOSI EC_SPI_CS0# 6 SOC_SPI_CS#0
From EC 3
<36> EC_SPI_CS0# EC_SPI_MISO SOC_SPI_SO_0_R
4 5
<36> EC_SPI_MISO
33_0804_8P4R_5%
EMI@
< SPI ROM - 8MB > - Main Source - XMC

+3VALW
@
UC3 CC2 1 2 0.1U_0201_10V K X5R
SOC_SPI_CS#0 1 8
SOC_SPI_SO_0_R 2 /CS VCC 7 SOC_SPI_IO3_0_R
SOC_SPI_IO2_0_R 3 DO(IO1) /HOLD(IO3) 6 SOC_SPI_CLK_0_R
/W P(IO2) CLK SOC_SPI_SI_0_R
4 5
GND DI(IO0)
1
A S IC FL 64M XM25QH64AHIG SOP 8P A
SA0000B8300 CC3
2 10P_0402_50V8J
@EMI@

Issued Date 2018/03/09 Decipii hered Date 2019/03/09 Tiitl e
SKL-U(3/12)SPI,SMB,LPC,ESPI
TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D Siiize Documentt Number R ev
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIT CONTAIIINS
Custtom
LA-G202P 1..0
Datte:: Friiiday,,, March 09,,,2018 Sheett 8 o ff 55

5 4 3 2 1
5 4 3 2 1
D D
UC1G SKL-U
Rev_1.0
< HD AUDIO >
AUDIO
RPC4
1 8 HDA_BIT_CLK HDA_SYNC BA22
<30> HDA_BITCLK_AUDIO 7 HDA_SYNC HDA_BIT_CLK HDA_SYNC/I2S0_SFRM
2 AY22
<30> HDA_SYNC_AUDIO HDA_SDOUT HDA_BLK/I2S0_SCLK
3 6 BB22 SDIO / SDXC
HDA_SDO/I2S0_TXD
4 5 HDA_SDOUT <30> HDA_SDIN0
BA21
<30> HDA_SDOUT_AUDIO AY21 HDA_SDI0/I2S0_RXD AB11
AW 22 HDA_SDI1/I2S1_RXD GPP_G0/SD_CMD AB13
33_0804_8P4R_5%
J5 HDA_RST#/I2S1_SCLK GPP_G1/SD_DATA0 AB12
EMI@
GPP_D23/I2S_MCLK GPP_G2/SD_DATA1 W 12
AY20
AW 20 I2S1_SFRM GPP_G3/SD_DATA2 W 11
I2S1_TXD GPP_G4/SD_DATA3 W 10
< To Enable ME Override > AK7 GPP_G5/SD_CD# W8
AK6 GPP_F1/I2S2_SFRM GPP_G6/SD_CLK W7
AK9 GPP_F0/I2S2_SCLK GPP_G7/SD_W P
AK10 GPP_F2/I2S2_TXD BA9
GPP_F3/I2S2_RXD GPP_A17/SD_PW R_EN#/ISH_GP7 BB9
GPP_A16/SD_1P8_SEL
H5 AB7 RC76 1 @ 2 200_0402_1%
D7 GPP_D19/DMIC_CLK0 SD_RCOMP
GPP_D20/DMIC_DATA0
D8 AF13
C8 GPP_D17/DMIC_CLK1 GPP_F23
RC116 1 2 0_0402_5% HDA_SDOUT GPP_D18/DMIC_DATA1
<36> ME_EN HDA_SPKR AW 5
<30> HDA_SPKR GPP_B14/SPKR
C C
7 OF 20
SKL-U_BGA1356 @
+3VS
Vinafix.com
RC33 1 @ 2 2.2K_0402_5% HDA_SPKR
SPKR (Internal Pull Down):

A36
D38
C36
D36
UC1I
B36 CSI2_DN0
C38
CSI-2
CSI2_DP0
CSI2_DN1
CSI2_DP1
CSI2_DN2
A38 CSI2_DP2
SKL-U
Rev_1.0
CSI2_CLKN0
CSI2_CLKP0
CSI2_CLKN1
CSI2_CLKP1
CSI2_CLKN2
C37
D37
C32
D32
C29
D29
CSI2_CLKP2 B26
TOP Swap Override B38 CSI2_DN3 CSI2_CLKN3 A26
B CSI2_DP3 CSI2_CLKP3 B
C31 E13 RC80 1 @ 2 100_0402_1%
0 = Disable TOP Swap mode. ==> Default D31 CSI2_DN4 CSI2_COMP B7
C33 CSI2_DP4 GPP_D4/FLASHTRIG
D33 CSI2_DN5
1 = Enable TOP Swap Mode. CSI2_DP5 EMMC
A31
B31 CSI2_DN6 AP2
A33 CSI2_DP6 GPP_F13/EMMC_DATA0 AP1
B33 CSI2_DN7 GPP_F14/EMMC_DATA1 AP3
CSI2_DP7 GPP_F15/EMMC_DATA2 AN3
A29 GPP_F16/EMMC_DATA3 AN1
B29 CSI2_DN8 GPP_F17/EMMC_DATA4 AN2
C28 CSI2_DP8 GPP_F18/EMMC_DATA5 AM4
D28 CSI2_DN9 GPP_F19/EMMC_DATA6 AM1
A27 CSI2_DP9 GPP_F20/EMMC_DATA7
B27 CSI2_DN10 AM2
C27 CSI2_DP10 GPP_F21/EMMC_RCLK AM3
D27 CSI2_DN11 GPP_F22/EMMC_CLK AP4
CSI2_DP11 GPP_F12/EMMC_CMD
9 OF 20 AT1 RC129 1 @ 2 200_0402_1%
EMMC_RCOMP
SKL-U_BGA1356 @
A A
Securiiity Clllassiiifiiicatiiion
2018/03/09
Compal Secret Data
2019/03/09 Tiitl e
Issued Date Deciiiphered Date
SKL-U(4/12)HDA,EMMC,SDIO,CSI2
Custttom
LA-G202P 1..0

5 4 3 2 1
5 4 3 2 1
U22_EMI@
SOC_XTAL24_IN RC154 1 2 33_0402_1% XTAL24_IN
U22_EMI@
SOC_XTAL24_OUT RC155 1 2 33_0402_1% XTAL24_OUT
U22@
RC34 1 2 1M_0402_5%
D D
YC1 U22@
UC1J SKL-U 24MHZ_18PF_XRCGB24M000F2P51R0
Rev_1.0 SJ10000UJ00
CLOCK SIGNALS
1 3
D42 1 3
<21> CLK_PEG_VGA# C42 CLKOUT_PCIE_N0 NC NC
DGPU <21> CLK_PEG_VGA VGA_CLKREQ# AR10 CLKOUT_PCIE_P0
<21> VGA_CLKREQ# GPP_B5/SRCCLKREQ0# 2 4
U22@ U22@
B42
27P_0402_50V8J
27P_0402_50V8J
<31> CLK_PCIE_LAN# A42 CLKOUT_PCIE_N1 F43 1 1
LAN <31> CLK_PCIE_LAN LANCLK_REQ# AT7 CLKOUT_PCIE_P1 CLKOUT_ITPXDP_N E43
+3VS
CC4
CC5
<31> LANCLK_REQ# GPP_B6/SRCCLKREQ1# CLKOUT_ITPXDP_P
RPC6 D41 BA17 SUSCLK 2 2
<33> CLK_PCIE_WLAN# C41 CLKOUT_PCIE_N2 GPD8/SUSCLK SUSCLK <33>
8 1 VGA_CLKREQ# NGFF WL+BT <33> CLK_PCIE_WLAN
7 2 WLANCLK_REQ# WLANCLK_REQ# AT8 CLKOUT_PCIE_P2 E37 SOC_XTAL24_IN
3 <33> WLANCLK_REQ# GPP_B7/SRCCLKREQ2# XTAL24_IN E35 SOC_XTAL24_OUT
6 EC_SCI# <6,36>
5 4 LANCLK_REQ# D40 XTAL24_OUT
C40 CLKOUT_PCIE_N3 E42 XCLK_BIASREF
10K_0804_8P4R_5% AT10 CLKOUT_PCIE_P3 XCLK_BIASREF
GPP_B8/SRCCLKREQ3# AM18 SOC_RTCX1 +1.0V_CLK5_F24NS
B40 RTCX1 AM20 SOC_RTCX2
A40 CLKOUT_PCIE_N4 RTCX2
AU8 CLKOUT_PCIE_P4 AN18 SOC_SRTCRST# XCLK_BIASREF RC35 1 2 2.7K_0402_1%
GPP_B9/SRCCLKREQ4# SRTCRST# AM16 SOC_RTCRST#
E40 RTCRST# RC110 1 @ 2 60.4_0402_1%
E38 CLKOUT_PCIE_N5
AU7 CLKOUT_PCIE_P5
GPP_B10/SRCCLKREQ5#
10 OF20
SKL-U_BGA1356 @
Follow 546765_2014WW48_Skylake_MOW_Rev_1_0
C
+3VL_RTC Stuff 2.7k ohm (RC35) PU for SkyLake-U C
Stuff 60.4 ohm (RC110) PD for CannonLake-U

RC36 1 2 20K_0402_5% SOC_SRTCRST#
Vinafix.com
CC6 1 2 1U_0201_6.3V6M
SE00000UC00 < PCH PLTRST Buffer >
RC42 1 @ 2 0_0402_5%
RC37 1 2 20K_0402_5% SOC_RTCRST# RC38 1 2 0_0402_5% EC_CLEAR_CMOS# <36> +3VS

CC7 1 2 1U_0201_6.3V6M
SE00000UC00 SOC_RTCX2
CLRP2 1 2 SHORT PADS CLR CMOS
5
UC4 @
SOC_PLTRST# 1
RC39 1 2 1M_0402_5% SM_INTRUDER# B 4 SOC_RTCX1
Y PCI_RST# <21,31,33,36>
G P
2
A
J
100P_0402_50V8
%
100K_0402_5
RC41 1 2 10M_0402_5%
1
TC7SH08FUF_SSOP5
RC44
SA007080100 ESD@
CC8
21
YC2
2
1 2
+3VALW S CRYSTAL 32.768KHZ 9PF X1A000141000200

SJ10000PW00
C
6.8P_0402_50V8
C
6.8P_0402_50V8
RPC7 1 1
8 1 PCH_PWROK
7 2 EC_RSMRST#
CC9
CC10
6 3 LAN_WAKE#
5 4 SYS_RESET# 2 2
B B
10K_0804_8P4R_5% UC1K SKL-U
Rev_1.0
SYSTEM POWER MANAGEMENT
AT11 PM_SLP_S0#
GPP_B12/SLP_S0# AP15 PM_SLP_S3# TP@T130
SOC_PLTRST# AN10 GPD4/SLP_S3# BA16 PM_SLP_S4# PM_SLP_S3# <36>
SYS_RESET# B5 GPP_B13/PLTRST# GPD5/SLP_S4# AY16 PM_SLP_S5# PM_SLP_S4# <36,43,46>
SYS_RESET# EC_RSMRST# AY17 SYS_RESET# GPD10/SLP_S5# TP@T131
ESD@ 1 2
100P_0402_50V8J <36> EC_RSMRST# RSMRST#
CC97 AN15
EC_RSMRST# H_CPUPW RGD SLP_SUS# AW 15
ESD@ 1 2
100P_0402_50V8J
Only For Power Sequence Debug T132 TP@ EC_VCCST_PG
A68
B65 PROCPW RGD SLP_LAN# BB17 SLP_WLAN#
CC94 TP@T133
2 SYS_PWROK VCCST_PW RGD GPD9/SLP_W LAN# AN16 PM_SLP_A#
ESD@ 1
100P_0402_50V8J SYS_PW ROK GPD6/SLP_A# TP@T134
CC95 B6
<36> SYS_PWROK PCH_PW ROK BA20 SYS_PW ROK BA15 PBTN_OUT#
<36> PCH_PWROK GPD3/PW RBTN# AY15 AC_PRESENT_R PBTN_OUT# <36>
EC_RSMRST# BB20 PCH_PW ROK RC103 1 @ 2 0_0402_5%
DSW _PW ROK GPD1/ACPRESENT AU13 PM_BATLOW# AC_PRESENT <24,36>
AR13 GPD0/BATLOW #
AP11 GPP_A13/SUSW ARN#/SUSPW RDNACK +3VALW
GPP_A15/SUSACK# AU11
BB15 GPP_A11/PME# AP16 SM_INTRUDER#
WAKE#
+3VALW LAN_W AKE# AM15 W AKE# INTRUDER# PM_BATLOW # RC46 1 2 8.2K_0402_5%
AW 17 GPD2/LAN_W AKE# AM10
1 2 W AKE# AT15 GPD11/LANPHYPC GPP_B11/EXT_PW R_GATE# AM11 SOC_VRALERT# AC_PRESENT RC48 1 @ 2 10K_0402_5%
GPD7/RSVD 11 OF 20 GPP_B2/VRALERT#
RC47 1K_0402_5%
SOC_VRALERT# RC50 1 @ 2 10K_0402_5%
SKL-U_BGA1356 @
From EC (Open-Drain)
+1.0V_VCCST
1
RC52
1K_0402_5%
2
A A
RC53 1 2 60.4_0402_1% EC_VCCST_PG
<36> VCCST_PWRGD
CC117
100P_0402_50V8J
2 ESD@

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IINC... AND CONTAIIINS CONFIIIDENTIIIAL
SKL-U(5/12)CLK,PM,GPIO
AND TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D Siiize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIT CONTAIIINS MAY BE USED
BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IINC...
Custtom
LA-G202P 1..0
Date: Friiiday,,, March 09,,,2018 Sheet 10 o ff 55

5 4 3 2 1
5 4 3 2 1
Capacity Description X76 PART NUMBER R3

GSPI0_MOSI (Internal Pull Down): ( )
WITHOUT ON-BOARD RAM N/A N/A
No Reboot SAMSUNG 2666MHz K4A8G165WC-BCTD X7677538L13 SA0000B6F10
(
HYNIX 2666MHz H5AN8G6NCJR-VKC ) X7677538L15 SA0000BMN10
0 = Disable No Reboot mode. ==> Default
( )
MICRON 2666MHzMT40A512M16LY-075:E X7677538L14 SA0000ARD30
1 = Enable No Reboot Mode. (PCH will disable the TCO 4GB N/A ( ) N/A N/A +3VS +3VS +3VS
Timer system reboot feature). This funct i oni s us eful
D
when running ITP/XDP. N/A N/A N/A D
N/A N/A N/A
1
RC135 RC133 RC215
N/A N/A N/A 10K_0402_5% 10K_0402_5% 10K_0402_5%
@ X76RAM@ X76RAM@
GSPI1_MOSI (Internal Pull Down): Function HDD ODD DETECT
_ D11_
2
GPP
OBRAM_ID0 OBRAM_ID1 OBRAM_ID2
Mount ODD ( _
0 )
GPP B19 GPP B20 GPP B21
1
Boot BIOS Strap Bit
Capacity Description _ _ _ RC214 RC134 RC138
Mount 2nd HDD 1
OBRAM ID 0 OBRAM ID 1 OBRAM ID2 10K_0402_5% 10K_0402_5% 10K_0402_5%
0 = SPI Mode ==> Default WITHOUT ON-BOARD RAM 0_ 0_ 0_
X76RAM@ X76RAM@ X76RAM@
2
1 = LPC Mode SAMSUNG 2666MHz K4A8G165WC-BCTD 0 0 1
(
HYNIX 2666MHz H5AN8G6NCJR-VKC ) 0 1 0
+3VS
+3VS ( )
MICRON 2666MHzMT40A512M16LY-075:E 0 1 1
4GB N/A ( ) 1 0 0
1 2 HDD_ODD_DETECT
HDD_ODD_DETECT <35>
RC208 10K_0402_5%
GSPI0_MOSI 1@ 2
N/A 1 0 1
RC59 1 @ 2 4.7K_0402_5%
RC207 10K_0402_5%
150K_0402_5% GSPI1_MOSI
N/A 1 1 0
RC60 1 @ 2
N/A 1 1 1
Function MODEL SETTING

GPP_ D12
15" ( _0 )
14" 1
C C
UC1F SKL-U
Rev_1.0
LPSS ISH
+3VS
Vinafix.com
RPC10 AN8 P2
+3VS 1 8 AP7 GPP_B15/GSPI0_CS# GPP_D9 P3
2 7 SOC_GPIOB17 AP8 GPP_B16/GSPI0_CLK GPP_D10 P4 HDD_ODD_DETECT RC206 1 14@ 2 10K_0402_5% MODEL_SETTING
3 6 UART0_RX GSPI0_MOSI AR7 GPP_B17/GSPI0_MISO GPP_D11 P1 MODEL_SETTING
4 5 UART0_TX GPP_B18/GSPI0_MOSI GPP_D12
RC205 1 15@ 2 10K_0402_5%
OBRAM_ID0 AM5 M4
49.9K_0804_8P4R_1% OBRAM_ID1 AN7 GPP_B19/GSPI1_CS# GPP_D5/ISH_I2C0_SDA N3
OBRAM_ID2 AP5 GPP_B20/GSPI1_CLK GPP_D6/ISH_I2C0_SCL
GSPI1_MOSI AN5 GPP_B21/GSPI1_MISO N1
GPP_B22/GSPI1_MOSI GPP_D7/ISH_I2C1_SDA
N2
+3VS GPP_D8/ISH_I2C1_SCL
AB1
<38> TP_INT# GPP_C8/UART0_RXD
AB2 AD11
SOC_GPIOC10 W4 GPP_C9/UART0_TXD GPP_F10/I2C5_SDA/ISH_I2C2_SDA AD12
RPC8
DGPU PRSNT
DGPU_PWR_EN GPP_C10/UART0_RTS# GPP_F11/I2C5_SCL/ISH_I2C2_SCL
8 1 AB3
7 2 DGPU_HOLD_RST# <33> WLBT_OFF# GPP_C11/UART0_CTS#
Function _ C15
GPP
( 0_ )
6 3 AD1 U1
5 4 W LBT_OFF# <33> UART0_RX
<33> UART0_TX
AD2 GPP_C20/UART2_RXD GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA U2 DIS
AD3 GPP_C21/UART2_TXD GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL U3
10K_0804_8P4R_5% AD4 GPP_C22/UART2_RTS# GPP_D15/ISH_UART0_RTS# U4 UMA Only 1
GPP_C23/UART2_CTS# GPP_D16/ISH_UART0_CTS#/SML0BALERT#
AC1 DGPU_PWR_EN
GPP_C12/UART1_RXD/ISH_UART1_RXD AC2 DGPU_HOLD_RST# DGPU_PWR_EN <26,36>
U7
<38> I2C0_SDA_TP GPP_C16/I2C0_SDA GPP_C13/UART1_TXD/ISH_UART1_TXD GPU_ALL_PGOOD DGPU_HOLD_RST# <21>
Touch PAD <38> I2C0_SCL_TP
U6
GPP_C17/I2C0_SCL GPP_C14/UART1_RTS#/ISH_UART1_RTS#
AC3
DGPU_PRSNT GPU_ALL_PGOOD <26>
AB4 +3VS
GPP_C15/UART1_CTS#/ISH_UART1_CTS#
U8
U9 GPP_C18/I2C1_SDA AY8 DGPU_PRSNT
RC61 1 UMA@ 2 10K_0402_5%
GPP_C19/I2C1_SCL GPP_A18/ISH_GP0 BA8
GPP_A19/ISH_GP1 BB7 DGPU_SEL
AH9 RC62 1 DIS@ 2 10K_0402_5%
GPP_F4/I2C2_SDA GPP_A20/ISH_GP2
AH10 BA7
GPP_F5/I2C2_SCL GPP_A21/ISH_GP3
AY7
GPP_A22/ISH_GP4
B AH11 AW 7 B
GPP_F6/I2C3_SDA GPP_A23/ISH_GP5
AH12 AP13
GPP_F7/I2C3_SCL Sx_EXIT_HOLDOFF# / GPP_A12 / BM_BUSY# / ISH_GP6
AF11
AF12 GPP_F8/I2C4_SDA
RPC11 GPP_F9/I2C4_SCL 6 OF 20 Function DGPU SEL
+3VS 8 1
GPP_ A20
7
6
2
3 I2C0_SCL_TP
SKL-U_BGA1356 @
N16V-GMR1 MX110 ( 0_ ) RC210 N16S_R3@
10K_0402_5%
N16S-GTR( MX130
)
5 4 I2C0_SDA_TP
1
2.2K_0804_8P4R_5% ( ) RC209 N16V_R3@
10K_0402_5%
+3VS
N16S_R1@
RC210 1 2 10K_0402_5% DGPU_SEL
N16V_R1@
RC209 1 2 10K_0402_5%
*N16V - MX110 Device ID: 0x174E
*N16S - MX130 ( Device ID: 0x174D)
( )
SOC_GPIOC10 RC204 1 2 0_0402_5% GPU_EVENT#

GPU_EVENT# <24>
TO DGPU
SOC_GPIOB17 RC195 1 2 0_0402_5% GC6_FB_EN GC6_FB_EN <24,25>
A A

SKL-U(6/12)GPIO,I2C,GSPI
AND TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D Siiize Documentt Number Rev
Custtom
LA-G202P 1..0

5 4 3 2 1
5 4 3 2 1
D D
UC1H @ SKL-U
Rev_1.0
SSIC / USB3
PCIE / USB3 / SATA
H8
USB3_1_RXN G8
H13 USB3_1_RXP C13
<21> PCIE_PRX_DTX_N1 PCIE1_RXN/USB3_5_RXN USB3_1_TXN
<21> PCIE_PRX_DTX_P1 G13 D13
PCIE1_RXP/USB3_5_RXP USB3_1_TXP
CC11 DIS@ 1 2 0.22U_0402_6.3V6K PCIE_PTX_DRX_N1 B17
<21> PCIE_PTX_C_DRX_N1 PCIE1_TXN/USB3_5_TXN
<21> PCIE_PTX_C_DRX_P1 CC14 DIS@ 1 2 0.22U_0402_6.3V6K PCIE_PTX_DRX_P1 A17 J6
USB3_RX2_N <37>
PCIE1_TXP/USB3_5_TXP USB3_2_RXN / SSIC_RXN H6
USB3_2_RXP / SSIC_RXP USB3_RX2_P <37>
G11 B13
<21> PCIE_PRX_DTX_N2
F11 PCIE2_RXN/USB3_6_RXN USB3_2_TXN / SSIC_TXN A13
USB3_TX2_N <37> USB2.0 / 3.0 Port (MB - 1)
<21> PCIE_PRX_DTX_P2 PCIE2_RXP/USB3_6_RXP USB3_2_TXP / SSIC_TXP USB3_TX2_P <37>
CC15 DIS@ 1 2 0.22U_0402_6.3V6K PCIE_PTX_DRX_N2 D16
<21> PCIE_PTX_C_DRX_N2 PCIE2_TXN/USB3_6_TXN
CC16 DIS@ 1 2 0.22U_0402_6.3V6K PCIE_PTX_DRX_P2 C16 J10
USB3_RX3_N <37>
<21> PCIE_PTX_C_DRX_P2 PCIE2_TXP/USB3_6_TXP USB3_3_RXN
dGPU USB3_3_RXP
H10
USB3_RX3_P <37>
H16 B15
G16 PCIE3_RXN USB3_3_TXN A15
USB3_TX3_N <37> USB2.0 / 3.0 Port (MB - 2)
PCIE3_RXP USB3_3_TXP USB3_TX3_P <37>
<21> PCIE_PRX_DTX_P3 CC12 DIS@ 1 2 0.22U_0402_6.3V6K PCIE_PTX_DRX_N3 D17
<21> PCIE_PTX_C_DRX_N3 CC13 DIS@ 1 2 0.22U_0402_6.3V6K PCIE_PTX_DRX_P3 C17 PCIE3_T XN E10
<21> PCIE_PTX_C_DRX_P3 PCIE3_TXP USB3_4_RXN F10
G15 USB3_4_RXP C15
<21> PCIE_PRX_DTX_N4 F15 PCIE4_RXN USB3_4_TXN D15
<21> PCIE_PRX_DTX_P4 PCIE4_RXP USB3_4_TXP
CC17 DIS@ 1 2 0.22U_0402_6.3V6K PCIE_PTX_DRX_N4 B19
<21> PCIE_PTX_C_DRX_N4 CC18 DIS@ 1 2 0.22U_0402_6.3V6K PCIE_PTX_DRX_P4 A19 PCIE4_T XN AB9
<21> PCIE_PTX_C_DRX_P4 PCIE4_TXP USB2N_1 AB10
USB2P_1
F16
<31> PCIE_PRX_DTX_N5 E16 PCIE5_RXN AD6 USB20_N2
<31> PCIE_PRX_DTX_P5 PCIE5_RXP USB2N_2 USB20_P2 USB20_N2 <37>
C
LAN <31> PCIE_PTX_DRX_N5
C19
PCIE5_TXN USB2P_2
AD7
USB20_P2 <37> USB2.0 / 3.0 Port (MB - 1) C
D19
<31> PCIE_PTX_DRX_P5 PCIE5_TXP USB20_N3
AH3
USB2N_3 USB20_P3 USB20_N3 <37>
<33> PCIE_PRX_DTX_N6 G18 AJ3 USB2.0 / 3.0 Port (MB - 2)
PCIE6_RXN USB2P_3 USB20_P3 <37>
<33> PCIE_PRX_DTX_P6 F18
PCIE6_RXP
NGFF WLAN+BT <33> PCIE_PTX_DRX_N6 D20
PCIE6_T XN
AD9
Vinafix.com
C20 USB2N_4 AD10
<33> PCIE_PTX_DRX_P6
PCIE6_TXP USB2P_4
F20 AJ1 USB20_N5
<34> SATA_PRX_DTX_N0 PCIE7_RXN/SATA0_RXN USB2N_5 USB20_P5 USB20_N5 <28>
E20 AJ2 Camera
<34> SATA_PRX_DTX_P0 PCIE7_RXP/SATA0_RXP USB2P_5 USB20_P5 <28>
HDD <34> SATA_PTX_DRX_N0
B21
PCIE7_TXN/SATA0_TXN
USB2
USB20_N6
A21 AF6
<34> SATA_PTX_DRX_P0 PCIE7_TXP/SATA0_TXP USB2N_6 USB20_P6 USB20_N6 <32>
AF7 Card Reader
USB2P_6 USB20_P6 <32>
G21
<35> SATA_PRX_DTX_N1 F21 PCIE8_RXN/SATA1A_RXN AH1 USB20_N7
<35> SATA_PRX_DTX_P1 PCIE8_RXP/SATA1A_RXP USB2N_7 USB20_P7 USB20_N7 <33>
ODD <35> SATA_PTX_DRX_N1
D21
PCIE8_TXN/SATA1A_TXN USB2P_7
AH2
USB20_P7 <33> NGFF WLAN+BT
C21
<35> SATA_PTX_DRX_P1 PCIE8_TXP/SATA1A_TXP
AF8
E22 USB2N_8 AF9
E23 PCIE9_RXN USB2P_8
B23 PCIE9_RXP AG1
A23 PCIE9_T XN USB2N_9 AG2
PCIE9_TXP USB2P_9
F25 AH7
E25 PCIE10_RXN USB2N_10 AH8 +3VALW
D23 PCIE10_RXP USB2P_10
PCIE10_T XN USB2_COMP RC70 1 RPC9
C23 AB6 2 113_0402_1%
PCIE10_TXP USB2_COMP AG3 RC104 1 2 1K_0402_5% USB_OC1# 8 1
RC71 1 2 100_0402_1% PCIE_RCOMPN F5 USB2_ID AG4 RC105 1 2 1K_0402_5% USB_OC3# 7 2
PCIE_RCOMPP E5 PCIE_RCOMPN USB2_VBUSSENSE USB_OC0# 6 3
PCIE_RCOMPP A9 USB_OC0# USB_OC2# 5 4
XDP_PRDY# D56 GPP_E9/USB2_OC0# C9 USB_OC1#
T147 TP@ XDP_PREQ# PROC_PRDY# GPP_E10/USB2_OC1# USB_OC2# USB_OC1# <37>
D61 D9 10K_0804_8P4R_5%
T148 TP@ PROC_PREQ# GPP_E11/USB2_OC2# USB_OC3#
BB11 B9
GPP_A7/PIRQA# GPP_E12/USB2_OC3#
E28 J1
B E27 PCIE11_RXN/SATA1B_RXN GPP_E4/DEVSLP0 J2 B
PCIE11_RXP/SATA1B_RXP GPP_E5/DEVSLP1 WL_OFF# <33>
D24 J3
PCIE11_TXN/SATA1B_TXN GPP_E6/DEVSLP2
C24
E30 PCIE11_TXP/SATA1B_TXP H2 +3VS
PCIE12_RXN/SATA2_RXN GPP_E0/SATAXPCIE0/SATAGP0
F30 H3
PCIE12_RXP/SATA2_RXP GPP_E1/SATAXPCIE1/SATAGP1
A25 G4
PCIE12_TXN/SATA2_TXN GPP_E2/SATAXPCIE2/SATAGP2
B25
PCIE12_TXP/SATA2_TXP H1 W L_OFF# RC139 1 @ 2 10K_0402_5%
8 OF 20 GPP_E8/SATALED#
SKL-U_BGA1356
When PCIE8/SATA1A is used as SATA Port 1 (ODD), then

PCIE11/SATA1B (M.2 SSD) cannot be used as SATA Port 1.
A A

SKL-U(7/12)PCIE,USB,SATA
AND TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D Siiize Document Number Rev
Custtom
LA-G202P 1..0

5 4 3 2 1
5 4 3 2 1
+1.2V +1.0VS_VCCIO
UC1N @ SKL-U
Rev_1.0
+VL +1.0VALW I(Max) : 0.16 A(+1.0V_VCCST) +1.0V_VCCST CPU POWER 3 OF 4
RON(Max) : 25 mohm AU23 AK28
+1.0VALW TO +1.0V_VCCST V drop : 0.004 V AU28
AU35
VDDQ_AU23
VDDQ_AU28
VCCIO
VCCIO
AK30
AL30
D VDDQ_AU35 VCCIO D
AU42 AL42
VDDQ_AU42 VCCIO
0.1U_0201_10V K X5R
CC21 CC22 @ BB23 AM28
1U_0201_6.3V6M 1U_0201_6.3V6M +1.0V_VCCST_R 2 1 BB32 VDDQ_BB23 VCCIO AM30
SE00000UC00 SE00000UC00 RC136 0_0402_5% BB41 VDDQ_BB32 VCCIO AM42 +VCCSA
VDDQ_BB41 VCCIO
2
+1.0VS_VCCIO BB47
1 VDDQ_BB47
CC23
BB51 AK23
VDDQ_BB51 VCCSA AK25
UC5 VCCSA G23
1 14 2 +1.0V_VCCST AM40 VCCSA G25
2 VIN1 VOUT1 13 VDDQC VCCSA G27
VIN1 VOUT1 A18 VCCSA G28
EN_1.0V_VCCSTU 3 VCCST VCCSA
RC74 2 1 0_0402_5% 12 1 2 J22
<36,45> SYSON ON1 CT1 CC24 Follow 543977_SKL_PDDG_Rev0_91 A22 VCCSA J23
VCCSTG_A22
4 11 8200P_0402_25V7K CC24 10PF ->22us(Spec:<= 65us) VCCSA J27
VBIAS GND AL23 VCCSA K23
EN_1.8VS VCCPLL_OC VCCSA
RC75 2 1 0_0402_5% 5 10 1 2 K25
<36,40,45> SUSP# ON2 CT2 CC25 K20 VCCSA K27
6 9 1000P_0402_50V7K K21 VCCPLL_K20 VCCSA K28
+1.8VALW 7 VIN2 VOUT2 8 +1.8VS VCCPLL_K21 VCCSA K30
VIN2 VOUT2 VCCSA
15 AM23
GPAD +1.8VS_R 2 VCCIO_SENSE
0.1U_0201_10V K X5R
1 RC137 AM22
S IC JW7110DFNC#TRPBF DFN14 DUAL LOAD SW 0_0402_5% VSSIO_SENSE
H21 VSSSA_SENSE
SA0000BEL00 VSSSA_SENSE VSSSA_SENSE <48>
1
@ CC26 H20 VCCSA_SENSE
1 VCCSA_SENSE VCCSA_SENSE <48>
CC27
1U_0201_6.3V6M 14 OF 20
SE00000UC00
+1.8VALW TO +1.8VS
2
I(Max) : 0.2 A(+1.8VS) SKL-U_BGA1356 Trace Length Match < 25 mils
2
RON(Max) : 25 mohm
V drop : 0.005 V
C C
+VL
Vinafix.com
+1.0VALW
+1.0VALW TO +1.0VS_VCCIO
I(Max) : 3.04 A(+1.0VS_VCCIO)

RON(Max) : 6.2 mohm
Reserved for BSoD 0x124 Issue
+1.0V_VCCST
PSC Side
+1.0VS_VCCIO
BSC Side
0.1U_0201_10V K X5R
V drop : 0.019 V
1
1
CC30
CC32
1U_0201_6.3V6M
@ SE00000UC00 UC6
2
2 1 +1.0VS_VCCIO
1 1
2 VIN1 CC128 CC129 CC35 @
VIN2 10U_0603_6.3V6M 10U_0603_6.3V6M 1U_0201_6.3V6M
+1.0VS_VCCIO_STG
21
7 6 RC79 1 2 0_0805_5% SE00000UC00
VIN thermal VOUT 2 2
1
3
VBIAS CC33
SUSP# RC81 2 1 0_0402_5% 4 5 @ 0.1U_0201_10V K X5R
ON GND 2
B B
AOZ1334DI-01_DFN 8P Close to A18 Close to K20 Close to A22
+1.0VS_VCCIO +1.2V
BSC Side PSC Side BSC Side PSC Side BSC Side
CC38 SE00000UC00
@ 1U_0201_6.3V6M
CC49 SE00000UC00
CC37 SE00000UC00
@ 1U_0201_6.3V6M
CC50 SE00000UC00
M
10U_0603_6.3V6
1U_0201_6.3V6M
CC39 SE00000UC00
1U_0201_6.3V6M
CC41 SE00000UC00
M
22U_0603_6.3V6
M
10U_0603_6.3V6
1U_0201_6.3V6M @
CC40 SE00000UC00
1U_0201_6.3V6M
CC42 SE00000UC00
M
1U_0201_6.3V6
1U_0201_6.3V6M
CC43 SE00000UC00
M
10U_0603_6.3V6
M
10U_0603_6.3V6
M
10U_0603_6.3V6
SE00000UC00
M
1U_0201_6.3V6
M
1U_0201_6.3V6
1 1 1 1 1 1
1
1
1
1
1
CC36
CC44
CC45
CC29
CC46
CC47
CC48
@ @
2
2
2
2
2
2
2 2 2 2 2 2
@ @
Under CPU Close to CPU Close to AL23 Close to AM40 Close to CPU Under CPU
A A
2018/03/09
Compal Secret Data
2019/03/09 Tiitl e
SKL-U(8/12)Power
Custttom
LA-G202P 1..0

5 4 3 2 1
5 4 3 2 1
D D
+1.0VALW +1.8VALW
UC1O SKL-U
Rev_1.0 +3VALW
CPU POWER 4 OF 4
AB19
Follow 543016_SKL_U_Y_PDG_1_0 CC51 1 2 1U_0201_6.3V6M
AB20 VCCPRIM_1P0 AK15
SE00000UC00 VCCPRIM_1P0 VCCPGPPA
+1.0VALW +1.0V_APLL P18 AG15
@ VCCPRIM_1P0 VCCPGPPB
Y16
LC1 CC54 1 2 1U_0201_6.3V6M AF18 VCCPGPPC Y15
MURATA BLM15EG221SN1D SE00000UC00 AF19 VCCPRIM_CORE VCCPGPPD T16
1 2 @ Imax : 2.57A V20 VCCPRIM_CORE VCCPGPPE AF16 VCCPGPPF support 1.8V only
SM01000BV00 RF@ V21 VCCPRIM_CORE VCCPGPPF AD15
0.1U_0201_10V K X5R
VCCPRIM_CORE VCCPGPPG
R_0402 2
CC31
RF@
CC55 1 2 1U_0201_6.3V6M DCPDSW AL1 V19
SE00000UC00 DCPDSW _1P0 VCCPRIM_3P3_V19
CC56 1 2 1U_0201_6.3V6M K17 T1
1 L1 VCCMPHYAON_1P0 VCCPRIM_1P0_T1 +1.0VALW
Close to K17 SE00000UC00 VCCMPHYAON_1P0
AA1 CC57 1 2 1U_0201_6.3V6M
CC60 1 2 22U_0603_6.3V6M N15 VCCATS_1P8 SE00000UC00
N16 VCCMPHYGT_1P0_N15 AK17
Imax : 1.54A N17 VCCMPHYGT_1P0_N16 VCCRTCPRIM_3P3
@
Follow 543016_SKL_U_Y_PDG_1_0 CC61 1 2 1U_0201_6.3V6M P15 VCCMPHYGT_1P0_N17 AK19
VCCMPHYGT_1P0_P15 VCCRTC_AK19 +3VL_RTC
Close to P15 SE00000UC00 P16 BB14
+1.0V_AMPHYPLL VCCMPHYGT_1P0_P16 VCCRTC_BB14
K15 BB10 DCPRTC CC62 1 2 0.1U_0201_10V K X5R
+1.0V_AMPHYPLL VCCAMPHYPLL_1P0 DCPRTC
L15
VCCAMPHYPLL_1P0 A14
VCCCLK1 +1.0V_CLK6_24TBT
V15
+1.0V_APLL VCCAPLL_1P0
1U_0201_6.3V6M
K19
M
22U_0603_6.3V6
VCCCLK2
SE00000UC00
1 AB17
Y18 VCCPRIM_1P0_AB17
1
CC59 @
L21
CC58
VCCPRIM_1P0_Y18 VCCCLK3 +1.0V_APLL

@ AD17 N20
+3VALW VCCDSW _3P3_AD17 VCCCLK4 +1.0V_CLK4_F100OC
2
2 AD18
AJ17 VCCDSW _3P3_AD18 L19
C VCCDSW _3P3_AJ17 VCCCLK5 +1.0V_CLK5_F24NS C
AJ19 A10
+3V_1.8V_HDA VCCHDA VCCCLK6 +1.0V_CLK6_24TBT
AJ16 AN11
VCCSPI GPP_B0/CORE_VID0 AN13
GPP_B1/CORE_VID1
Vinafix.com
+1.0V_CLK5_F24NS CC65 1 2 1U_0201_6.3V6M AF20
Follow 543016_SKL_U_Y_PDG_1_0 SE00000UC00 AF21 VCCSRAM_1P0
@ Close to AF20 T19 VCCSRAM_1P0
+3VALW +3V_1.8V_HDA T20 VCCSRAM_1P0
LC2 VCCSRAM_1P0
22U_0603_6.3V6M
AJ21
M
22U_0603_6.3V6
MURATA BLM15EG221SN1D CC67 1 2 1U_0201_6.3V6M

1 2 SE00000UC00 VCCPRIM_3P3_AJ21
1 1 AK20
CC64
SM01000BV00 RF@
CC63
0.1U_0201_10V K X5R
@ Close to AJ21 VCCPRIM_1P0_AK20
R_0402
@ @ N18
1 CC68 1 2 1U_0201_6.3V6M VCCAPLLEBB_1P0
2 2
CC66
SE00000UC00 15 OF 20
Close to N18
RF@
SKL-U_BGA1356
2 @
+1.0V_CLK4_F100OC
22U_0603_6.3V6M
M
22U_0603_6.3V6
1 1
CC70
CC69
@ @
2 2
B B
+1.0V_CLK6_24TBT RTC Battery

+3VL_RTC +RTCBATT
+1.0VALW +3VALW +1.8VALW +3VALW W=20mils

22U_0603_6.3V6M
M
22U_0603_6.3V6
1U_0201_6.3V6M
1U_0201_6.3V6M
SE00000UC00
SE00000UC00
1 1 RC90 1 2 0_0402_5%
1
CC85
22U_0603_6.3V6M
22U_0603_6.3V6M
M
22U_0603_6.3V6
CC86
CC83 @
CC84 @
M
22U_0603_6.3V6
M
22U_0603_6.3V6
M
22U_0603_6.3V6
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1 1 1 1 1 1
SE00000UC00
SE00000UC00
SE00000UC00
CC74
SE00000UC00
CC75
CC82
CC73
M
1U_0201_6.3V6
CC72
CC76
0.1U_0201_10V K X5R
CC71
@ @ 1
2
1
1
1
1U_0201_6.3V6M
CC78 @
2 2
CC80 @
CC77 @
21
SE00000UC00
CC81
CC79
@ @ @ @ @ @
2 2 2 2 2 2
2
2
2
2
Safty suggestion remove EE side, Keep PWR side

Close to AG15 Close to Y16 Close to T16 Close to AK17
A A
2018/03/09
Compal Secret Data
2019/03/09 Tiitl e
SKL-U(9/12)Power
Custtom
LA-G202P 1..0

5 4 3 2 1
5 4 3 2 1
D D
+VCCGT +VCCGT
UC1M SKL-U
Rev_1.0
+VCCGT_VCCCORE CPU POWER 2 OF 4
N70
A48 VCCGT N71
A53 VCCGT VCCGT R63
+VCCCORE +VCCCORE A58 VCCGT VCCGT R64
A62 VCCGT VCCGT R65
UC1L SKL-U A66 VCCGT VCCGT R66
Rev_1.0 AA63 VCCGT VCCGT R67
CPU POWER 1 OF 4 VCCGT VCCGT
AA64 R68
A30 G32 AA66 VCCGT VCCGT R69
A34 VCC_A30 VCC_G32 G33 AA67 VCCGT VCCGT R70
A39 VCC_A34 VCC_G33 G35 AA69 VCCGT VCCGT R71
A44 VCC_A39 VCC_G35 G37 AA70 VCCGT VCCGT T62
AK33 VCC_A44 VCC_G37 G38 AA71 VCCGT VCCGT U65
AK35 VCC_AK33 VCC_G38 G40 AC64 VCCGT VCCGT U68
AK37 VCC_AK35 VCC_G40 G42 AC65 VCCGT VCCGT U71
AK38 VCC_AK37 VCC_G42 J30 AC66 VCCGT VCCGT W 63
AK40 VCC_AK38 VCC_J30 J33 AC67 VCCGT VCCGT W 64
AL33 VCC_AK40 VCC_J33 J37 AC68 VCCGT VCCGT W 65
AL37 VCC_AL33 VCC_J37 J40 AC69 VCCGT VCCGT W 66
AL40 VCC_AL37 VCC_J40 K33 AC70 VCCGT VCCGT W 67
AM32 VCC_AL40 VCC_K33 K35 AC71 VCCGT VCCGT W 68
AM33 VCC_AM32 VCC_K35 K37 J43 VCCGT VCCGT W 69
C AM35 VCC_AM33 VCC_K37 K38 J45 VCCGT VCCGT W 70 C
AM37 VCC_AM35 VCC_K38 K40 J46 VCCGT VCCGT W 71
AM38 VCC_AM37 VCC_K40 K42 J48 VCCGT VCCGT Y62 +VCCGT_VCCCORE
G30 VCC_AM38 VCC_K42 K43 Trace Length Match < 25 mils J50 VCCGT VCCGT
VCC_G30 VCC_K43 J52 VCCGT
Vinafix.com
K32 E32 J53 VCCGT AK42
RSVD VCC_SENSE E33 VCCCORE_SENSE <48> VCCGT VCCGTX_AK42
J55 AK43
VSS_SENSE VSSCORE_SENSE <48> VCCGT VCCGTX_AK43
AK32 J56 AK45
RSVD B63 SOC_SVID_ALERT# J58 VCCGT VCCGTX_AK45 AK46 +VCCGT
AB62 VIDALERT# A63 VR_SVID_CLK J60 VCCGT VCCGTX_AK46 AK48
P62 VCCOPC_AB62 VIDSCK D64 VR_SVID_DATA VR_SVID_CLK <48> K48 VCCGT VCCGTX_AK48 AK50
V62 VCCOPC_P62 VIDSOUT K50 VCCGT VCCGTX_AK50 AK52 R417 1 U22@ 2 0_0402_5%
VCCOPC_V62 G20 ALERT signal must be routed between CLK and DATA signals R416 1 U22@ 2 0_0603_5% +VCCG T_K52 K52 VCCGT VCCGTX_AK52 AK53
H63 VCCSTG_G20 K53 VCCGT VCCGTX_AK53 AK55
VCC_OPC_1P8_H63 +1.0VS_VCCIO K55 VCCGT VCCGTX_AK55 AK56
G61 K56 VCCGT VCCGTX_AK56 AK58
VCC_OPC_1P8_G61 K58 VCCGT VCCGTX_AK58 AK60
VCCOPC_SENSE AC63 K60 VCCGT VCCGTX_AK60 AK70
T157 TP@ VSSOPC_SENSE AE63 VCCOPC_SENSE VCCGT VCCGTX_AK70
L62 AL43
T158 TP@ VSSOPC_SENSE VCCGT VCCGTX_AL43
L63 AL46
AE62 L64 VCCGT VCCGTX_AL46 AL50
AG62 VCCEOPIO L65 VCCGT VCCGTX_AL50 AL53
VCCEOPIO L66 VCCGT VCCGTX_AL53 AL56
AL63 L67 VCCGT VCCGTX_AL56 AL60
AJ62 VCCEOPIO_SENSE L68 VCCGT VCCGTX_AL60 AM48
VSSEOPIO_SENSE 12 OF 20 L69 VCCGT VCCGTX_AM48 AM50
L70 VCCGT VCCGTX_AM50 AM52
SKL-U_BGA1356 L71 VCCGT VCCGTX_AM52 AM53
@ M62 VCCGT VCCGTX_AM53 AM56
N63 VCCGT VCCGTX_AM56 AM58
N64 VCCGT VCCGTX_AM58 AU58
N66 VCCGT VCCGTX_AU58 AU63
N67 VCCGT VCCGTX_AU63 BB57
N69 VCCGT VCCGTX_BB57 BB66
VCCGT VCCGTX_BB66
B VCCGT_SENSE J70 AK62 VCCGTX_SENSE B
<48> VCCGT_SENSE VSSGT_SENSE VCCGT_SENSE VCCGTX_SENSE AL61 VSSGTX_SENSE T161 TP@
J69 T162 TP@
<48> VSSGT_SENSE VSSGT_SENSE 13 OF 20VSSGTX_SENSE
Trace Length Match < 25 mils SKL-U_BGA1356

@
SVID ALERT
+1.0V_VCCST
Place the PU
resistors close to CPU
1
RC94
56_0402_5%
2
SOC_SVID_ALERT# 1 2
VR_ALERT# <48>
(To VR)
RC95 220_0402_5%
+1.0V_VCCST
SVID DATA Place the PU

resistors close to CPU
1
RC96
100_0402_1%
A A
2
VR_SVID_DATA
VR_SVID_DATA <48> (To VR)
2018/03/09
Compal Secret Data
2019/03/09 Tiitl e
SKL-U(10/12)Power,SVID
TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D Siiize Documentt Number Rev
Custttom
LA-G202P 1..0

5 4 3 2 1
5 4 3 2 1
D D
UC1Q SKL-U
UC1P SKL-U Rev_1.0 UC1R SKL-U
Rev_1.0 GND 2 OF 3 Rev_1.0
GND 1 OF 3 GND 3 OF 3
AT63 BA49 F8 L18
A5 AL65 AT68 VSS VSS BA53 G10 VSS VSS L2
A67 VSS VSS AL66 AT71 VSS VSS BA57 G22 VSS VSS L20
A70 VSS VSS AM13 AU10 VSS VSS BA6 G43 VSS VSS L4
AA2 VSS VSS AM21 AU15 VSS VSS BA62 G45 VSS VSS L8
AA4 VSS VSS AM25 AU20 VSS VSS BA66 G48 VSS VSS N10
AA65 VSS VSS AM27 AU32 VSS VSS BA71 G5 VSS VSS N13
AA68 VSS VSS AM43 AU38 VSS VSS BB18 G52 VSS VSS N19
AB15 VSS VSS AM45 AV1 VSS VSS BB26 G55 VSS VSS N21
AB8 VSS VSS AM61 AV71 VSS VSS BB43 G63 VSS VSS P17
AD13 VSS VSS AM68 AW 10 VSS VSS BB55 G66 VSS VSS P19
AD16 VSS VSS AM71 AW 12 VSS VSS BB6 H15 VSS VSS P20
AD19 VSS VSS AM8 AW 14 VSS VSS BB60 H18 VSS VSS P21
AD20 VSS VSS AN20 AW 16 VSS VSS BB64 H71 VSS VSS R13
AD21 VSS VSS AN23 AW 18 VSS VSS BB67 J11 VSS VSS R6
AD62 VSS VSS AN28 AW 21 VSS VSS BB70 J13 VSS VSS T15
AD8 VSS VSS AN30 AW 23 VSS VSS C1 J25 VSS VSS T17
AE64 VSS VSS AN32 AW 26 VSS VSS C25 J28 VSS VSS T18
AE65 VSS VSS AN33 AW 28 VSS VSS C5 J32 VSS VSS T2
AE66 VSS VSS AN35 AW 30 VSS VSS D10 J35 VSS VSS T21
AE67 VSS VSS AN37 AW 32 VSS VSS D11 J38 VSS VSS T4
C AE68 VSS VSS AN38 AW 34 VSS VSS D14 J42 VSS VSS U10 C
AE69 VSS VSS AN40 AW 36 VSS VSS D18 J8 VSS VSS U63
AF1 VSS VSS AN42 AW 38 VSS VSS D22 K16 VSS VSS U64
VSS
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AF17 VSS VSS AP10 AW 45 VSS D30 K61 VSS VSS U69
AF2 VSS VSS AP18 AW 47 VSS VSS D34 K63 VSS VSS U70
AF4 VSS VSS AP20 AW 49 VSS VSS D39 K64 VSS VSS V16
AF63 VSS VSS AP23 AW 51 VSS VSS D44 K65 VSS VSS V17
AG16 VSS VSS AP28 AW 53 VSS VSS D45 K66 VSS VSS V18
AG17 VSS VSS AP32 AW 55 VSS VSS D47 K67 VSS VSS W 13
AG18 VSS VSS AP35 AW 57 VSS VSS D48 K68 VSS VSS W6
AG19 VSS VSS AP38 AW 6 VSS VSS D53 K70 VSS VSS W9
AG20 VSS VSS AP42 AW 60 VSS VSS D58 K71 VSS VSS Y17
AG21 VSS VSS AP58 AW 62 VSS VSS D6 L11 VSS VSS Y19
AG71 VSS VSS AP63 AW 64 VSS VSS D62 L16 VSS VSS Y20
AH13 VSS VSS AP68 AW 66 VSS VSS D66 L17 VSS VSS Y21
AH6 VSS VSS AP70 AW 8 VSS VSS D69 VSS VSS
AH63 VSS VSS AR11 AY66 VSS VSS E11
AH64 VSS VSS AR15 B10 VSS VSS E15 18 OF 20
AH67 VSS VSS AR16 B14 VSS VSS E18
AJ15 VSS VSS AR20 B18 VSS VSS E21 SKL-U_BGA1356
AJ18 VSS VSS AR23 B22 VSS VSS E46 @
AJ20 VSS VSS AR28 B30 VSS VSS E50
AJ4 VSS VSS AR35 B34 VSS VSS E53
AK11 VSS VSS AR42 B39 VSS VSS E56
AK22 VSS VSS AR48 B58 VSS VSS F1
AK69 VSS VSS AR53 BA1 VSS VSS F23
AK8 VSS VSS AR55 BA10 VSS VSS F27
B AL2 VSS VSS AR58 BA14 VSS VSS F28 B
AL28 VSS VSS AR63 BA18 VSS VSS F32
AL32 VSS VSS AR8 BA2 VSS VSS F33
AL35 VSS VSS AT2 BA23 VSS VSS F35
AL48 VSS VSS AT35 F68 VSS VSS F40
AL55 VSS VSS AT42 VSS VSS BA41
AL58 VSS VSS AT56 VSS
AL64 VSS VSS AT58
VSS VSS
17 OF 20
16 OF 20
SKL-U_BGA1356
SKL-U_BGA1356 @
@
A A

Issued Date 2018/03/09 Deciiiphered Date 2019/03/09 Tiiitllle
SKL-U(11/12)GND
Custttom
LA-G202P 1..0

5 4 3 2 1
5 4 3 2 1
RC106 U42_EMI@ 33_0201_5%

SOC_XTAL24_IN_U42 1 2 XTAL24_IN_U42
SOC_XTAL24_OUT_U42 1 2 XTAL24_OUT_U42
D
RC107 U42_EMI@ 33_0201_5% U42@ D
RC40 1 2 1M_0402_5%
U42@
YC3
24MHZ_18PF_XRCGB24M000F2P51R0
UC1T SKL-U SJ10000UJ00
UC1S SKL-U Rev_1.0
Rev_1.0 SPARE 1 3
RESERVED SIGNALS-1 1 3
+1.8VALW AW 69 F6 NC NC
E68 BB68 AW 68 RSVD_AW 69 RSVD_F6 E3 SOC_XTAL24_IN_U42
CFG[0] RSVD_TP_BB68 BB69 AU56 RSVD_AW 68 RSVD_E3 2 4
27P_0402_50V8J
B67 C11
27P_0402_50V8J
D65 CFG[1] RSVD_TP_BB69 AW 48 RSVD_AU56 RSVD_C11 B11
CFG[2] SOC_XTAL24_OUT_U42 RSVD_AW 48 RSVD_B11 2 2
D67 C7
CC52
CC126
AK13 A11
E70 CFG[3] RSVD_TP_AK13 AK12 U12 RSVD_C7 RSVD_A11
CFG4 RC98 1 @ 2 0_0402_5% D12 U42@ U42@
C68 CFG[4] RSVD_TP_AK12 U11 RSVD_U12 RSVD_D12 C12
RC1021 @ 2 0_0402_5%
D68 CFG[5] H11 RSVD_U11 RSVD_C12 F52 1 1
1U_0201_6.3V6M
BB2
C67 CFG[6] RSVD_BB2 BA3 RSVD_H11 RSVD_F52
SE00000UC00
F71 CFG[7] RSVD_BA3
CC98 @
20 OF 20
G69 CFG[8]
CFG[9]
21
F70 AU5 SKL-U_BGA1356
G68 CFG[10] TP5 AT5 @
H70 CFG[11] TP6
G71 CFG[12]
H69 CFG[13] D5
G70 CFG[14] RSVD_D5 D4
CFG[15] RSVD_D4 B2
E63 RSVD_B2 C2
F63 CFG[16] RSVD_C2
CFG[17] B3
E66 RSVD_B3 A3
F66 CFG[18] RSVD_A3
C CFG[19] AW 1 C
CFG_RCOMP E60 RSVD_AW 1
CFG_RCOMP E1
E8 RSVD_E1 E2
ITP_PMODE RSVD_E2
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AY2 BA4
AY1 RSVD_AY2 RSVD_BA4 BB4
RSVD_AY1 RSVD_BB4
D1 A4
D3 RSVD_D1 RSVD_A4 C4
RSVD_D3 RSVD_C4
K46 BB5
K45 RSVD_K46 TP4
RSVD_K45 A69
AL25 RSVD_A69 B69
AL27 RSVD_AL25 RSVD_B69
RSVD_AL27 AY3 RC97 1 @ 2 0_0402_5%
C71 RSVD_AY3
B70 RSVD_C71 D71
RSVD_B70 RSVD_D71 C70
F60 RSVD_C70
RSVD_F60 C54
A52 RSVD_C54 D54
RSVD_A52 RSVD_D54
BA70 AY4
BA68 RSVD_TP_BA70 TP1 BB3
RSVD_TP_BA68 TP2
J71 AY71
J68 RSVD_J71 VSS_AY71 AR56
RSVD_J68 ZVM#
F65 AW 71
G65 VSS_F65 RSVD_TP AW 70 +1.0V_VCCST
VSS_G65 RSVD_TP
F61 AP56 PM_MSM# T185 TP@
E61 RSVD_F61 MSM# C64 SKL_CNL#
RSVD_E61 PROC_SELECT# 1 2
B RC99 @ 100K_0402_5% B
19 OF 20
SKL-U_BGA1356
@ Follow 544669_SKL_U_DDR3L_RVP7_schematic_rev1.0
Stuff 100k(RC99) for CannonLake-U
Un-stuff 100k(RC99) for SkyLake-U
1 2 CFG_RCOMP
RC100 49.9_0402_1%
1 2 CFG4
RC101 1K_0402_5%
Display Port Presence Strap

A A
1 : Disabled;
No Physical Display Port attached to Embedded Display Port
CFG4
0 : Enabled;
An external Display Port device is connected to the Embedded Display Port

Issued Date 2018/03/09 Deciiiphered Date 2019/03/09 Tiiitllle
SKL-U(12/12)CFG,RSVD
TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D Siiize Document Number Rev
Custttom
LA-G202P 1..0
Date: Friiiday,,, March 09,,,2018 Sheet 17 o ff 55

5 4 3 2 1
5 4 3 2 1
Interleaved Memory
+DDR_VREF_CA +DDR_VREF_CA +DDR_VREF_CA
+DDR_VREF_CA
U4 U2 U3
U1
DDR_A_D13 DDR_A_D29 DDR_A_D43
M1 G2 M1 G2 M1 G2
VREF CA DQ L0 DDR_A_D12 VREF CA DQ L0 DDR_A_D25 VREF CA DQ L0 DDR_A_D40 DDR_A_D60
F7 F7 F7 M1 G2
DQ L1 DDR_A_D11 DQ L1 DDR_A_D27 DQ L1 DDR_A_D42 VREF CA DQ L0 DDR_A_D61
H3 H3 H3 F7
DDR_A_MA0 DQ L2 DDR_A_D8 DDR_A_MA0 DQ L2 DDR_A_D24 DDR_A_MA0 DQ L2 DDR_A_D41 DQ L1 DDR_A_D62
1 P3 H7 1 P3 H7 1 P3 H7 H3
DDR_A_MA1 A0 DQ L3 DDR_A_D10 DDR_A_MA1 A0 DQ L3 DDR_A_D30 DDR_A_MA1 A0 DQ L3 DDR_A_D47 DDR_A_MA0 DQ L2 DDR_A_D57
CD271 P7 H2 CD125 P7 H2 CD126 P7 H2 1 P3 H7
.047U_0402_16V7K DDR_A_MA2 A1 DQ L4 DDR_A_D9 .047U_0402_16V7K DDR_A_MA2 A1 DQ L4 DDR_A_D28 .047U_0402_16V7K DDR_A_MA2 A1 DQ L4 DDR_A_D45 DDR_A_MA1 A0 DQ L3 DDR_A_D58
R3 H8 R3 H8 R3 H8 CD127 P7 H2
DDR_A_MA3 A2 DQ L5 DDR_A_D14 DDR_A_MA3 A2 DQ L5 DDR_A_D31 DDR_A_MA3 A2 DQ L5 DDR_A_D46 .047U_0402_16V7K DDR_A_MA2 A1 DQ L4 DDR_A_D56
SE076473K80 N7 J3 SE076473K80 N7 J3 SE076473K80 N7 J3 R3 H8
2 DDR_A_MA4 A3 DQ L6 DDR_A_D15 2 DDR_A_MA4 A3 DQ L6 DDR_A_D26 2 DDR_A_MA4 A3 DQ L6 DDR_A_D44 DDR_A_MA3 A2 DQ L5 DDR_A_D59
N3 J7 N3 J7 N3 J7 SE076473K80 N7 J3
DDR_A_MA5 A4 DQ L7 DDR_A_MA5 A4 DQ L7 DDR_A_MA5 A4 DQ L7 2 DDR_A_MA4 A3 DQ L6 DDR_A_D63
P8 P8 P8 @ N3 J7
DDR_A_MA6 A5 DDR_A_MA6 A5 DDR_A_MA6 A5 DDR_A_MA5 A4 DQ L7
D
P2 P2 P2 P8 D
DDR_A_MA7 A6 DDR_A_D6 DDR_A_MA7 A6 DDR_A_D22 DDR_A_MA7 A6 DDR_A_D38 DDR_A_MA6 A5
R8 A3 R8 A3 R8 A3 P2
DDR_A_MA8 A7 DQ U0 DDR_A_D1 DDR_A_MA8 A7 DQ U0 DDR_A_D17 DDR_A_MA8 A7 DQ U0 DDR_A_D37 DDR_A_MA7 A6 DDR_A_D50
R2 B8 R2 B8 R2 B8 R8 A3
DDR_A_MA9 A8 DQ U1 DDR_A_D7 DDR_A_MA9 A8 DQ U1 DDR_A_D23 DDR_A_MA9 A8 DQ U1 DDR_A_D35 DDR_A_MA8 A7 DQ U0 DDR_A_D52
R7 C3 R7 C3 R7 C3 R2 B8
DDR_A_MA10 A9 DQ U2 DDR_A_D5 DDR_A_MA10 A9 DQ U2 DDR_A_D20 DDR_A_MA10 A9 DQ U2 DDR_A_D32 DDR_A_MA9 A8 DQ U1 DDR_A_D51
M3 C7 M3 C7 M3 C7 R7 C3
DDR_A_MA11 A10/AP DQ U3 DDR_A_D3 DDR_A_MA11 A10/AP DQ U3 DDR_A_D19 DDR_A_MA11 A10/AP DQ U3 DDR_A_D33 DDR_A_MA10 A9 DQ U2 DDR_A_D48
T2 C2 T2 C2 T2 C2 M3 C7
DDR_A_MA12 A11 DQ U4 DDR_A_D4 DDR_A_MA12 A11 DQ U4 DDR_A_D16 DDR_A_MA12 A11 DQ U4 DDR_A_D36 DDR_A_MA11 A10/AP DQ U3 DDR_A_D54
M7 C8 M7 C8 M7 C8 T2 C2
DDR_A_MA13 A12/BC DQ U5 DDR_A_D2 DDR_A_MA13 A12/BC DQ U5 DDR_A_D18 DDR_A_MA13 A12/BC DQ U5 DDR_A_D39 DDR_A_MA12 A11 DQ U4 DDR_A_D53
T8 D3 T8 D3 T8 D3 M7 C8
DDR_A_MA14 A13 DQ U6 DDR_A_D0 DDR_A_MA14 A13 DQ U6 DDR_A_D21 DDR_A_MA14 A13 DQ U6 DDR_A_D34 DDR_A_MA13 A12/BC DQ U5 DDR_A_D55
L2 D7 L2 D7 L2 D7 T8 D3
A14/W E DQ U7 A14/W E DQ U7 A14/W E DQ U7 DDR_A_MA14 A13 DQ U6 DDR_A_D49
L2 D7
DDR_A_BA0 DDR_A_BA0 DDR_A_BA0 A14/W E DQ U7
N2 N2 N2
<7,18,20> DDR_A_BA0 DDR_A_BA1 BA0 <7,18,20> DDR_A_BA0 DDR_A_BA1 BA0 <7,18,20> DDR_A_BA0 DDR_A_BA1 BA0 DDR_A_BA0
N8 B3 N8 B3 N8 B3 N2
<7,18,20> DDR_A_BA1 BA1 VDD +1.2V <7,18,20> DDR_A_BA1 BA1 VDD +1.2V <7,18,20> DDR_A_BA1 BA1 VDD +1.2V <7,18,20> DDR_A_BA0 DDR_A_BA1 BA0
B9 B9 B9 N8 B3
VDD VDD VDD <7,18,20> DDR_A_BA1 BA1 VDD +1.2V
E2 D1 E2 D1 E2 D1 B9
+1.2V DMU/DBIU VDD +1.2V DMU/DBIU VDD +1.2V DMU/DBIU VDD VDD
E7 G7 E7 G7 E7 G7 E2 D1
DML/DBIL VDD DML/DBIL VDD DML/DBIL VDD +1.2V DMU/DBIU VDD
J1 J1 J1 E7 G7
VDD VDD VDD DML/DBIL VDD
J9 J9 J9 J1
VDD VDD VDD VDD
L1 L1 L1 J9
DDR_A_CLK0 VDD L9 DDR_A_CLK0 VDD DDR_A_CLK0 VDD VDD
K7 K7 L9 K7 L9 L1
<7,18> DDR_A_CLK0 DDR_A_CLK#0 CK_t VDD <7,18> DDR_A_CLK0 DDR_A_CLK#0 CK_t VDD <7,18> DDR_A_CLK0 DDR_A_CLK#0 CK_t VDD DDR_A_CLK0 VDD
K8 R1 K8 R1 K8 R1 K7 L9
<7,18> DDR_A_CLK#0 DDR_A_CKE0 CK_c VDD <7,18> DDR_A_CLK#0 DDR_A_CKE0 CK_c VDD <7,18> DDR_A_CLK#0 DDR_A_CKE0 CK_c VDD <7,18> DDR_A_CLK0 DDR_A_CLK#0 CK_t VDD
K2 T9 K2 T9 K2 T9 K8 R1
<7,18,20> DDR_A_CKE0 CKE VDD <7,18,20> DDR_A_CKE0 CKE VDD <7,18,20> DDR_A_CKE0 CKE VDD <7,18> DDR_A_CLK#0 DDR_A_CKE0 CK_c VDD
<7,18,20> DDR_A_CKE0 K2 T9
CKE VDD
A1 A1 A1
VDDQ VDDQ VDDQ
A9 A9 A9 A1
VDDQ VDDQ VDDQ VDDQ
C1 C1 C1 A9
VDDQ VDDQ VDDQ VDDQ
D9 D9 D9 C1
VDDQ VDDQ VDDQ VDDQ
F2 F2 F2 D9
VDDQ VDDQ VDDQ VDDQ
F8 F8 F8 F2
DDR_A_ODT0 VDDQ DDR_A_ODT0 VDDQ DDR_A_ODT0 VDDQ VDDQ
K3 G1 K3 G1 K3 G1 F8
<7,20> DDR_A_ODT0 DDR_A_CS#0 O DT VDDQ DDR_A_CS#0 O DT VDDQ DDR_A_CS#0 O DT VDDQ DDR_A_ODT0 VDDQ
L7 G9 L7 G9 L7 G9 K3 G1
<7,18,20> DDR_A_CS#0 DDR_A_MA16 CS VDDQ <7,18,20> DDR_A_CS#0 DDR_A_MA16 CS VDDQ <7,18,20> DDR_A_CS#0 DDR_A_MA16 CS VDDQ DDR_A_CS#0 O DT VDDQ
L8 J2 L8 J2 L8 J2 L7 G9
DDR_A_MA15 RAS VDDQ DDR_A_MA15 RAS VDDQ DDR_A_MA15 RAS VDDQ <7,18,20> DDR_A_CS#0 DDR_A_MA16 CS VDDQ
M8 J8 M8 J8 M8 J8 L8 J2
CAS VDDQ CAS VDDQ CAS VDDQ DDR_A_MA15 RAS VDDQ
M8 J8
CAS VDDQ
B2 Replace with 240 Ohm to Support DDP@ B2 Replace with 240 Ohm to Support DDP@ B2 Replace with 240 Ohm to Support DDP@
VSS VSS VSS
E1 E1 E1 B2 Replace with 240 Ohm to Support DDP@
VSS VSS VSS VSS
E9 RD200 1 @ 2 0_0402_5% E9 RD201 1 @ 2 0_0402_5% E9 RD202 1 @ 2 0_0402_5% E1
VSS VSS VSS VSS
G8 G8 G8 E9 RD203 1 @ 2 0_0402_5%
DDR_A_DQS#0 VSS DDR_A_DQS#2 VSS DDR_A_DQS#4 VSS VSS G8
A7 K1 A7 K1 A7 K1
DDR_A_DQS0 DQ SU_c VSS DDR_A_DQS2 DQ SU_c VSS DDR_A_DQS4 DQ SU_c VSS DDR_A_DQS#6 VSS K1
B7 K9 B7 K9 B7 K9 A7
DDR_A_DQS#1 DQ SU_t VSS DDR_A_BG1_R DDR_A_DQS#3 DQ SU_t VSS DDR_A_BG1_R DDR_A_DQS#5 DQ SU_t VSS DDR_A_BG1_R DDR_A_DQS6 DQ SU_c VSS
F3 M9 F3 M9 F3 M9 B7 K9
DDR_A_DQS1 DQ SL_c VSS DDR_A_BG1_R <20> DDR_A_DQS3 DQ SL_c VSS DDR_A_DQS5 DQ SL_c VSS DDR_A_DQS#7 DQ SU_t VSS DDR_A_BG1_R
G3 N1 G3 N1 G3 N1 F3 M9
DQSL_t VSS DQSL_t VSS DQSL_t VSS DDR_A_DQS7 DQ SL_c VSS
T1 T1 T1 G3 N1
VSS VSS VSS DQSL_t VSS
MEMRST# P1 MEMRST# P1 MEMRST# P1 T1
RESET RESET RESET VSS
MEMRST# P1
1 2 RU160 F9 RESET
C 1 2 RU161 F9 1 2 RU162 F9 C
240_0402_1% ZQ 240_0402_1% ZQ 240_0402_1% ZQ 1 2 RU163 F9
240_0402_1% ZQ
M_A_ACT# M_A_ACT# M_A_ACT#
L3 A2 L3 A2 L3 A2
<7,20> M_A_ACT# DDR_A_BG0 ACT VSSQ DDR_A_BG0 ACT VSSQ DDR_A_BG0 ACT VSSQ M_A_ACT#
<7,20> DDR_A_BG0 M2 A8 M2 A8 M2 A8 L3 A2
BG0 VSSQ BG0 VSSQ BG0 VSSQ DDR_A_BG0 ACT VSSQ
N9 C9 N9 C9 N9 C9 M2 A8
DDR_A_ALERT# TEN VSSQ DDR_A_ALERT# TEN VSSQ DDR_A_ALERT# TEN VSSQ BG0 VSSQ
P9 D2 P9 D2 P9 D2 N9 C9
<7> DDR_A_ALERT# DDR_A_PARITY ALERT VSSQ DDR_A_PARITY ALERT VSSQ DDR_A_PARITY ALERT VSSQ DDR_A_ALERT# TEN VSSQ
T3 D8 T3 D8 T3 D8 P9 D2
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<7,20> DDR_A_PARITY PAR VSSQ PAR VSSQ PAR VSSQ DDR_A_PARITY ALERT VSSQ
E3 E3 E3 T3 D8
VSSQ VSSQ VSSQ PAR VSSQ
T7 E8 T7 E8 T7 E8 E3
NC VSSQ NC VSSQ NC VSSQ VSSQ
B1 F1 B1 F1 B1 F1 T7 E8
+2.5V VPP VSSQ +2.5V VPP VSSQ +2.5V VPP VSSQ NC VSSQ
R9 H1 R9 H1 R9 H1 B1 F1
VP P VSSQ VPP VSSQ VPP VSSQ +2.5V VPP VSSQ
H9 H9 H9 R9 H1
96-B AL L VSSQ 96-B AL L VSSQ 96-B AL L VSSQ VPP VSSQ
H9
96-B AL L VSSQ
SDRAM DDR4 SDRAM DDR4 SDRAM DDR4
K4AAG165WB-MCRC C38 K4AAG165WB-MCRC C38 K4AAG165WB-MCRC C38 SDRAM DDR4
@ @ @ K4AAG165WB-MCRC C38
@
Co-lay for SDP / DDP Memory DIE

<7,20> DDR_A_MA[0..16]
<7> DDR_A_DQS#[0..7]
<7> DDR_A_DQS[0..7]
On Board RAM - DataMapping

<7> DDR_A_D[0..63]
B B
DDR_A_BG1_R
DDP@ U4 DQ U2 DQ U3 DQ U1 DQ
RD204 1 2 0_0402_5%
DDR_A_BG1 <7>
DQL0 D13 DQL0 D29 DQL0 D43 DQL0 D60
For SDP@
RD205 1 @ 2 0_0402_5% DQL2 D11 DQL2 D27 DQL2 D42 DQL2 D62
CLOCKTERMINATION DQL3 D8 DQL3 D24 DQL3 D41 DQL3 D57
+0.6VS
DDR_A_CLK0
DDR_A_CLK#0
RU166 1 2 36_0402_1% DQU0 D6 DQU0 D22 DQU0 D38 DQU0 D50
RU167 1 2 36_0402_1%
DDR_A_CLK0
DQU1 D1 DQU1 D17 DQU1 D37 DQU1 D52
1 DQU2 D7 DQU2 D23 DQU2 D35 DQU2 D51
+1.2V
@
CD273 DQU3 D5 DQU3 D20 DQU3 D32 DQU3 D48
3300P_0402_50V7K
DDR_A_CLK#0 2 DQU4 D3 DQU4 D19 DQU4 D33 DQU4 D54
+1.2V
2
DDR_A_ALERT# RD41 2
1 49.9_0402_1% RD195
1.8K_0402_1% DQU7 D0 DQU7 D21 DQU7 D34 DQU7 D49
RD11 +DDR_VREF_CA
2.7_0402_1%
1
2 1
<7> +0.6V_A_VREFCA
1
DDR_DRAMRST# RD46 1 @ 2 0_0402_5% MEMRST#
<7,19> DDR_DRAMRST#
CD24
0.022U_0402_16V7K
2
A 1 A
1
CD36
100P_0201_25V8J RD13 RD210
2 @ 24.9_0402_1% 1.8K_0402_1%
2
Securiiittty Clllassiiifffiiicatttiiion Compalll Secret Data

IIIssued Dattte 2018/03/09//// Decipii hered Dattte 2019///03///09 Tiitttlle
THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIISTHE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC...AND CONTAIIINS CONFIIIDENTIIIAL AND TRADE
DDR4 ON BOARD CHIPS
Siiize Documenttt Numberrr Re v
SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D DEPARTMENT EXCEPT Custttom LA---G201P 1..0
AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,,IIINC...NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIITCONTAIIINS
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IIINC... Dattte::: Frrriiday,,, Marrrch 09,,,2018 Sheettt 18 o ff55
5 4 3 2 1
A B C D E
<7> DDR_B_DQS#[0..7]
Reverse Type
<7> DDR_B_D[0..63]
<7> DDR_B_DQS[0..7] 2-3A to 1 DIMMs/channel

+1.2V +1.2V
<7> DDR_B_MA[0..16]
DDR_B_BA0
JDIMM1
<7> DDR_B_BA0 DDR_B_BA1 +1.2V
1 2
<7> DDR_B_BA1 DDR_B_BG0 DDR_B_D14 VSS VSS DDR_B_D11
3 4
<7> DDR_B_BG0 DDR_B_BG1 DQ 5 DQ 4
<7> DDR_B_BG1 5 6
DDR_B_D15 VSS VSS DDR_B_D10
7 8
DQ 1 DQ 0
9 10
DDR_B_DQS#1 VSS VSS +DIMM_VREF_DQ
11 12
DDR_B_DQS1
13 DQS0 _ C DM0*/DBI0* 14
DDR_B_CLK0 DQ S0_T VSS DDR_B_D8
2
15 16
<7> DDR_B_CLK0 DDR_B_CLK#0 DDR_B_D13 VSS DQ 6 RD194
17 18
<7> DDR_B_CLK#0 DDR_B_CLK1 DQ7 VSS DDR_B_D9
1 <7> DDR_B_CLK1 19 20 1K_0402_1% 1
DDR_B_CLK#1 DDR_B_D12 VSS DQ 2 RD10
21 22
<7> DDR_B_CLK#1
23
DQ3 VSS
24 DDR_B_D4 20mil 2_0402_1%
VSS DQ 12
1
DDR_B_D1 25 26 2 1
DDR_B_CKE0 DQ1 3 VSS DDR_B_D0 <7> +0.6V_B_VREFDQ
27 28
<7> DDR_B_CKE0 DDR_B_CKE1 DDR_B_D5 VSS DQ 8
29 30
<7> DDR_B_CKE1 DDR_B_CS#0 DQ9 VSS DDR_B_DQS#0
<7> DDR_B_CS#0 31 32 1
DDR_B_CS#1 33 VSS DQ S1_C DDR_B_DQS0
<7> DDR_B_CS#1 34
35 DM1*/DBI1* DQS1 _ T 36 CD21
DDR_B_D3 37 VSS VSS 38 DDR_B_D6 0.022U_0402_16V7K
SOC_SMBDATA 39 DQ1 5 DQ 14 2
40
<8> SOC_SMBDATA SOC_SMBCLK DDR_B_D2 41 VSS VSS DDR_B_D7
42
<8> SOC_SMBCLK 43 DQ1 0 DQ 11
2
1
44
DDR_B_D21 45 VSS VSS DDR_B_D20 RD12 RD199
46
DDR_B_ODT0 47 DQ2 1 DQ 20
48 24.9_0402_1% 1K_0402_1%
<7> DDR_B_ODT0 DDR_B_ODT1 DDR_B_D17 49 VSS VSS DDR_B_D16
50
<7> DDR_B_ODT1 51 DQ1 7 DQ 16
52
DDR_B_DQS#2 53 VSS VSS
1
2
54
DDR_B_DQS2 55 DQS2 _ C DM2*/DBI2* 56
DQS2 _ T VSS DDR_B_D19
Note: DDR_B_D23
57
59 VSS DQ 22
58
Layout Note: Check voltage tolerance of DQ2 3 VSS
60
DDR_B_D18
61
Place near JDIMM1 VREF_DQ at the DIMM socket DDR_B_D22 63 VSS DQ 18
62
64
65 DQ1 9 VSS
66 DDR_B_D28
DDR_B_D29 67 VSS DQ 28
68
69 DQ2 9 VSS DDR_B_D24
70
DDR_B_D25 71 VSS DQ 24
72
73 DQ2 5 VSS
74
DDR_B_DQS#3
+1.2V 75 VSS DQ S3_C DDR_B_DQS3
76
77 DM3*/DBI3* DQS3 _ T 78
79 80
DQ3 0 DQ 31
81 82
83 84
DQ2 6 DQ 27
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
85 86
SE00000UC00
SE00000UC00
SE00000UC00
SE00000UC00
SE00000UC00
SE00000UC00
SE00000UC00
SE00000UC00
VSS VSS 88
1
1
1
1
1
87
89 CB5_NC CB4 _ NC 90
CD17
CD4
CD18
CD7
CD8
CD5
CD9
CD6
VSS VSS 92
91
CB1_NC
2
2
2
CB0 _ NC
2
@ 93 94
1 2 95 VSS VSS 96
RD1615 240_20402_1% 97 DQS8 _ C DM8*/DBI8* 98
RD166 @ 240_0402_1% 99 DQS8 _ T VSS 100
VSS CB6 _ NC 102
101
CB2_NC VSS
4 as near side of the DIMM close to VDD pins 103
VSS CB7 _ NC 106
104
105
CB3_NC VSS 108 DDR_DRAMRST#_R
107
2 DDR_B_CKE0 VSS RESET* 110 DDR_B_CKE1 2
+1.2V 109
CKE0 CKE1
111 112 1
DDR_B_BG1 VDD1 VDD2 114 CD34
113
DDR_B_BG0 BG1 ACT* 116 M_B_ACT# <7>
0.1U_0201_10V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
115
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
BG0 ALERT* 118 DDR_B_ALERT# <7>

117 @
DDR_B_MA12 VDD3 VDD4 DDR_B_MA11 2
119 120
DDR_B_MA9 A12 A11 DDR_B_MA7
1 1 1 1 1 1 1 1 121 122
A9 A7 +1.2V
CD13
CD12
CD15
CD11
CD14
CD19 @
123 124
CD10 @
CD20
Vinafix.com
DDR_B_MA8 VDD5 VDD6 DDR_B_MA5
125 126
DDR_B_MA6 A8 A5 A4 DDR_B_MA4
127 128
2 2 2 2 2 2 2 2 A6 VDD8
129 130
DDR_B_MA3 VDD7 A2 DDR_B_MA2
131 132
DDR_B_MA1 A3 EVENT* 134
133
A1 VDD10 136
135
DDR_B_CLK0 VDD9 CK1_T DDR_B_CLK1
1
137 138
DDR_B_CLK#0 CK0_T CK1_C DDR_B_CLK#1 RD43
139 140
CK0_C VDD12
141 142 470_0402_1%
VDD11 A0 DDR_B_MA0
143 144
<7> DDR_B_PARITY PARITY
2
DDR_DRAMRST#_R RD45 1 @ 2 0_0402_5%
DDR_B_BA1 DDR_B_MA10 DDR_DRAMRST# <7,18>
145 146
BA1 A10_AP
147 148
DDR_B_CS#0 149 VDD13 VDD14 DDR_B_BA0
150
DDR_B_MA14 151 S0* BA0 DDR_B_MA16
152
153 A14_W E* A16_RAS* 154 +DIMM_VREF_DQ
DDR_B_ODT0 VDD15 VDD16 DDR_B_MA15
155 156
DDR_B_CS#1 157 ODT0 A15_CAS* DDR_B_MA13
158
159 S1* A13
160
DDR_B_ODT1 VDD17 VDD18 162
161
+3VS ODT1 S2*/C0 164
163
VDD19 VREF CA DDR_B_SA2
Place these caps on the VTT plane close to DIMM 165
S3*/C1 SA2
166
167 168
169 170
DQ3 7 DQ 36
+0.6VS 171 172
173 174
+3VS_DIMM DQ3 3 DQ 32
175 176
DDR_B_DQS#4 VSS VSS
177 178
DDR_B_DQS4
179 DQS4 _ C DM4*/DBI4* 180 JDIMM1 ADDRESS PLACE CLOSE TO DIMM
( )
DQ S4_T VSS DDR_B_D39
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
SE00000UC00
SE00000UC00
SE00000UC00
10U_0603_6.3V6M
181 182
10U_0603_6.3V6M
SE00000UC00
1 1 1 1 DDR_B_D38 VSS DQ 39
1
CD28
CD23 @
183 184
CD22
0.1U_0201_10V6K DQ3 8 VSS DDR_B_D35

CD30
CD31
CD32 @
CD33 @
C2142 185 186

DDR_B_D34 VSS DQ 35
2.2U_0402_6.3V6M 187 188
DQ3 4 VSS
2
DDR_B_D45
2
2 2 2 2 189 190
DDR_B_D44 VSS DQ 45
3 191 192 3
DQ4 4 VSS DDR_B_D41 +3VS +3VS
193 194
DDR_B_D40 VSS DQ 41
195 196
DQ4 0 VSS DDR_B_DQS#5
close to DIMM 197
VSS DQ S5_C
198
DDR_B_DQS5
199 200
DM5*/DBI5* DQS5 _ T
2
2
201 202
DDR_B_D43 VSS VSS DDR_B_D47 RD139
203 204 RD108
DQ 46 DQ 47 0_0402_5%
205 206 @ 0_0402_5%
DDR_B_D42 VSS VSS DDR_B_D46 @
207 208
DQ 42 DQ 43
209 210
VSS VSS
1
DDR_B_D52 DDR_B_D53
1
211 212
DQ 52 DQ 53
213 214
DDR_B_D49 VSS VSS DDR_B_D48 DDR_B_SA2 DDR_B_SA1 DDR_B_SA0
215 216
DQ 49 DQ 48
217 218
DDR_B_DQS#6 VSS VSS
219 220
DDR_B_DQS6 DQS6 _ C DM6*/DBI6*
221 222
DQ S6_T VSS DDR_B_D54
1
223 224
DDR_B_D55 VSS DQ 54 RD138
225 226 RD140
+2.5V DQ5 5 VSS DDR_B_D51 0_0402_5%
227 228 @ 0_0402_5%
DDR_B_D50 VSS DQ 50 @
229 230
DQ5 1 VSS DDR_B_D60
231 232
VSS DQ 60
2
DDR_B_D61
2
233 234
DQ6 1 VSS DDR_B_D57
235 236
DDR_B_D56 VSS DQ 57
237 238
DQ5 6 VSS DDR_B_DQS#7
239 240
VSS DQ S7_C DDR_B_DQS7
+2.5V 241 242 +0.6VS
243 DM7*/DBI7* DQS7 _ T 244
1 245 246
DQ6 2 DQ 63
1
@ C2140 CD29 247 248

10U_0603_6.3V6M 1U_0201_6.3V6M DDR_B_D58 VSS VSS DDR_B_D62
249 250
SE00000UC00 DQ5 8 DQ 59
251 252
VSS VSS SOC_SMBDATA
2
2 SOC_SMBCLK 253 254

+3VS_DIMM SCL SDA DDR_B_SA0
255 256
VDDSPD SA0
257 258
VPP1 VTT DDR_B_SA1
259 260
VPP2 SA1
261
G ND
262
G ND
FOX_AS0A827-H2SB-7H
LTCX0069FA0
ME@
4 4
Securiiittty Clllassiiifffiiicatttiiion Compalll Secret Data Compal Electronics, Inc.

DDR4_DIMM
SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D DEPARTMENT EXCEPT
LA-G202P
Custttom 1..0
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IIINC... Dattte::: Frrriiday,,, Marrrch 09,,,2018 Sheettt 19 offf 55
A B C D E
1 2 3 4 5
UV1A
COMMON
1/14 PCI_EXPRESS
Place near Place near BGA

+1.0VS_DGPU
AB6 PEX_WAKE# balls
1.0V
P E X _ IO V DD AA22
PLT_RST_VGA_MON# PLT_RST_VGA#
1U_0201_6.3V6M
22U_0603_6.3V6M
AB23
1U_0201_6.3V6M
M
4.7U_0402_6.3V6
10U_0603_6.3V6M
10U_0603_6.3V6M
22U_0603_6.3V6M
RV379 1 2 0_0402_5% AC7 P E X _ RST# P E X _ IO V DD
SE00000UC00
SE00000UC00
AC24
CV2 DIS@
CV199 @
CV204 @
NOGC6@ P E X _ IO V DD 1 1 1 1 1
1
CLKREQ_PCIE#0_R
CV7 @
CV202 DIS@
AD25
CV205 @
CV9 @
AC6 P E X _ CLKR EQ # P E X _ IO V DD
P E X _ IO V DD AE26
AE8 P E X _R EF CLK P E X _ IO V DD AE27
<10> CLK_PEG_VGA
2
2 2 2 2 2
PCIE CLK <10> CLK_PEG_VGA# AD8 P E X _ REF CLK#
PCIE_PRX_DTX_P1 CV11 DIS@ 1 2 0.22U_0402_6.3V6K PCIE_PRX_C_DTX_P1 AC9 P E X _TX 0
<12> PCIE_PRX_DTX_P1 PCIE_PRX_DTX_N1 PCIE_PRX_C_DTX_N1
CV12 DIS@ 1 2 0.22U_0402_6.3V6K AB9 P E X _ TX 0#
A <12> PCIE_PRX_DTX_N1 A
PCIE_PTX_C_DRX_P1 AG6 P E X _RX0
<12> PCIE_PTX_C_DRX_P1 PCIE_PTX_C_DRX_N1 AG7 P E X _ RX0# P E X _ IO V DDQ AA10
<12> PCIE_PTX_C_DRX_N1
PCIE_PRX_C_DTX_P2
P E X _ IO V DDQ AA12 Place near Place near BGA
PCIE_PRX_DTX_P2 +1.0VS_DGPU
<12> PCIE_PRX_DTX_P2 PCIE_PRX_DTX_N2
CV13 DIS@ 1 2 0.22U_0402_6.3V6K AB10 P E X _ TX 1 P E X _ IO V DDQ AA13 balls
CV14 DIS@ 1 2 0.22U_0402_6.3V6K PCIE_PRX_C_DTX_N2 AC10 P E X _TX 1 # P E X _ IO V DDQ AA16 1.0V
P E X _ IO V DDQ AA18
PCIE_PTX_C_DRX_P2
4.7U_0402_6.3V6M
AA19
1U_0201_6.3V6M
1U_0201_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
AF7 P E X _ RX1 P E X _ IO V DDQ
<12> PCIE_PTX_C_DRX_P2 PCIE_PTX_C_DRX_N2
SE00000UC00
CV3 @
SE00000UC00
AA20
CV198 @
CV203 DIS@
<12> PCIE_PTX_C_DRX_N2 AE7 P E X _RX1 # P E X _ IO V DDQ 1 1 1 1 1
AA21
CV201 @
CV200 @
CV10 @
CV8 DIS@
P E X _ IO V DDQ
PCIE_PRX_DTX_P3 PCIE_PRX_C_DTX_P3
PCIE X4 Bus <12> PCIE_PRX_DTX_P3 PCIE_PRX_DTX_N3
CV15 DIS@ 1 2 0.22U_0402_6.3V6K
PCIE_PRX_C_DTX_N3
AD11 P E X _ TX 2 P E X _ IO V DDQ AB22
21
21
CV16 DIS@ 1 2 0.22U_0402_6.3V6K AC11 P E X _TX 2 # P E X _ IO V DDQ AC23
<12> PCIE_PRX_DTX_N3 2 2 2 2 2
P E X _ IO V DDQ AD24
PCIE_PTX_C_DRX_P3 AE9 P E X _ RX2 P E X _ IO V DDQ AE25
<12> PCIE_PTX_C_DRX_P3 PCIE_PTX_C_DRX_N3 AF9 P E X _ RX2# P E X _ IO V DDQ AF26
<12> PCIE_PTX_C_DRX_N3 AF27
P E X _ IO V DDQ
PCIE_PRX_DTX_P4 CV17 DIS@ 1 2 0.22U_0402_6.3V6K PCIE_PRX_C_DTX_P4 AC12 P E X _ TX 3
<12> PCIE_PRX_DTX_P4 PCIE_PRX_DTX_N4 PCIE_PRX_C_DTX_N4
CV18 DIS@ 1 2 0.22U_0402_6.3V6K AB12 P E X _ TX 3#
PCIE_PTX_C_DRX_P4 AG9 P E X _RX3
<12> PCIE_PTX_C_DRX_P4 PCIE_PTX_C_DRX_N4
<12> PCIE_PTX_C_DRX_N4 AG10 P E X _ RX3#
Near UV1 AB13 P E X _TX 4

AC13 P E X _TX 4 #
AF10 P E X _R X4
AE10 P E X _ RX4#
AD14 NC FOR GF119

P E X _ TX 5
AC14 P E X _TX 5 # P E X _ PLL_HVDD AA8
P E X _ PLL_HVDD AA9
+3VS_DGPU_AON
NC FOR GM108
AE12 P E X _R X5
AF12 P E X _ RX5# Place near BGA
P E X _ SVDD_3V 3 AB8
AC15 P E X _ TX 6
B AB15 B
4.7U_0402_6.3V6M
0.1U_0201_10V6K
M
4.7U_0402_6.3V6
P E X _ TX 6#
CV4 DIS@
CV207 DIS@
CV5 DIS@
1 1 1
AG12 P E X _ RX6
AG13 P E X _ RX6#
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AB16 P E X _TX 7 2 2 2
AC16 P E X _TX 7 #
AF13 P E X _R X7
AE13 P E X _ RX7#
AD17 P E X _ TX 8
AC17 P E X _TX 8 #
Reset Control
+3VS AE15 P E X _R X8
AF15 P E X _ RX8#
UV12
5
MC74VHC1G08DFT2G_SC70-5 AC18 VDD_SENSE_GPU

P E X _ TX 9 V D D _ SENSE F2 VDD_SENSE_GPU <51>
1
AB18 P E X _ TX 9# To POWER
GND VCC
<10,31,33,36> PCI_RST# IN1 4 AG15 GND_SENSE_GPU

(From PCH) 2 OUT
P E X _ RX9 G N D _ S ENSE F1
PLT_RST_VGA_MON# <24> AG16 GND_SENSE_GPU <51>
<11> DGPU_HOLD_RST#
IN2 P E X _ RX9# trace width: 16mils
+3VS_DGPU_AON differential voltage sensing.
AB19 P E X _TX 10
DIS@ AC19
differential signal routing.
UV15 P E X _TX 10#
3
MC74VHC1G08DFT2G_SC70-5 AF16 P E X _ RX10

AE16 P E X _RX 10#
1
GND VCC
IN1
NC FOR GF117/GK208/GM108
4 PLT_RST_VGA# AD20 P E X _TX 1 1
2 OUT AC20 P E X _TX 1 1#
(From GPU) <24> PLT_RST_VGA_HOLD# IN2
1
AE18 P E X _ RX11
GC6@ RV378 AF18 P E X _RX11 #
3
10K_0402_5%
C DIS@ AC21 P E X _TX 1 2 C
2
AB21 P E X _TX 12 #
AG18 P E X _ RX12 AF22 PEX_PLL_CLK_OUT RV4 2 @ 1200_0402_1%

P E X _ TS TC LK_O U T
AG19 P E X _RX 12# P E X _ TS TC LK_O U T# AE22 PEX_PLL_CLK_OUT#
CLK_REQ +3VS_DGPU
AD23
AE23
P E X _TX 1 3
+1.0VS_DGPU
P E X _TX 13 #
1.0V
AF19 P E X _ PLLVDD AA14 PEX_PLLVDD_GPU RV377 1 2 0_0402_5%
P E X _RX 13
AE19 P E X _ RX13# P E X _ PLLVDD AA15
1
Place near BALL Place near BGA
1U_0201_6.3V6M
0.1U_0201_10V6K
M
4.7U_0402_6.3V6
SE00000UC00
CV6 DIS@
RV17 AF24 P E X _ TX 14 1 1
CV206 DIS@
CV208 DIS@
10K_0402_5% AE24 P E X _TX 14 #
DIS@
AE21 P E X _ RX14
2
2
AF21 P E X _RX14 #
2 2
RV16 1 @ 2 0_0402_5% AD9 GPU_TESTMODE
<25,26,51> DGPU_PWROK TE S TM O D E GPU_TESTMODE <24>
AG24 P E X _ TX 15
AG25 P E X _TX 1 5#
+3VS_DGPU_AON
1U_0201_6.3V6M
AG21 P E X _ RX15
SE00000UC00
AG22 P E X _RX 15#

1
1
CV121 @
RV68
10K_0402_5% PEX_TERMP
P E X _ TE R M P AF25
2
DIS@ QV3
1
G
2N7002K_SOT23-3
2
N16S-GT-S-A2_BGA595 RV376
CLKREQ_PCIE#0_R 3 1 VGA_CLKREQ# @ 2.49K_0402_1%
VGA_CLKREQ# <10>
S
DIS@
DIS@ (To SOC)
2
1
VGS(Max) : 2.5 V RV18

10K_0402_5%
D @ D
2
RV375 1 @ 2 0_0402_5%

NV(1/5)-PCIE
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIT CONTAIIINS 1..0
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IINC... LA-G202P
1 2 3 4 5
1 2 3 4 5
UV1G IFPA/B UV1H

COMMON
IFPC
COMMON 5/14 IFPC
4/14 IFPAB IFPC
T6 IF P C _ R S E T GF119/GK208
IF P A _TX C # AC4
IF P A _ TX C AC3 DVI/HDMI DP
AA6 IF P A B _RS E T M7 IF P C_P LLV D D I2CW _SDA IF P C_A U X # N5
NC FOR GF117/GM108
IF P A _TX D0# Y3 N7 IF P C_P LLV D D I2CW _SCL IF P C _ A U X N4
IF P A _ TX D 0 Y4
A A
NC FOR GF117/GM108
V7 IF P A B _P LLV D D TXC IF P C_L3# N3
IF P A _TX D1# AA2 TXC IFPC_L3 N2
W7
IF P A B _P LLV D D IF P A _ TX D 1 AA3
DAC_A IF P C_L2# R3
NC FOR GF117/GM108
TXD0
UV1K IFPC_L2 R2
TXD0
IF P A _TX D2# AA1 COMMON
IF P A _ TX D 2 AB1 3/14 DACA TXD1 IF P C_L1# R1
TXD1 IFPC_L1 T1
GF117/GM108 GF117 GM108/GK208
NC FOR GF117/GM108
IFPA_TXD3# AA5 W5 B7 I2CA_SCL T3
D A C A _VDD NC NC I2CA _S C L I2CA_SCL <24> TXD2 IF P C_L0#
AA4 A7 I2CA_SDA T2
IF P A _ TX D 3 NC I2CA _S D A I2CA_SDA <24> TXD2 IFPC_L0
AE2 D A C A _VR EF TSEN_VREF
IF P B _TX C # AB4 AF2 D A C A _RS ET NC D A C A _HS YNC AE3 GF117

NC
IF P B _ TX C AB5 NC D A C A _VS YN C AE4 P6 IFPC_IOVDD G P IO 1 5 C3
NC
W6 IFPA_IOVDD IF P B _TX D4# AB2 D A C A _RED AG3

NC
IF P B _ TX D 4 AB3 N16S-GT-S-A2_BGA595
Y6 IFPB_IOVDD NC D A C A _G R E EN AF4 @
IF P B _TX D5#
IF P B _ TX D 5
AD2
AD3
NC D A C A _BLUE AF3 UV1I
COMMON
IFPD
GM108 6/14 IFPD
GK208
GF117
IF P B _TX D6# AD1
IF P B _ TX D 6 AE1 N16S-GT-S-A2_BGA595 U6 GF119/GK208
IF P D _ R S E T
@
DVI/HDMI DP
IFPB_TXD7# AD5
IF P B _ TX D 7 AD4 T7 IFPD_PLLVDD I2CX_SDA IF P D_A U X # P4
I2CX_SCL IF P D _ A U X P3
NC FOR GF117/GM108
R7
IFPD_PLLVDD
NC FOR GF117/GM108
B R5 B
TXC IF P D_L3#
GF117
TXC IFPD_L3 R4
G P IO 1 4 B3
NC
IFPAB TXD0
TXD0
IFPD_L2#
IFPD_L2
T5
T4
Vinafix.com
N16S-GT-S-A2_BGA595
@ TXD1 IF P D_L1# U4
+1.0VS_DGPU IFPD TXD1 IFPD_L1 U3
1V DIS@ IF P D_L0# V4
GPU_PLLVDD TXD2
LV5 1 2 S SUPPRE_ MURATA BLM15PD300SN1D 0402 SM01000LX00 IFPD_L0 V3
TXD2
Place near balls
22U_0603_6.3V6M
0.1U_0201_10V K X5R
GF117
1 1
CV32 DIS@
CV31 DIS@
R6 IFPD_IOVDD G P IO 1 7 D4
IFPE/F
NC
UV1J
COMMON 2 2
7/14 IFPEF
GF119/GK208
N16S-GT-S-A2_BGA595
DVI-DL DVI-SL/HDMI DP @
I2CY_SDA I2CY_SDA IF P E _ A U X# J3
I2CY_SCL I2CY_SCL IF P E _ A U X J2
J7 IF P E F _P LLV D D
IF P E _L3# J1
TXC TXC
IFPE_L3 K1
TXC TXC
NC FOR GF117/GM108
K7 IF P E F _P LLV D D
IF P E _L2# K3
NC FOR GF117/GK208/GM108
TXD0 TXD0
IFPE_L2 K2
TXD0 TXD0
K6 IF P E F _RS E T IFPE_L1# M3
TXD1 TXD1
IFPE_L1 M2
TXD1 TXD1
X'TAL
C C
IF P E _L0# M1 UV1M
TXD2 TXD2
IFPE_L0 N1 COMMON
TXD2 TXD2
9/14 XTAL_PLL
IFPE NC FOR GK208 L6 P LLV D D
+1.0VS_DGPU Place near BGA Place near balls M6 S P _ P LLVDD
+3VS_DGPU_AON
RV23 @
C2 LV6 1 2 0_0603_5% VID_PLLVDD N6 VID_PLLVDD 10K_0402_1%
HPD_E G P IO 18 NC
HPD_E XTAL_OUTBUFF 1 2
1V
10U_0603_6.3V6M
22U_0603_6.3V6M
M
22U_0603_6.3V6
0.1U_0201_10V K X5R
0.1U_0201_10V K X5R
NC FOR GF117 GF119/GK208 GF117/GM108
1 1 1 1 1
CV30 DIS@
CV61 DIS@
CV35 @
CV34 DIS@
CV60 DIS@
RV21 DIS@ RV20 DIS@
H6 IFPE_IOVDD 10K_0402_1% 10K_0402_1%
2 1 XTAL_OUTBUFF 1 2
GF119/GK208 A10 X TA L S S IN X TA L O U TB U F F C10
J6 2 2 2 2 2
IFPF_IOVDD
DVI-DL DVI-SL/HDMI DP
IF P F _ A U X # H4 C11 XTALIN XTALOU T B10
I2CZ_SDA
I2CZ_SCL IF P F _ A U X H3
N16S-GT-S-A2_BGA595
@
TXC IF P F _L3# J5 90-OHM DIFF Impedance for XTALIN & XTALOUT.
2
TXC IFPF_L3 J4
NC FOR GF117/GM108
YV1 RV110 DIS@

TXD3 TXD0 IF P F _L2# K5 27MHZ_10PF_XRCGB27M000F2P18R0 1.5K_0402_1%
TXD3 TXD0 IFPF_L2 K4 SJ10000UI00
1
IF P F _L1# L4 1 3
TXD4 TXD1 1 3
IFPF TXD4 TXD1 IFPF_L1 L3
NC NC
1 1
TXD5 TXD2 IF P F _L0# M5 DIS@
IFPF_L0 M4 CV210 DIS@ 2 4 CV209 DIS@
TXD5 TXD2
2 18P_0402_50V8J 2 18P_0402_50V8J
NC FOR GK208
D D
G P IO 19 F7
HPD_F
NC FOR GF117
N16S-GT-S-A2_BGA595
@
NV(2/5)-IFP_ABCDEF_DAC_XTAL
Datte:: Friiiday,,, March 09,,,2018 Sheett 22 o f 55
1 2 3 4 5
1 2 3 4 5
UV1D UV1F
+1.35VS_VRAM COMMON COMMON
Place under GPU 12/14 FBVDDQ
B26 F B V D D Q GPU_Decoupling A2
AB17
13/14 GND
GND
GND
GND
GND
M13
M15
CAPs @ Power
C25 F B VD D Q AB20 GND GND M17
1U_0201_6.3V6M
M
4.7U_0402_6.3V6
M
4.7U_0402_6.3V6
1U_0201_6.3V6M
K
0.1U_0201_10V6
K
0.1U_0201_10V6
E23 FB V DD Q AB24 GND GND N10
SE00000UC00
SE00000UC00
CV217 DIS@
CV38 DIS@
1 1 1 1 E26 FB V DD Q AC2 GND GND N12
CV218 DIS@
CV221 DIS@
CV222
CV215
F14 FB V DD Q AC22 N14
Page
A GND GND A
F21 FB V DD Q AC26 GND GND N16
21
21
G13 FB V DD Q AC5 GND GND N18
2 2 2 2
DIS@
DIS@
G14 FB V DD Q AC8 GND GND P11
G15 FB V DD Q AD12 GND GND P13
G16 FB V DD Q AD13 GND GND P15
G18 FB V DD Q A26 GND GND P17
G19 FB V DD Q +VGA_CORE UV1E AD15 GND P2
GND
G20 FB V DD Q COMMON AD16 GND GND P23
G21 FB V DD Q Voltage by GPU SKU 11/14 NVVDD AD18 GND GND P26
L22 FB V DD Q K10 V D D AD19 GND GND P5
L24 FB V DD Q K12 V D D AD21 GND GND R10
L26 FB V DD Q K14 V D D AD22 GND GND R12
M21 FB V DD Q K16 V D D AE11 GND R14
GND
N21 FB V DD Q K18 V D D AE14 GND R16
GND
R21 FB V DD Q L11 V D D AE17 GND R18
GND
T21 FB V DD Q L13 V D D AE20 GND T11
GND
V21 FB V DD Q L15 V D D AB11 GND T13
GND
W 21 FB V D D Q L17 V D D AF1 T15
GND GND
M10 V D D AF11 T17
GND GND
M12 V D D AF14 U10
GF117 GND GND
M14 V D D AF17 U12
GF119 GND GND
M16 V D D AF20 U14
GK208 GND GND
M18 V D D AF23 U16
GND GND
H24 N11 V D D AF5 U18
F B VD D Q _A O N FBVDDQ GND GND
H26 N13 V D D AF8 U2
F B VD D Q _A O N FBVDDQ GND GND
J21 N15 V D D
22U_0603_6.3V6M
M
10U_0603_6.3V6
F B VD D Q _A O N FBVDDQ
AG2 GND GND U23
N17 V D D
1 1 K21 F B V D D Q _A O N FBVDDQ
AG26 GND GND U26
P10 V D D
CV44
AB14 U5
CV45
P12 V D D GND GND
B1 GND GND V11
P14 V D D
B11 GND GND V13
2 2 P16 V D D
DIS@
DIS@
B14 GND V15
P18 V D D GND
R11 V D D B17 GND GND V17
R13 V D D B20 GND GND Y2
B B5 Y5 B
T10 V D D GND GND
Place near GPU T12 V D D B8 GND
T14 V D D E11 GND
E14
CIZ00 22uF x1 change to 10uF x2 T16 V D D
E17
GND
T18 V D D GND
Vinafix.com
U11 V D D E2 GND
U13 V D D E20 GND
U15 V D D E22 GND
U17 V D D E25 GND
Near Ball +1.35VS_VRAM V10 V D D E5 GND
V12 V D D E8 GND
V14 V D D H2 GND
F B _ C A L_PD_VD DQ D22 RV41 1 DIS@ 2 40.2_0402_1% V16 V D D H23 GND
V18 V D D H25 GND
H5 GND
F B _ C A L_PU_G N D C24 RV42 2 DIS@ 1 40.2_0402_1% K11 GND
K13 GND
N16S-GT-S-A2_BGA595 K15 GND
B25 RV43 2 DIS@ 1 60.4_0402_1% @ K17 GND
F B _ C A LTE RM _G ND
L10 GND
L12 GND
N16S-GT-S-A2_BGA595 L14 GND
@ L16 GND
L18 GND
L2 GND
L23 GND
L25 GND
L5 GND GND AA7
M11 GND GND AB7
N16S-GT-S-A2_BGA595
@
C UV1C C
COMMON
14/14 XVDD/VDD33
+3VS_DGPU
Under GPU Near GPU
AD10 NC VDD33 G8
AD7 NC V D D 3 3 G9
GM108
G10
K
0.1U_0201_10V6
K
0.1U_0201_10V6
1U_0201_6.3V6M
M
4.7U_0402_6.3V6
3V3_AON VDD33
SE00000UC00
G12
CV216 DIS@
3V3_AON VDD33 1 1 1
1
CV220
CV211
CV219 DIS@
F11 3 V 3 A UX_NC
2
2 2 2
DIS@
DIS@
V5 F E R M I_ R SV D1_NC
V6 F E R M I_ R SV D2_NC
+3VS_DGPU_AON
Under GPU Near GPU

CONFIGURABLE
POWERCHANNELS
4.7U_0402_6.3V6M
1U_0201_6.3V6M
K
0.1U_0201_10V6
* nc on substrate
CV213 DIS@
SE00000UC00
1 1
CV212 DIS@
CV214
G1 X PW R_G 1
G2 X PW R_G 2
21
G3 X PW R_G 3
G4 2 2
X PW R_G 4
DIS@
G5 X PW R_G 5
G6 X PW R_G 6
G7 X P W R_G 7
V1 X P W R_V1
V2 X P W R_V2
** XPWR pins are configurable.
These pins are not connected on the substrate.
D D
W1 X PW R_W 1 Therefore, XPW R pins can be assigned as needed, to
W2 X PW R_W 2
W3 X PW R_W 3 improve Top layer routing, power delivery.
W4 X P W R_W 4
N16S-GT-S-A2_BGA595
@
NV(3/5)-POWER
1 2 3 4 5
1 2 3 4 5
+3VS_DGPU_AON
UV1N
COMMON
GPIO +3VS_DGPU_AON
PLT_RST_VGA_HOLD#
DGPU_MAIN_EN
1
2
RPV5
8
7
8/14 MISC1
D9 I2CS_SCL
I 2 CS_ SCL
I 2 CS_ SDA
D8 I2CS_SDA
RV203 1 DIS@ 2 2.2K_0402_5% RV204
1 DIS@ 2 2.2K_0402_5%
I2CS SMBUS: 0x96 PSI
VGA_AC_DET
3
4
6
5
I 2 CC_ SCL A9 I2CC_SCL RV205 1 @ 2 2.2K_0402_5%

and 0x9E(Default) 10K_0804_8P4R_5%
B9 I2CC_SDA RV206 1 @ 2 2.2K_0402_5% DIS@
I2 C C _ SD A
E12 GF117 GPU_EVENT#_D RV72 1 GC6@ 2 10K_0402_5%

T HE R M D N
C9 I2CB_SCL
NC I2 C B _ SCL
F12 C8 I2CB_SDA GPIO8_OVERT# RV69 1 DIS@ 2 100K_0402_5%
T HE R M D P NC I2 C B _ SDA
GPU_JTAG_TCK AE5 J TAG_ TCK

T231 TP@
GPU_JTAG_TMS AD6 J TAG_ TMS RPV6
T232 TP@ GPU_JTAG_TDI AE6 J TAG_ TDI GPIO9_ALERT# 1 8
A T242 TP@ GPU_JTAG_TDO A
T243 TP@ AF6 J TAG_ TDO 2 7
GPU_JTAG_TRST# AG4 J TAG_ TRST# GPI O0
C6 GPIO0_GC6_FB_EN RV202 1 2 0_0402_5% GPU_JTAG_TRST# 3 6
GC6_FB_EN <11,25> FB_CLAMP
GPI O1 B2 4 5
<25> FB_CLAMP
G P IO 2
GPI O3
C7
D6
For GC6 2.0 10K_0804_8P4R_5%
GPI O4 F9 DIS@
GPI O5
A3 DGPU_MAIN_EN
A4 GPU_EVENT#_D DV1 GC6@ 2 1 S SCH DIO RB751V40SC76 DGPU_MAIN_EN <26,51> RPV3
GK208 G P IO 6 GPU_EVENT# <11> I2CA_SCL 1 8
GM108 GPI O7 B6 GPIO8_OVERT# SCS00002G00 <22> I2CA_SCL I2CA_SDA
OVERT GPI O8 A6 2 7
GPIO9_ALERT#
GPI O9 F8 MEM_VREF
DV5 DIS@ 2 1 S SCH DIO RB751V40 SC76
GPU_PROHOT# <36> To EC <22> I2CA_SDA I2CB_SCL
I2CB_SDA
3 6
SCS00002G00 4 5
GPI O1 0 C5 GPU_VID0 MEM_VREF <27>
GPI O1 1 E7 VGA_AC_DET To DGPU VR
D7 GPU_VID0 <51>
GPI O1 2
B4 PSI
From EC 2.2K_0804_8P4R_5%
G P IO 1 3 PSI <51> To DGPU VR @
GM108 GK208 GF117 GF119 GPU_BUFRST RV67 1 @ 2 10K_0402_5%

GPIO16 GPIO16 NC G P IO 16 D5
E6 GPU_TESTMODE RV71 1 DIS@ 2 10K_0402_5%
GPIO20 GPIO20 NC G P IO 20 <21> GPU_TESTMODE
C4 PLT_RST_VGA_HOLD#
GPIO21 GPIO8 NC G P IO 2 1 PLT_RST_VGA_HOLD# <21> MEM_VREF RV102 1 DIS@ 2 100K_0402_5%
E9 PLT_RST_VGA_MON#
GPIO8 NC NC NC PLT_RST_VGA_MON# <21>
PLT_RST_VGA_MON# RV70 1 @ 2 10K_0402_5%
N16S-GT-S-A2_BGA595 GC6_FB_EN RV88 1 GC6@ 2 10K_0402_5%

@
UV1L
STRAP STRAP STRAP0 : PU 49.9K (50K)
STRAP[1:5] : Reserved
COMMON
10/14MISC2
+3VS_DGPU_AON
+3VS_DGPU
E10 VM O N_ I N0 _ NC
F10 VM O N_ I N1 _ NC R O M _ C S# D12
1
1
49.9K_0402_1%
45.3K_0402_1%
4.99K_0402_1%
4.99K_0402_1%
B B
1
B12 ROM_SI
14.7K_0402_1%
4.99K_0402_1%
4.99K_0402_1%
RV384
10K_0402_1%
ROM_ SI
ROM_SO
DIS@
RV81
@ @ @ @
RV389
RV382
RV51
RV61
R O M _ S O A12
ROM_SCLK
DIS@
RV84
RV80
STRAP0 D1 S T R AP 0 R O M _ S CL K C12
STRAP1 D2 S TR AP 1 @ @
2
2
2
E4 S TR AP 2 NC FOR
STRAP2
2
GM108
STRAP3 E3 S TR AP 3
Vinafix.com
STRAP4 D3 ROM_SI STRAP0
S TR AP 4
ROM_SO STRAP1
ROM_SCLK STRAP2
STRAP3
+3VS_DGPU_AON C1 S T R AP 5 _ NC STRAP4
GPU_BUFRST
1
4.99K_0402_1%
4.99K_0402_1%
4.99K_0402_1%
RV265 B UF R ST # D11
1
1
1
@
DIS@
RV65
RV64
RV381
4.99K_0402_1%
4.99K_0402_1%
4.99K_0402_1%
45.3K_0402_1%
4.99K_0402_1%
0_0402_5%
STRAPREF0 F6 M UL T I S T R AP_ REF 0 _ G ND
RV383
RV388
RV387
P G O O D D10
RV385
RV390
1@2 NC
GF117 @ @ @ @ @
GK208 GF117 GF119
2
2
2
1
GM108 GK208
2
2
2
2
RV380 F4 GM108
RV65 Stuff in X76.
M UL T I S T R AP_ REF 1 _ G ND NC
40.2K_0402_1%
DIS@ F5 M UL T I S T R AP_ REF 2 _ G ND
NC
2
N16S-GT-S-A2_BGA595
@
Internal Thermal Sensor
+3VS_DGPU_AON
+3VS Reserve for

leakage issue
Link to PCH SML1
5
G
+3VS +3VS DIS@ PU @ PCH SIDE
QV2B
I2CS_SCL
2
4 3
S
RV15 @ RV26 @ EC_SMB_CK2 <8,36>
D
10K_0402_5% 10K_0402_5% 2N7002KDW_SOT363-6
C C
DV4 @
1
2
RB751V-40_SOD323-2
G
VGA_AC_DET 2 1 AC_PRESENT DIS@
AC_PRESENT <10,36> RAM_CFG[3:0] BAX40 QV2A
(ROM_SI)
I2CS_SDA 1 6
S
RV126 1 @ 2 0_0402_5% 0x0 4.99K(L) S2G@ EC_SMB_DA2 <8,36>
D
2N7002KDW_SOT363-6
0x1 10.0K(L) M2G@

0x2 15.0K(L)
0x3 20.0K(L)
0x4 24.9K(L)
CONFIG
RAM_CFG X76 ROM_SI 0x5 30.1K(L) H2G@
0x0 RV65 UV6 S2G_R1@ UV7 S2G_R1@
K4G80325FB-HC28 0x6 34.8K(L)
4.99K(L) X7677538L04 S2G@ 4.99K +-1% 0402 SA000092D10 SA000092D10
SD034499180 UV6 S2G_R3@ UV7 S2G_R3@ K4G80325FB-HC28
S2G@ SA000092D30 SA000092D30
0x7 45.3K(L)
0x1 RV65
UV6 M2G_R1@ UV7 M2G_R1@
MT51J256M32HF-70:A 0x8 4.99K(H)
SA00009TV00 SA00009TV00
10.0K(L) X7677538L05 M2G@ 10K +-1% 0402
UV6 M2G_R3@ UV7 M2G_R3@
SD034100280
SA00009TV20 SA00009TV20
MT51J256M32HF-70:A 0x9 10.0K(H)
M2G@
0x5 RV65 UV6 H2G_R1@ UV7 H2G_R1@
H5GC8H24MJR-R0C 0xA 15.0K(H)
30.1K(L) X7677538L06 H2G@ 30.1K +-1% 0402 SA00009U100 SA00009U100
SD034301280 UV6 H2G_R3@ UV7 H2G_R3@ H5GC8H24MJR-R0C 0xB 20.0K(H)
H2G@ SA00009U130 SA00009U130
0xC 24.9K(H)
D 0xD 30.1K(H) D
0xE 34.8K(H)
0x6 RV65
34.8K +-1% 0402 RESERVED 0xF 45.3K(H)
34.8K(L) SD034348280
@
0x7 RV65
45.3K +-1% 0402 RESERVED
45.3K(L) SD034453280
0x4
@ Securiiity Clllassiiifiiicatiiion Compalll Secret Data Compal Electronics, Inc.
RV65 Issued Date 2018/03/09 2019/03/09 Tiitttlle
Deciiiphered Date
24.9K +-1% 0402 RESERVED NV(4/5)-GPIO/Strap
24.9K(L) SD034249280 THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
@ Siiize Documenttt Numberrr Rev
TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIIT CONTAIIINS
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIORWRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IIINC... LA-G202P 1..0
Dattte::: Frrriiday,,, Marrrch 09,,, 2018 Sheett 24 o ff 55

1 2 3 4 5
1 2 3 4 5
UV1B
For GC6 +3VS
COMMON
2/14 FBA 1
<27> FB_A_D[0..31] FB_A_D0 FB_CLAMP
E18 F B A _D0 F B _ C L AMP F3 CV223 @
FB_A_D1 NC FB_CLAMP <24>
F18 F B A _ D1 0.1U_0201_10V K X5R
FB_A_D2 E16 F B A _ D 2
FB_A_D3 GF119 2
F17 F B A _ D3 UV23 GC6@
FB_A_D4 D20 F B A _ D 4 S IC TC7SH32FU SSOP 5P
5
FB_A_D5 D21 F B A _ D 5 SA007320120
A FB_A_D6 GC6_FB_EN A
F20 F B A _ D6 2
<11,24> GC6_FB_EN B
G Vcc
FB_A_D7 E21 F B A _ D 7 4
FB_A_D8 Y 1.35V_PWR_EN <26,52>
E15 F B A _ D 8 1
FB_A_D9 <21,26,51> DGPU_PWROK A
D15 F B A _ D 9
FB_A_D10 F15 F B A _ D10
3
FB_A_D11 F13 F B A _ D11
FB_A_D12 C13 F B A _ D 12
FB_A_D13 B13 F B A _ D1 3
FB_A_D14 E13 F B A _ D1 4 RV201 1 2 0_0402_5%
FB_A_D15 D13 F B A _ D 15 NOGC6@
FB_A_D16 B15 F B A _ D1 6
FB_A_D17 C16 F B A _ D 17 Stuff RV201 if not support GC6
FB_A_D18 A13 F B A _ D1 8
FB_A_D19 A15 F B A _ D1 9
FB_A_D20 B18 F B A _ D2 0
FB_A_D21 A18 F B A _ D2 1
FB_A_D22 A19 F B A _ D2 2
FB_A_D23
FB_A_D24
C19 F B A _ D 23
B24 F B A _ D2 4
From DG-07158-001_v05_secured(NVDIA Spec)
FB_A_D25 C23 F B A _ D 25
FB_A_D26 A25 F B A _ D2 6
FB_A_D27 A24 F B A _ D2 7
FB_A_D28 A21 F B A _ D2 8
FB_A_D29 B21 F B A _ D2 9
FB_A_D30 FB_A_CMD[0..31] <27>
C20 F B A _ D 30
FB_A_D31 C21 F B A _ D 31
<27> FB_A_D[32..63] FB_A_D32 R22 F B A _ D 32
FB_A_D33 R24 F B A _ D 33 C27 FB_A_CMD0
F B A _ C MD0
FB_A_D34 T22 F B A _ D34 C26 FB_A_CMD1
F B A _ C MD1
FB_A_D35 R23 F B A _ D 35 E24 FB_A_CMD2 +1.35VS_VRAM +1.35VS_VRAM
F B A _ C MD2
FB_A_D36 N25 F B A _ D 36 F24 FB_A_CMD3
F B A _ C MD3
FB_A_D37 FB_A_CMD4
10K_0402_5%
%
10K_0402_5
N26 F B A _ D 37 F B A _ C MD4 D27
2
FB_A_D38 N23 F B A _ D 38 D26 FB_A_CMD5
F B A _ C MD5
FB_A_D39 FB_A_CMD6
DIS@
RV255
DIS@
RV256
N24 F B A _ D 39 F B A _ C MD6 F25
FB_A_D40 V23 F B A _ D4 0 F26 FB_A_CMD7
F B A _ C MD7
B FB_A_D41 V22 F B A _ D4 1 F23 FB_A_CMD8 B
F B A _ C MD8
FB_A_D42 T23 F B A _ D42 G22 FB_A_CMD9
F B A _ C MD9
1
1
FB_A_D43 U22 F B A _ D 43 G23 FB_A_CMD10
F B A _ C MD10
FB_A_D44 Y24 F B A _ D4 4 G24 FB_A_CMD11 FBA_CKE_L FB_A_CMD14
F B A _ C MD11
FB_A_D45 AA24 FBA_D45 F27 FB_A_CMD12
F B A _ C MD12
Vinafix.com
FB_A_D46 Y22 F B A _ D4 6 G25 FB_A_CMD13 FBA_CKE_H FB_A_CMD30
F B A _ C MD13
FB_A_D47 AA23 FBA_D47 G27 FB_A_CMD14
F B A _ C MD14
FB_A_D48 AD27 FBA_D48 G26 FB_A_CMD15 FBA_RST_L FB_A_CMD13
F B A _ C MD15
FB_A_D49 AB25 FBA_D49 M24 FB_A_CMD16
F B A _ C MD16
FB_A_D50 AD26 FBA_D50 M23 FB_A_CMD17 FBA_RST_H FB_A_CMD29
F B A _ C MD17
FB_A_D51 AC25 FBA_D51 K24 FB_A_CMD18
F B A _ C MD18
FB_A_D52 AA27 FBA_D52 FB_A_CMD19
10K_0402_5%
%
10K_0402_5
F B A _ C MD19 K23
FB_A_D53
GDDR5 design
2
AA26 FBA_D53 M27 FB_A_CMD20
F B A _ C MD20
FB_A_D54 FB_A_CMD21
DIS@
RV253
DIS@
RV254
W 26 F B A _ D 54 F B A _ C MD21 M26
FB_A_D55 Y25 F B A _ D5 5 M25 FB_A_CMD22
F B A _ C MD22
FB_A_D56 R26 F B A _ D 56 K26 FB_A_CMD23
F B A _ C MD23
FB_A_D57 T25 F B A _ D57 K22 FB_A_CMD24
F B A _ C MD24
1
1
FB_A_D58 N27 F B A _ D 58 J23 FB_A_CMD25
F B A _ C MD25
FB_A_D59 R27 F B A _ D 59 J25 FB_A_CMD26
F B A _ C MD26
FB_A_D60 V26 F B A _ D6 0 J24 FB_A_CMD27
F B A _ C MD27
FB_A_D61 V27 F B A _ D6 1 K27 FB_A_CMD28
F B A _ C MD28
FB_A_D62 FB_A_CMD29
FB_A_D63
W 27 F B A _ D 62 F B A _ C MD29 K25
FB_A_CMD30
Refer CIZ00 LA-E011
W 25 F B A _ D 63 F B A _ C MD30 J27
J26 FB_A_CMD31
F B A _ C MD31
<27> FB_A_DBI[3..0] FB_A_DBI0 D19 F B A _ D Q M 0
FB_A_DBI1 D14 F B A _ D Q M 1 FBVDDQ_GPU
FB_A_DBI2 C17 F B A _ D Q M 2
FB_A_DBI3 GF117/GF119
C22 F B A _ D Q M 3 GK208
+1.35VS_VRAM
<27> FB_A_DBI[7..4] FB_A_DBI4 P24 F B A _ D Q M 4
FB_A_DBI5 W 24 F B A _ C MD32 B19 1.35V
FB A _DQM5 NC
FB_A_DBI6 AA25
FB A _DQM6
FB_A_DBI7 U25 F B A _ C MD34 F22 RV82 1 @ 2 60.4_0402_1%
FB A _DQM7 FBA_DEBUG0
FBA_DEBUG1 F B A _ C MD35 J22 RV83 1 @ 2 60.4_0402_1%
C
<27> FB_A_EDC[3..0] FB_A_EDC0 C
E19 F B A _ D Q S_W P0
FB_A_EDC1 C15 F B A _ D Q S_W P1
FB_A_EDC2 FB_A_CLK0
Refer CIZ00 LA-E011 FB_A_EDC3
B16 F B A _ D Q S_W P2 F B A _ C LK0 D24
FB_A_CLK#0 FB_A_CLK0 <27>
B22 F B A _ D Q S_W P3 F B A _ C LK0# D25
<27> FB_A_EDC[7..4] FB_A_EDC4 FB_A_CLK1 FB_A_CLK#0 <27>
R25 F B A _ D Q S_W P4 F B A _ C LK1 N22 FB_A_CLK1 <27>
FB_A_EDC5 W 23 F B A _ DQ S _W P5 F B A _ C LK1# M22
FB_A_CLK#1
FB_A_EDC6 FB_A_CLK#1 <27>
AB26 F B A _ D Q S_W P6
FB_A_EDC7 T26 F B A _ DQ S _W P7
FB_A_WCK0
F19 F B A _ DQ S _RN0 F B A _W CK01 D18
FB_A_W CK#0 FB_A_WCK0 <27> Refer CIZ00 LA-E011
C14 F B A _ D Q S_ RN1 F B A _W CK01# C18
FB_A_W CK1 FB_A_WCK#0 <27>
A16 F B A _ DQ S _RN2 F B A _W CK23 D17
FB_A_W CK#1 FB_A_WCK1 <27>
A22 F B A _ DQ S _RN3 F B A _W CK23# D16 FB_A_WCK#1 <27>
P25 F B A _W CK45 T24 FB_A_WCK2
F B A _ DQ S _RN4 FB_A_WCK2 <27>
W 22 F B A _W CK45# U24
FB_A_W CK#2
F B A _ D Q S_R N5
FB_A_W CK3 FB_A_WCK#2 <27>
AB27 F B A _ D Q S_R N6 F B A _W CK67 V24 FB_A_WCK3 <27>
T27 F B A _W CK67# V25
FB_A_W CK#3
F B A _ DQ S _RN7 FB_A_WCK#3 <27>
GF119
F B _ P L LAVDD F16
+1.0VS_PLLAVDD +1.0VS_PLLAVDD +1.0VS_DGPU
NC
F B _ P L LAVDD P22
Close to P22 Close to F16 1.0V DIS@
F B _ D L LAVDD H22 1 2
FB_PLLAVDD
LV7 S SUPPRE_ MURATA BLM15PD300SN1D 0402
0.1U_0201_10V K X5R
CV53 DIS@
0.1U_0201_10V K X5R
CV55 DIS@
0.1U_0201_10V K X5R
CV52 DIS@
M
22U_0603_6.3V6
CV51 DIS@
GF117 SM01000LX00
1 2 1 1
For VRAM DEBUG using 2 1 2 2
FB_VREF D23
T2401 TP@ FB_VREF_PROBE
D D
Close to H22 Near GPU
N16S-GT-S-A2_BGA595
@

NV(5/5)-MEMORY FBA
1 2 3 4 5
5 4 3 2 1
I_Continuous(Max) : 0.79 A(+1.0VS_DGPU)

RON(Max) : 22 mohm
+1.0V_PRIM to +1.0VS_DGPU V drop : 0.0175 V
+3VS to +3VS_DGPU +5VALW +3VS +3VS_DGPU Rising : ~ 208us
QV26 DIS@
ME2301DC-G_SOT23-3
2
+5VALW +1.35VS_VRAM +5VALW +1.0VALW +1.0VS_DGPU
RV261 QV5 DIS@
D
3 1
47K_0402_5% ME2320D-G 1N SOT-23-3
1
470_0603_5%
RV260 @
DIS@
1
100K_0402_1%
RV252 @
22_0603_1%
RV251 @
RV262 DIS@ 1 3
S
G
1
1U_0201_6.3V6M
DGPU_MAIN_EN# 10K_0402_5% DGPU_MAIN_EN#_GATE
SE00000UC00
0.1U_0201_10V6K
CV133 @
1
47K_0402_5%
RV266 DIS@
CV314 DIS@
G
2
2
2 1
2
2
6
D D
RV263
2
SE00000UC00
1U_0201_6.3V6M
CV318 @
0_0402_5% 1 1 D
3
D QV145B @
1
DGPU_MAIN_EN 1 2 2 2 DGPU_MAIN_EN# 1.35V_PWR_EN# 5
0.1U_0201_10V K X5R
CV320 DIS@
4.7U_0402_6.3V6M
CV319
QV30A DIS@ 2N7002KDW_SOT363-6
<24,51> DGPU_MAIN_EN G G
L2N7002DW1T1G 2N SC88-6
1
2 2 S QV25 @
6
@ 2N7002K_SOT23-3 D QV145A @ S
4
1
2N7002KDW_SOT363-6
SE00000UC00
2
1U_0201_6.3V6M
CV321 @
<25,52> 1.35V_PWR_EN G
DGPU_MAIN_EN DGPU_MAIN_EN_GATE 2 DIS@ 1 DGPU_MAIN_EN_R_GATE RV85
1@2
2
S RV128 0_0402_5% 47K_0402_5%
1
D QV146 DIS@
DGPU_MAIN_EN# 2
0.1U_0201_10V K X5R
CV316 DIS@
2N7002K_SOT23-3 2 1
G DIS@ CV315
S .047U_0402_16V7K
3
SE076473K80 1 2
+3VS to +3VS_DGPU_AON +5VALW +3VS +3VS_DGPU_AON
QV20 DIS@
ME2301DC-G_SOT23-3
2
D
3 1
RV258
47K_0402_5%
1
G
DIS@
1
470_0603_5%
RV257 @
RV259 DIS@
DGPU_PW R_EN# 10K_0402_5% DGPU_PWR_EN#_GATE
2
3
SE00000UC00
1U_0201_6.3V6M
CV311 @
RV264 1 1 D
1
2
0_0402_5% DGPU_PW R_EN#
2
0.1U_0201_10V K X5R
CV313 DIS@
4.7U_0402_6.3V6M
CV312
QV30B DIS@
DGPU_PWR_EN 1 2 5 G
<11,36> DGPU_PWR_EN L2N7002DW1T1G 2N SC88-6
1
2 2 S QV19 @
C C
3
@ 2N7002K_SOT23-3
4
1
SE00000UC00
1U_0201_6.3V6M
CV317 @
Vinafix.com
2
+3VS_DGPU_AON
2
RG82
10K_0402_5%
DIS@
DG4
1
DGPU_PW ROK 1
<21,25,51> DGPU_PWROK 2 S SCH DIO RB751V40 SC76
SCS00002G00
DIS@
+1.35VGS_PGOOD RG83 1 2 0_0402_5% GPU_ALL_PGOOD

<52> +1.35VGS_PGOOD GPU_ALL_PGOOD <11>
B B
A A
Securiiity Clllassiiifiiicatiiion Compalll Secret Data Compal Electronics, Inc.

Issued Date 2018/03/09 Deciiiphered Date 2019/03/09 Tiitttlle
THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
DGPU_DC/DC Interface
Sii ze Documenttt Numberrr Rev
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIORWRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IIINC...
LA-G202P 1..0
Dattte::: Frrriiday,,, Marrrch 09,,, 2018 Sheettt 26 o ff55

5 4 3 2 1
5 4 3 2 1
VRAM Memory Partition A UV6 MF=0 UV7 MF=1

MF= 0 MF =1 MF= 1 MF =0 MF=0 MF=1 MF= 1 MF=0
A4 FB_A_D0 A4 FB_A_D56
FB_A_EDC0 C2 DQ24 DQ0 A2 FB_A_D1 FB_A_EDC7 C2 DQ24 DQ0 A2 FB_A_D57
FB_A_EDC1 EDC3 DQ25 FB_A_D2 FB_A_EDC6 EDC3 DQ25 FB_A_D58
C13 EDC0 DQ1 B4 C13 EDC0 DQ1 B4
FB_A_EDC2 R13 EDC1 EDC2 DQ26 DQ2 B2 FB_A_D3 FB_A_EDC5 R13 EDC1 EDC2 DQ26 DQ2 B2 FB_A_D59
FB_A_EDC3 R2 EDC2
EDC3
EDC1
EDC0
DQ27
DQ28
DQ3
DQ4
E4 FB_A_D4
FB_A_D5
BYTE0 FB_A_EDC4 R2 EDC2
EDC3
EDC1
EDC0
DQ27
DQ28
DQ3
DQ4
E4 FB_A_D60
FB_A_D61
BYTE7
E2 E2
DQ29 DQ5 F4 FB_A_D6 DQ29 DQ5 F4 FB_A_D62
D2 DQ30 DQ6 F2 FB_A_D7 D2 DQ30 DQ6 F2 FB_A_D63
<25> FB_A_DBI0 D13 DBI0# DBI3# DQ31 DQ7 A11 FB_A_D8 <25> FB_A_DBI7 D13 DBI0# DBI3# DQ31 DQ7 A11 FB_A_D48
<25> FB_A_DBI1 P13 DBI1# DBI2# DQ16 DQ8 A13 FB_A_D9 <25> FB_A_DBI6 P13 DBI1# DBI2# DQ16 DQ8 A13 FB_A_D49
<25> FB_A_DBI2 P2 DBI2# DBI1# DQ17 DQ9 B11 FB_A_D10 <25> FB_A_DBI5 P2 DBI2# DBI1# DQ17 DQ9 B11 FB_A_D50
D <25> FB_A_DBI3 DBI3# DQ18 DQ10 B13 FB_A_D11 <25> FB_A_DBI4 DBI3# DQ18 DQ10 B13 FB_A_D51 D
DBI0# FB_A_D12 DBI0# FB_A_D52
<25> FB_A_CLK0
FB_A_CLK0 J12 DQ19
DQ20
DQ11
DQ12
E11
FB_A_D13
BYTE1 <25> FB_A_CLK1
FB_A_CLK1 J12 DQ19
DQ20
DQ11
DQ12
E11
FB_A_D53
BYTE6
FB_A_CLK#0 J11 CK E13 FB_A_CLK#1 J11 CK E13
<25> FB_A_CLK#0 FB_A_CMD14 J3 CK# DQ21 DQ13 F11 FB_A_D14 <25> FB_A_CLK#1 FB_A_CMD30 J3 CK# DQ21 DQ13 F11 FB_A_D54
CKE# DQ22 DQ14 F13 FB_A_D15 CKE# DQ22 DQ14 F13 FB_A_D55
DQ23 DQ15 U11 FB_A_D16 DQ23 DQ15 U11 FB_A_D40
FB_A_CMD2 H11 DQ8 DQ16 U13 FB_A_D17 FB_A_CMD19 H11 DQ8 DQ16 U13 FB_A_D41
FB_A_CMD4 K10 BA0/A2 BA2/A4 DQ9 DQ17 T11 FB_A_D18 FB_A_CMD17 K10 BA0/A2 BA2/A4 DQ9 DQ17 T11 FB_A_D42
FB_A_CMD3 K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 FB_A_D19 FB_A_CMD18 K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 FB_A_D43
FB_A_CMD1 H10 BA2/A4 FB_A_D20
BA3/A3
BA0/A2 DQ11
DQ12
DQ19
DQ20
N11
FB_A_D21
BYTE2 FB_A_CMD20 H10 BA2/A4
BA3/A3
BA0/A2 DQ11
DQ12
DQ19
DQ20
N11 FB_A_D44
FB_A_D45
BYTE5
BA1/A5 N13 BA1/A5 N13
DQ13 DQ21 M11 FB_A_D22 DQ13 DQ21 M11 FB_A_D46
FB_A_CMD6 K4 DQ14 DQ22 M13 FB_A_D23 FB_A_CMD26 K4 DQ14 DQ22 M13 FB_A_D47
FB_A_CMD11 H5 A8/A7 A10/A0 DQ15 DQ23 U4 FB_A_D24 FB_A_CMD23 H5 A8/A7 A10/A0 DQ15 DQ23 U4 FB_A_D32
FB_A_CMD10 H4 A9/A1 A11/A6 DQ0 DQ24 U2 FB_A_D25 FB_A_CMD22 H4 A9/A1 A11/A6 DQ0 DQ24 U2 FB_A_D33
FB_A_CMD7 K5 A10/A0 A8/A7 DQ1 DQ25 T4 FB_A_D26 FB_A_CMD27 K5 A10/A0 A8/A7 DQ1 DQ25 T4 FB_A_D34
FB_A_CMD9 J5 A11/A6 DQ2 DQ26 T2 FB_A_D27 FB_A_CMD25 J5 A11/A6 DQ2 DQ26 T2 FB_A_D35
A9/A1 FB_A_D28 A9/A1
A12/RFU/NC DQ3
DQ4
DQ27
DQ28
N4
FB_A_D29
BYTE3 A12/RFU/NC DQ3
DQ4
DQ27
DQ28
N4 FB_A_D36
FB_A_D37
BYTE4
A5 N2 A5 N2
U5 VPP/NC DQ5 DQ29 M4 FB_A_D30 U5 VPP/NC DQ5 DQ29 M4 FB_A_D38
VPP/NC DQ6 DQ30 M2 FB_A_D31 +1.35VS_VRAM VPP/NC DQ6 DQ30 M2 FB_A_D39
DQ7 DQ31 DQ7 DQ31
RV116 DIS@ 2 1 1K_0402_1% J1 +1.35VS_VRAM RV130 DIS@ 2 1 1K_0402_1% J1 +1.35VS_VRAM
RV118 DIS@ 2 1 1K_0402_1% J10 MF RV132 DIS@ 2 1 1K_0402_1% J10 MF
RV120 DIS@ 2 1 121_0402_1% J13 SEN B1 RV134 DIS@ 2 1 121_0402_1% J13 SEN B1
ZQ VDDQ D1 ZQ VDDQ D1
VDDQ F1 VDDQ F1
FB_A_CMD8 J4 VDDQ M1 FB_A_CMD24 J4 VDDQ M1
FB_A_CMD12 G3 ABI# VDDQ P1 FB_A_CMD31 G3 ABI# VDDQ P1
FB_A_CMD0 G12 RAS# CAS# VDDQ T1 FB_A_CMD21 G12 RAS# CAS# VDDQ T1
FB_A_CMD15 L3 CS# WE# VDDQ G2 FB_A_CMD28 L3 CS# WE# VDDQ G2
FB_A_CMD5 L12 CAS# RAS# VDDQ L2 FB_A_CMD16 L12 CAS# RAS# VDDQ L2
W E# CS# VDDQ B3 W E# CS# VDDQ B3
VDDQ D3 VDDQ D3
VDDQ F3 VDDQ F3
FB_A_W CK#0 D5 VDDQ H3 FB_A_W CK#3 VDDQ H3
FB_A_WCK0 D5
<25> FB_A_WCK#0 W CK23# VDDQ <25> FB_A_WCK#3 FB_A_WCK3 W CK23#
D4 W CK01# K3 D4 W CK01# VDDQ K3
<25> FB_A_WCK0 W CK01 W CK23 VDDQ <25> FB_A_WCK3 W CK01 W CK23 VDDQ M3
M3
FB_A_W CK#1 P5 VDDQ P3 FB_A_W CK#2 P5 VDDQ P3
<25> FB_A_WCK#1 FB_A_WCK1 P4 W CK23# W CK01# VDDQ T3 <25> FB_A_WCK#2 FB_A_WCK2 P4 W CK23# W CK01# VDDQ T3
<25> FB_A_WCK1 W CK23 W CK01 VDDQ E5 <25> FB_A_WCK2 W CK23 W CK01 VDDQ E5
VDDQ N5 VDDQ N5
C VDDQ VDDQ C
A10 E10 A10 E10
U10 VREFD VDDQ N10 U10 VREFD VDDQ N10
+FBA_VREFC0 J14 VREFD VDDQ B12 +FBA_VREFC0 J14 VREFD VDDQ B12
VREFC VDDQ D12 VREFC VDDQ D12
VDDQ F12 VDDQ F12
VDDQ H12 VDDQ H12
Vinafix.com
FB_A_D[0..31] FB_A_CMD13 J2 VDDQ FB_A_CMD29 VDDQ K12
K12 J2
<25> FB_A_D[0..31] RESET# VDDQ RESET# VDDQ M12
M12
FB_A_D[32..63] VDDQ P12 VDDQ P12
<25> FB_A_D[32..63] VDDQ VDDQ
T12 T12
VDDQ G13 VDDQ G13
H1 VDDQ L13 H1 VDDQ L13
FB_A_EDC[0..3] K1 VSS VDDQ B14 K1 VSS VDDQ B14
<25> FB_A_EDC[0..3] VSS VDDQ B5 VSS VDDQ D14
B5 D14
FB_A_EDC[4..7] G5 VSS VDDQ F14 VSS VDDQ
G5 F14
<25> FB_A_EDC[4..7] VSS VDDQ L5 VSS VDDQ M14
L5 M14
T5 VSS VDDQ P14 T5 VSS VDDQ P14
B10 VSS VDDQ T14 B10 VSS VDDQ T14
FB_A_CMD[0..15] D10 VSS VDDQ D10 VSS VDDQ
<25> FB_A_CMD[0..15] VSS VSS
G10 G10
FB_A_CMD[16..31] L10 VSS A1 L10 VSS A1
<25> FB_A_CMD[16..31] VSS VSSQ C1 P10 VSS VSSQ C1
P10
T10 VSS VSSQ E1 T10 VSS VSSQ E1
H14 VSS VSSQ N1 H14 VSS VSSQ N1
K14 VSS VSSQ R1 K14 VSS VSSQ R1
+1.35VS_VRAM VSS VSSQ U1 +1.35VS_VRAM VSS VSSQ U1
Near to UV6 G1
VSSQ H2
VSSQ K2 G1
VSSQ
VSSQ
H2
K2
L1 VDD VSSQ A3 L1 VDD VSSQ A3
G4 VDD VSSQ C3 G4 VDD VSSQ C3
RV1 DIS@ RV2 DIS@ L4 VDD VSSQ E3 L4 VDD VSSQ E3
C5 VDD VSSQ N3 C5 VDD VSSQ N3
FB_A_CLK0 40.2_0402_1% 40.2_0402_1% FB_A_CLK#0
1 2 1 2 R5 VDD VSSQ R3 R5 VDD VSSQ R3
C10 VDD VSSQ U3 C10 VDD VSSQ U3
R10 VDD VSSQ C4 R10 VDD VSSQ C4
1 VDD VSSQ R4 VDD VSSQ
CV19 DIS@ D11 D11 R4
G11 VDD VSSQ F5 G11 VDD VSSQ F5
0.01U_0402_16V7K
L11 VDD VSSQ M5 L11 VDD VSSQ M5
2 P11 VDD VSSQ F10 P11 VDD VSSQ F10
G14 VDD VSSQ M10 G14 VDD VSSQ M10
L14 VDD VSSQ C11 L14 VDD VSSQ C11
VDD VSSQ R11 VDD VSSQ R11
B B
VSSQ A12 VSSQ A12
VSSQ C12 VSSQ C12
VSSQ E12 VSSQ E12
VSSQ N12 VSSQ N12
Near to UV7 170-BALL

VSSQ R12
VSSQ U12 170-BALL
VSSQ
VSSQ
R12
U12
VSSQ H13 VSSQ H13
SGRAM GDDR5 VSSQ K13 SGRAM GDDR5 VSSQ K13
RV3 DIS@ RV5 DIS@ VSSQ A14 VSSQ A14
VSSQ C14 VSSQ C14
FB_A_CLK1 40.2_0402_1% 40.2_0402_1% FB_A_CLK#1
1 2 1 2 VSSQ E14 VSSQ E14
VSSQ N14
VSSQ N14
VSSQ R14 VSSQ R14
1 VSSQ U14 VSSQ
CV20 DIS@ U14
VSSQ VSSQ
0.01U_0402_16V7K
@ K4G80325FB-HC03_FBGA170~D @ K4G80325FB-HC03_FBGA170~D
2
+1.35VS_VRAM Near VRAM Near ball +1.35VS_VRAM Near VRAM Near ball
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
22U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
22U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
CV604 DIS@
CV605 DIS@
CV606 DIS@
CV608 DIS@
CV706 DIS@
CV705 DIS@
CV704 DIS@
CV701 DIS@
CV702 DIS@
CV601 DIS@
CV602 DIS@
+1.35VS_VRAM
CV708 @
CV603 @
CV607 @
CV703 @
CV707 @
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1
RV125 DIS@
549_0402_1%
Place near pin J14 of each vram
2
RV200 1 DIS@ 2 931_0402_1% +FBA_VREFC0 +1.35VS_VRAM Near ball +1.35VS_VRAM Near ball
+FBA_VREFC0
D
W=16mils
1
2
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1.33K_0402_1%
RV127 DIS@
820P_0402_25V7
CV158 DIS@
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
820P_0402_25V7
CV159 DIS@
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
<24> MEM_VREF 1 1
G
SE00000UC00
SE00000UC00
SE00000UC00
SE00000UC00
SE00000UC00
SE00000UC00
SE00000UC00
SE00000UC00
SE00000UC00
SE00000UC00
SE00000UC00
SE00000UC00
SE00000UC00
SE00000UC00
SE00000UC00
SE00000UC00
SE00000UC00
SE00000UC00
SE00000UC00
SE00000UC00
A A
1
1
1
1
1
1
1
1
CV613 DIS@
CV709 DIS@
CV711 DIS@
CV712 DIS@
CV715 DIS@
CV717 DIS@
CV611 DIS@
CV612 DIS@
CV617 @
CV710 DIS@
CV714 DIS@
QV50
CV618 DIS@
CV713 DIS@
CV609 DIS@
CV610 DIS@
CV614 @
CV716 DIS@
CV718 @
CV616 @
CV615 DIS@
S 2N7002KW_SOT323-3
3
SB000009Q80 2 2
2
2
2
2
2
2
2
2
DIS@

N16P_GDDR5_A
Sii ze Documenttt Numberrr Rev
LA-G202P 1..0
Dattte::: Frrriiday,,, Marrrch 09,,, 2018 Sheettt 27 o ff55

5 4 3 2 1
5 4 3 2 1
LCD POWER SWITCH CAMERA POWER CIRCUIT

+3VS +LCDVDD_CONN
U202 +3VS +3VS_CMOS

D W=60mils 5 1
W=60mils D
+LCDVDD R211 1 @ 2 0_0805_5%
IN OUT
2 1
GND
1
C217 4 3 C201
1U_0201_6.3V6M EN OC
2
4.7U_0402_6.3V6M W=20mils W=20mils
SE00000UC00 EM5203AJ-20 SOT23 5P R212 1 @ 2 0_0603_5%
2
SA00008R900 1 1
@
<6> PCH_ENVDD
C202 C203
0.1U_0201_10V KX5R 10U_0603_6.3V6M
1
2 2
R202 @
100K_0402_5%
DISPLAY OFF HOT PLUG DETECT

C C
Vinafix.com
R204 1 2 0_0402_5% DISPOFF# R207 1 2 0_0402_5% EDP_HPD_R
Through EC <36> BKOFF# <6> EDP_HPD
1
2
R205 R209
100K_0402_5% 100K_0402_5%
2
1
B
eDP CONNECTOR B
+3VS_CMOS
W=20mils JEDP1
1 2 USB20_N5 <12>
3 1 2 4 USB20_P5 <12>
5 3 4 6
C206 1 EDP_AUXN_C 7 5 6
<6> EDP_AUXN 2 0.1U_0201_10V K X5R 8
EDP_AUXP_C 7 8 INVPWM <6>
<6> EDP_AUXP C207 1 2 0.1U_0201_10V K X5R 9 10 DISPOFF#
9 10 EDP_HPD_R
11 12
C208 1 EDP_TXP0_C 11 12 +LCDVDD_CONN +LEDVDD B+
2 0.1U_0201_10V K X5R 13 14
<6> EDP_TXP0 C209 1 EDP_TXN0_C 13 14
2 0.1U_0201_10V K X5R 15 16
<6> EDP_TXN0 15 16
17 17 18 18 R203 1 @ 2 0_0805_5%
C210 1 2 0.1U_0201_10V K X5R EDP_TXP1_C 19 20
<6> EDP_TXP1 C211 1 EDP_TXN1_C 21
19 20
22
W=60mils W=100mils
2 0.1U_0201_10V K X5R 21 22 1
<6> EDP_TXN1
23 23 24 24
25 25 26 26 C205 @
<30> DMIC_CLK 28
27 27 28 4.7U_0805_25V6-K
<30> DMIC_DAT 2
29 29 30 30
+3VS
@EMI@ 31 32
C216 1 2 10P_0402_50V8J GND GND
ACES_87242-3001-09_30P
SP02000NB00
EMI ME@
A A
Securiiity Clllassiiifiiicatiiion Compal Secret Data Comepal Electronics, Inc.

D
Siiize Documentt Number R ev
P
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIT CONTAIIINS Custtom 1..0
5 4 3 2 1
5 4 3 2 1
HDMI EMI
EMI
CH13 1 2 0.1U_0201_10V K X5R HDMI_CLK+_CK_C RH11 1 EMI@ 2 8.2_0402_1% HDMI_CLK+_CONN HDMI_CLK+_CONN RH12 1 EMI@ 2 150_0402_5% HDMI_CLK-_CONN
<6> HDMI_CLK+_CK
<6> HDMI_CLK-_CK CH14 1 2 0.1U_0201_10V K X5R HDMI_CLK-_CK_C RH15 1 EMI@ 2 8.2_0402_1% HDMI_CLK-_CONN HDMI_TX0+_CONN RH13 1 EMI@ 2 150_0402_5% HDMI_TX0-_CONN
D D
HDMI_TX1+_CONN RH14 1 EMI@ 2 150_0402_5% HDMI_TX1-_CONN
HDMI_TX2+_CONN RH16 1 EMI@ 2 150_0402_5% HDMI_TX2-_CONN
For HDMI
CH15 1 2 0.1U_0201_10V K X5R HDMI_TX0+_CK_C RH17 1 EMI@ 2 8.2_0402_1% HDMI_TX0+_CONN
<6> HDMI_TX0+_CK +5VS +5V_Display
CH16 1 2 0.1U_0201_10V K X5R HDMI_TX0-_CK_C RH18 1 EMI@ 2 8.2_0402_1% HDMI_TX0-_CONN UH11

<6> HDMI_TX0-_CK
3
W=40mils
OUT
1 1
IN CH11
1
@ 2 0.1U_0201_10V KX5R
CH12 GND
0.1U_0201_10V KX5R 2
2 S IC AP2330W-7 SC59 3P PW R SW
CH17 1 2 0.1U_0201_10V K X5R HDMI_TX1+_CK_C RH19 1 EMI@ 2 8.2_0402_1% HDMI_TX1+_CONN
<6> HDMI_TX1+_CK SA00004ZA00
CH18 1 2 0.1U_0201_10V K X5R HDMI_TX1-_CK_C RH20 1 EMI@ 2 8.2_0402_1% HDMI_TX1-_CONN

<6> HDMI_TX1-_CK
+3VS
CH19 1 2 0.1U_0201_10V K X5R HDMI_TX2+_CK_C RH21 1 2 8.2_0402_1% HDMI_TX2+_CONN
C <6> HDMI_TX2+_CK C
EMI@
1
CH20 1 2 0.1U_0201_10V K X5R HDMI_TX2-_CK_C RH22 1 2 8.2_0402_1% HDMI_TX2-_CONN
<6> HDMI_TX2-_CK
EMI@ RH23
1M_0402_5%
Vinafix.com
QH14
2
G
2N7002K_SOT23-3
2
JHDMI1
3 1 HDMI_DET 19
<6> TMDS_B_HPD 18 HP_DET
Near JHDMI1
D
+5V_Display +5V
1
17
HDMIDAT_R 16 DDC/CEC_GND
RH24
RPH11 20K_0402_5% HDMICLK_R 15 SDA
5 4 14 SCL
6 3 13 Reserved
2
7 2 HDMI_CLK-_CONN 12 CEC 20
8 1 11 CK- GND 21
HDMI_CLK+_CONN 10 CK_shield GND 22
470 +-5% 8P4R HDMI_TX0-_CONN 9 CK+ GND 23
8 D0- GND
HDMI_TX0+_CONN 7 D0_shield
RPH12 HDMI_TX1-_CONN 6 D0+
5 4 5 D1-
6 3 HDMI_TX1+_CONN 4 D1_shield
7 2 HDMI_TX2-_CONN 3 D1+
8 1 2 D2-
HDMI_TX2+_CONN 1 D2_shield
470 +-5% 8P4R +3VS D2+
ACON_HMRA4-AK120C
D
1
DC232003J00
2
G ME@
S QH17
3
2N7002K_SOT23-3
B B
+3VS +3VS +5V_Display

2.2K_0402_5%
%
2.2K_0402_5
%
2.2K_0402_5
%
2.2K_0402_5
1
1
RH25
RH27
RH28
RH26
QH15A
2N7002KDW 2N SC88-6 DH11 @ESD@ DH12 @ESD@ DH13 @ESD@
1 1 HDMIDAT_R
2
SB00000EO00 HDMIDAT_R HDMI_TX1-_CONN 9 10 HDMI_TX1-_CONN HDMI_TX0-_CONN HDMI_TX0-_CONN

9 10 1 1 9 10 1 1
2 HDMICLK_R
2
2
2
1 6 HDMICLK_R HDMICLK_R 2 HDMI_TX1+_CONN 8 9 HDMI_TX1+_CONN HDMI_TX0+_CONN 8 9 HDMI_TX0+_CONN

<6> HDMICLK_NB 8 9 2 2 2 2
4 4 HDMI_DET
5
HDMI_DET HDMI_TX2-_CONN 7 7 HDMI_TX2-_CONN HDMI_CLK-_CONN 7 7 HDMI_CLK-_CONN

7 7 4 4 4 4
4 3 HDMIDAT_R +5V_Display 5 5 +5V_Display HDMI_TX2+_CONN 6 6 HDMI_TX2+_CONN HDMI_CLK+_CONN 6 6 HDMI_CLK+_CONN
<6> HDMIDAT_NB 6 6 5 5 5 5
QH15B 33 3 3 3 3
2N7002KDW 2N SC88-6
SB00000EO00 8 8 8
L05ESDL5V0NA-4 SLP2510P8 ESD L05ESDL5V0NA-4 SLP2510P8 ESD L05ESDL5V0NA-4 SLP2510P8 ESD
A A
Securiiity Clllassiiifiiicatiiion Compal Secret Data Compal ElecHtronics, Inc.

Issued Date 2018/03/09 2019/03/09 Tiitl e
D
Decipii hered Date
LMA-G201P
5 4 3 2
Datte:: Friiiday,,, March 09,,, 2018 I 1
Sheett 29 o ff 55
A B C D E
ALC3240
place close audio codec
+5VS_PVDD RA2 1 @ 2 0_0805_5%
+5VS Input +3VDD_CODEC
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
0.1U_0201_10V K X5R
0.1U_0201_10V K X5R
+3VDD_CODEC
2 1 2 1 Combo Jack
2
+1.8VS
CA53
(Normal Open)
CA1
CA66
CA49
RA51
1 2 1 2 100K_0402_1%
CA40 2
4.7U_0402_6.3V6M
1
PLUG_IN_R RA23 1 2 200K_0402_1% PLUG_IN
SE00000SO00
@ 1 EMI
29
34
39
1
UA1 EXT_MIC_SLEEVE EMI@ RA42 2 1 BLM15BD121SN1D_2P SM010009U00 HGNDB
W=40mils EXT_MIC_RING2
1 Headphone W=40mils EMI@ RA31 2 1 BLM15BD121SN1D_2P SM010009U00 HGNDA 1
DVDD
PVDD1
PVDD2
CPVDD
33_0402_5% 2 1 RA52 HDA_SDIN0_AUDIO 7 HP_OUTL EMI@ RA45 1 2 47_0402_5% HPOUT_L
<9> HDA_SDIN0
4 SDATA-IN 25 HP_OUTL HP_OUTR EMI@ RA56 1 2 47_0402_5% HPOUT_R
<9> HDA_SDOUT_AUDIO SDATA-OUT HPOUT-L(PORT-I-L) 26 HP_OUTR
HPOUT-R(PORT-I-R)
PC_BEEP 11 CA68 1 2 1U_0201_6.3V6M
PCBEEP SE00000UC00 GNDA
22 For Universal Audio Jack EMI@ EMI@ EMI@ EMI@
470P_0402_50V7K
2
2
VREF 27 CPVEE CA70 1 2 1U_0201_6.3V6M
470P_0402_50V7
220P_0402_50V7
220P_0402_50V7
5 1 1
<9> HDA_BITCLK_AUDIO BCLK CPVEE SE00000UC00
10K_0402_5
10K_0402_5
@EMI@ LINE1-L CA46 1 2 1U_0201_6.3V6M
RA57
RA44
CA56
CA59
22P_0402_50V8J CA52 33_0402_5% 2 @EMI@ 1 RA50 SE00000UC00 @ @
CA65
CA50
%
1 2
12
LINE1-R CA54 1 2 1U_0201_6.3V6M
RA58 1 2 2.2K_0402_5% EXT_MIC_RING2 13 17 LINE1-R SE00000UC00 2 2
14 MIC2-L(PORT-F-L)/RING LINE1-R(PORT-C-R)
1
1
RA54 1 2 2.2K_0402_5% EXT_MIC_SLEEVE 18 LINE1-L
%
15 MIC2-R(PORT-F-R)/SLEEVE LINE1-L(PORT-C-L) 24
GNDA
CA63 2 1 2.2U_0402_6.3V6M
K
+LINE1-VREFO-R
23 MIC2-CAP LINE1-VREFO-L 12 PLUG_IN_R RA36 1 2 4.7K_0402_5% GNDA GNDA GNDA GNDA GNDA GNDA
wide 40MIL +MIC2-VREFO MIC2-VREFO HP/ LINE1-JD(JD1) External DMIC
SPK_L2+ 35 2 RA49 1 2 4.7K_0402_5%
+LINE1-VREFO-R
SPK_L1- 36 SPK-OUT-LP GPIO0/DMIC-DATA12 3 DMIC_CLK_R LA9 2 EMI@ 1 220_0402_5% DMIC_DAT <28>
SPK_R1- 37 SPK-OUT-LN GPIO1/DMIC-CLK SM01000Q500 DMIC_CLK <28> Combo Jack
EMI
SPK_R2+ 38 SPK-OUT-RN 8
SPK-OUT-RP DVDD-IO +IOVDD_CODEC
(Normal Open)
GNDA GNDA
2.2U_0402_6.3V6M1 2 CA61
1
LDO1 21 28 CA57 JHP1
LDO2 32
LDO1-CAP CBN
30
HGNDA / HGNDB , W=60mils 7
2.2U_0402_6.3V6M1 2 CA64 1U_0201_6.3V6M
LDO3 6 LDO2-CAP CBP SE00000UC00 HGNDA 3 GND
LDO3-CAP #3G/M
2
2.2U_0402_6.3V6M1 2 CA51 HPOUT_L RA63 1 @ 2 0_0402_5% HPOUT_L1 1
40 PDB RA46 1 2 0_0402_5% #1L
PDB EC_MUTE# <36>
10
VD33STB
9 DC DET
2
41 5
<9> HDA_SYNC_AUDIO
AVDD1
AVDD2
SYNC THERMAL PAD #5
AVSS1
AVSS2
RA43 @
10K_0402_5%
PLUG_IN 6
ALC3240-VA3-CG_MQFN40_5X5 #6
1
20
33
19
31
16
HPOUT_R RA64 1 @ 2 0_0402_5% HPOUT_R1 2
HGNDB 4 #2R
#4M/G
2 SINGA_2SJ3095-140111F 2
L03ESDL5V0CC3-2_SOT23-3
DA8 SCA00002900
DA9 SCA00002900
3
%
33K_0402_5
DC231711010
1
ME@
@ESD@
RA62
Vinafix.com
GNDA +3VALW
+5VDDA_CODEC +1.8VS
@ESD@
ESD@
2
RA53 1 2 0_0402_5%
Place RA53 on GNDA moat
1
CA60 1 2 1U_0201_6.3V6M GNDA
SE00000UC00
Place near Pin33
Output
SPEAK 4 ohm : 40MIL
SPEAK 8 ohm : 20MIL
JSPK1
+5VS to +5VDDA_CODEC Each Platform Power Net Support List： SPK_L1-

SPK_L2+
LA7
LA8
1
1
2
2
0_0603_5%
0_0603_5%
SPK_L1-_CONN
SPK_L2+_CONN 1 1
SPK_R1- SPK_R1-_CONN 2
LA5 1 2 0_0603_5%
SPK_R2+ SPK_R2+_CONN 3
+1.5VS +1.8VS +3VS +5VS LA6 1 2 0_0603_5% 2
4
+3VALW
1000P_0402_50V7K
1000P_0402_50V7K
+5VS +5VDDA_CODEC 3 G1
1000P_0402_50V7
1000P_0402_50V7
G2
1 1 1 1
K EMI@ CA67
K EMI@ CA47
RA48 2 1 0_0603_5% 1.5V(S0) 1.8V(S0) 3.3V(S0) 5V(S0) 3.3V(S0~S5) 4
EMI@ CA45
ACES_50278-00401-001
EMI@ CA71
Intel Broadwell V X V V V 5 SP02000RR00
0.1U_0201_10V K X5R
2 2 2 2 ME@
1
Intel Skylake X V V V V
EMI
CA58 6
CA55
3 1U_0201_6.3V6M 3
Place RA48 on GNDA moat
21
SE00000UC00
2
ESD protection needs to be placed near connector side
GNDA
Each Platform HDA Link Voltage Support (Pin 8)： DA3 @ESD@
SPK_R2+_CONN 6 3 SPK_L1-_CONN
Place near Pin20 I/O4 I/O2
3.3V 1.5V
+5VS
Intel Broadwell V (default) V
5 2
VDD GND
Intel Skylake V (default) V
SPK_R1-_CONN 4 1 SPK_L2+_CONN
I/O3 I/O1
AZC099-04S.R7G_SOT23-6
ESD
+3VS to +IOVDD_CODEC +3VS to +3VDD_CODEC PC Beep place close audio codec EMI RA65 1 @ 2 0_0402_5%
2 47K_0402_5% BEEP_N PC_BEEP

+3VS +IOVDD_CODEC +3VS +3VDD_CODEC EC Beep <36> BEEP# RA41 1 CA69 2 1 0.1U_0201_10V KX5R
SE00000SV00 RA60 1 @ 2 0_0402_5%
APU Beep <9> HDA_SPKR RA55 1 2 47K_0402_5%
J
100P_0402_50V8
CA43 @ESD@
1
1
RA61 1 @ 2 0_0402_5%
RA6 2 1 0_0603_5% RA59 2 1 0_0603_5% RA47
4 27K_0402_5% 4
0.1U_0201_10V K X5R
2 RA66 1 @ 2 0_0402_5%
1
0.1U_0201_10V K X5R
CA44
CA62
1
2
1U_0201_6.3V6M
CA48
SE00000UC00
2
2 GND GNDA
Place near Pin8 2
Place near Pin1 GNDA

HD Audio Codec - ALC3240
Datte:: Friiiday,,, March 09,,,2018 Sheett 30 o f 55
A B C D E
5 4 3 2 1
LAN Rising time 10%~90% Should >0.5mS and <100mS. GIGAOnly

( )
+LAN_VDD
+3V_LAN
W=60mils
2
+3VALW +3V_LAN
RL11 8111GLDO@
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
D
0_0603_5% D
SE00000SO00
SE00000SO00
RL18 1 @ 2 0_0603_5% 1 1 1 1
CL21 @
0.1U_0201_10V K X5R
CL2 SE00000SV00
0.1U_0201_10V K X5R
CL3 SE00000SV00
CL20 @
60mil W=60mil
1
+LAN_SROUT1.05
2 2 2 2
1
2
CL1 CL15 8111GLDO@

1U_0201_6.3V6M
SE00000UC00
0.1U_0201_10V K X5R
SE00000SV00
RJ-45 Connector
1
CL2 closeto Pin 11. JLAN1
CL3 closeto Pin32. RJ45_TX3- GND

12
8
PR4- 11
RJ45_TX3+ 7 GND
PR4+
RJ45_RX1- 6
PR2-
RJ45_TX2- 5
PR3-
+3VS RJ45_TX2+ 4 LANGAN1
CL13 1 2 27P_0402_50V8J XTLO +LAN_VDD PR3+
RJ45_RX1+ 3
PR2+
1
YL1 RJ45_TX0- 2
M
1U_0201_6.3V6
RL8 PR1-
SE00000UC00
0.1U_0201_10V K X5R
CL5 SE00000SV00
10
0.1U_0201_10V K X5R
CL6 SE00000SV00
0.1U_0201_10V K X5R
CL4 SE00000SV00
0.1U_0201_10V K X5R
CL7 SE00000SV00
1K_0402_5% 1 1 1 1 GND
RJ45_TX0+
1
1 3 1
CL8
1 3 PR1+ 9
2
NC NC GND
ISOLATE#
2
25MHZ_20PF_XRCGB25M000F2P18R0 2 2 2 2
2 4 SJ10000UH00 PS_601012-008041
DC234007L00
RL10 ME@
15K_0402_5%
LANGAN
C CL14 1 2 27P_0402_50V8J XTLI Pin3 Pin8 Pin22 Pin30 Pin22 C
Vinafix.com
+LAN_VDD +LAN_VDD
+3V_LAN LAN_MDIP0 1 17 PCIE_PRX_C_DTX_P5 CL11 1 2 0.1U_0201_10V K X5R SE00000SV00

W=40mils PCIE_PRX_DTX_P5 <12>
RL1 LAN_MDIN0 2 MDIP0 HSOP 18 PCIE_PRX_C_DTX_N5 CL12 1 2 0.1U_0201_10V K X5R SE00000SV00
+LAN_VDDREG 3 MDIN0 HSON 19 PCI_RST# PCIE_PRX_DTX_N5 <12>
1 2
LAN_MDIP1 4 AVDD10 PERSTB 20 ISOLATE# PCI_RST# <10,21,33,36>
0_0603_5% LAN_MDIN1 5 MDIP1 ISOLATEB 21 PCIE_WAKE#
LAN_MDIP2 6 MDIN1 LANWAKEB 22 PCIE_WAKE# <33,36>
LAN_MDIN2 7 MDIP2 DVDD10 23 +LAN_VDDREG
SE00000SV00
0.1U_0201_10V K X5R
1
8 MDIN2 VDDREG 24 +LAN_SROUT1.05 +3V_LAN
CL10 LAN_MDIP3 9 AVDD10 REGOUT 25 TPL1 TP@
LAN_MDIN3 10 MDIP3 LED2 26 LED1_GPIO 1 @ 2
2 11 MDIN3 LED1/GPIO 27 TPL2 TP@ RL17 10K_0402_5%
+3V_LAN
12 AVDD33 LED0 28 XTLO
<10> LANCLK_REQ# CL22 1 2 0.1U_0201_10V K X5R SE00000SV00 PCIE_PTX_C_DRX_P5 13 CLKREQB CKXTAL1 29 XTLI
<12> PCIE_PTX_DRX_P5 CL23 1 2 0.1U_0201_10V K X5R SE00000SV00 PCIE_PTX_C_DRX_N5 14 HSIP CKXTAL2 30 Reserve GPIO Pin
<12> PCIE_PTX_DRX_N5 15 HSIN AVDD10 31 2.49K_0402_1% 2 1 RL9
Close to Pin23 <10> CLK_PCIE_LAN 16 REFCLK_P RSET 32
REFCLK_N AVDD33 33 +3V_LAN
<10> CLK_PCIE_LAN#
GND
UL2
SA000065Y00
S IC RTL8106E-CG QFN 32P E-LAN CTRL
UL2 UL2 RTL8111GS-CG_QFN32_4X4

SA00005O700 SA00005O700
S IC RTL8111GS-CG QFN 32P E-LAN CTRL S IC RTL8111GS-CG QFN 32P E-LAN CTRL
B
8111GLDO@ @ B
EMI ESD EMI

TL1 RL19 CL19
RL4 1 2 0_0402_5% +V_DAC 1 24 MCT 1 2 12
DL2 TCT1 MCT1
RL5 1 2 0_0402_5% LAN_MDIN1 1
I/O1 I/O3
4 LAN_MDIP0
EMI LAN_MDIP3
LAN_MDIN3
2
TD1+ MX1+
23 RJ45_TX3+
RJ45_TX3-
75_0805_5%
EMI@
1000P_0603_50V8J
EMI@
3 22
EMI@ CL18 TD1- MX1-
LANGAN 2 5 1 2 +V_DAC 4 21 MCT 2 1
GND VDD TCT2 MCT2 LANGAN
0.01U_0402_16V7K LAN_MDIP2 5 20 RJ45_TX2+ DL3
RL6 1 2 0_0402_5% TD2 MX2+ BS4200N-C-LV_SMB-F2
LAN_MDIP1 3 6 LAN_MDIN0 LAN_MDIN2 6 19 RJ45_TX2- @EMI@
RL7 1 2 0_0402_5% I/O2 I/O4 TD2- MX2-
+V_DAC 7 18 MCT
AZC099-04S.R7G_SOT23-6
TCT3 MCT3
SC300001G00
LAN_MDIP1 8 17 RJ45_RX1+
@ESD@ TD3+ MX3+
LANGAN1
LAN_MDIN1 9 16 RJ45_RX1-
TD3- MX3-
DL1 +V_DAC 10 15 MCT
LAN_MDIN3 1 4 LAN_MDIP2 TCT4 MCT4
I/O1 I/O3 LAN_MDIP0 11 14 RJ45_TX0+
TD4+ MX4+
LAN_MDIN0 12 13 RJ45_TX0-
2 5 TD4- MX4-
GND VDD TL1
A A
S X'FORM_ NS892404 ETHERNET 10/100 NS892407
SP050003P00 @
LAN_MDIP3 3 6 LAN_MDIN2
I/O2 I/O4 TL1
AZC099-04S.R7G_SOT23-6 S X'FORM_ NS892407 1G
SC300001G00 SP050006800
@ESD@ DL1 Only For GIGA 8111GLDO@

Issued Date 2018/03/09 Deciiiphered Date 2019/03/09 Tiiitttllle
LAN RTL8106E
TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIVIIISIIION OF R&D DEPARTMENT Siiize Documenttt Number Rev
EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IINC...NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIT CONTAIIINS C 1..0
5 4 3 2 1
5 4 3 2 1
CARD READER
D D
Card Reader IC
Main
UR1
S IC RTS5146-GR QFN 24P USB2.0 CARD READ
SA0000AW900
Second UR1
S IC GL835-OGYL3 QFN 24P CARD READER
SA0000AVM10
GEN_CR@
+Card_3V3
+3VS
UR1
C RR2 1 @ 2 0_0402_5% USB20_CR_N6 3 1 CR5 2 1 1U_0201_6.3V6M C
<12> USB20_N6 USB20_CR_P6 DM AV18
RR3 1 @ 2 0_0402_5% 4 7 SE00000UC00
<12> USB20_P6 DP CARD_3V3
SD_CD_N 10 16 SDREG CR4 2 1 1U_0201_6.3V6M
15 SD_CD# SDREG SE00000UC00
MS_INS# SD_WP
*Genesys Can Un-Pop This One. 11
9 SP1 SD_D0
Vinafix.com
13
SD_D1 12 GPIO SP2 14
1 1
CR1 CR2 SD_DAT1 SP3 17
RR1 2 1 6.19K_0402_1% RREF 2 SP4 18 SD_CLK_R RR5 1 @ 2 0_0402_5% SD_CLK
0.1U_0201_10V K X5R 4.7U_0402_6.3V6M
SE00000SO00 5 RREF SP5 19
2 2 6 3V3_IN1 SP6 20 SD_CMD
+3VS 1
8 3V3_IN2 SP7 21 @EMI@
3V3_IN3 SP8 22 SD_D3 CR3
24 SP9 23 SD_D2 5P_0402_50V8C
48MHz_In SP10 2
25
GND
RTS5146-GR_ QFN24_4X4
SA0000AW900
@
JSD1
SD_D3 1
+Card_3V3 CD/DAT3
SD_CMD 2 CMD
B B
3 VSS1
4 VDD
SD_CLK 5 CLK
1 1
CR7 CR6 6 VSS2
0.1U_0201_10V K X5R 4.7U_0402_6.3V6M
SE00000SO00 SD_D0 7
2 2 DAT0
SD_D1 8 12
DAT1 G1
SD_D2 9 13
DAT2 G2
SD_CD_N 10 14
CD G3
Place Close to Connector SD_WP 11
WP G4
15
DEREN_43-42095-01111RHF-R
SP07001BB00
ME@
GNDA
A A

2018/03/09 2019/03/09
Issued Date Deciiiphered Date Tiiitttllle
Card Reader
5 4 3 2 1
A B C D E
NGFF - WLAN / BT (E- KEY)

1 1
+3VS +3VS_W LAN
R242 1 @ 2 0_0805_5%
1 1 1 1
C243 C244 C245 C246
4.7U_0402_6.3V6M 0.1U_0201_10V KX5R 22U_0603_6.3V6M 22U_0603_6.3V6M
@ @ @
2 2 2 2
2 2
+3VS_W LAN
Vinafix.com
JW LAN1
1 2
3 GND 3.3VAUX 4
<12> USB20_P7 5 USB_D+ 3.3VAUX 6
BT <12> USB20_N7 7 USB_D- LED1# 8
9 GND PCM_CLK 10
11 SIDO_CLK PCM_SYNC 12
13 SDIO_CMD PCM_IN 14
15 SDO_DAT0 PCM_OUT 16
17 SDO_DAT1 LED2# 18
SDO_DAT2 GND 20
19
21 SDO_DAT3 UART_W AKE# 22 WL_UART_RX
UART for Intel Debug
23 SDIO_W AKE# UART_RX
SDIO_RESET# R254 1 2 @ 0_0402_5%
UART0_RX <11>
R253 1 2 @ 0_0402_5%
UART0_TX <11>
32 WL_UART_TX
33 UART_TX 34
CC102 1 2 0.1U_0201_10V K X5R PCIE_PTX_C_DRX_P6 35 GND UART_CTS 36
<12> PCIE_PTX_DRX_P6 2 0.1U_0201_10V K X5R PCIE_PTX_C_DRX_N6 37 PETP0 UART_RTS 38
CC103 1 R243 1 2 0_0402_5%
<12> PCIE_PTX_DRX_N6 PETN0 RESERVED 40 EC_TX <36>
39 R244 1 2 0_0402_5%
GND RESERVED 42 EC_RX <36>
41
<12> PCIE_PRX_DTX_P6 43 PERP0 RESERVED 44
WLAN <12> PCIE_PRX_DTX_N6
45 PERN0 COEX3 46
47 GND COEX2 48
<10> CLK_PCIE_WLAN 49 REFCLKP0 COEX1 50 SUSCLK_R R245 1 2 0_0402_5%
<10> CLK_PCIE_WLAN# REFCLKN0 SUSCLK 52 WL_RST# SUSCLK <10>
51
R246 1 2 0_0402_5% WLANCLK_REQ#_R 53 GND PERST0# 54 BT_DISABLE_R R247 1 2 0_0402_5%
<10> WLANCLK_REQ# W AKE#_R CLKEQ0# W _DISABLE2# 56 WLBT_OFF# <11>
R249 1 @ 2 0_0402_5% 55 R248 1 2 0_0402_5%
<31,36> PCIE_WAKE# PEW AKE0# W _DISABLE1# 58 WL_OFF# <12>
3 57 3
59 GND I2C_DATA 60
61 RSRVD/PETP1 I2C_CLK 62
63 RSRVD/PETN1 ALERT 64 Note: The real behavior of BT_DISABLE are
65 GND RESERVED 66 BT_DISABLE=LOW, BT=OFF
RSRVD/PERP1 RESERVED 68
67
RSRVD/PERN1 RESERVED 70
BT_DISABLE=HIGH, BT=ON
69
71 GND RESERVED 72
RESERVED 3.3VAUX 74
73
75 RESERVED 3.3VAUX
GND
77 76
MTG77 MTG76
LOTES_APCI0128-P005A
SP070011H00
ME@
2
R251 R252 WL_RST# R250 1 2 0_0402_5% PCI_RST# <10,21,31,36>
100K_0402_5% 100K_0402_5%
1 @
4 4
2018/03/09
Compal Secret Data
2019/03/09
ComNpal Electronics, Inc.
Tiitl e
Issued Date Decipii hered Date
G
F
A B C D
Datte::
F
Friiiday,,, March 0 9, 2018
E
Sheett 33 o ff 55
A B C D E F G H
HDD FFC Connector to Sub Board

1 1
+5VS +5V_HDD
R233 1 @ 2 0_0805_5% 1000P_0402_50V7K
0.1U_0201_10V K X5R
M
10U_0603_6.3V6
1 1 1
C237
C232
C238
@
2 2 2
Place Near Connector JHDD1

1
2 +5V_HDD 1 2
2
3 2
4 3
C236 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_P0 5 4
<12> SATA_PRX_DTX_P0 C235 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_N0 6 5
<12> SATA_PRX_DTX_N0 6
Vinafix.com
7
C234 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_N0 8 7
<12> SATA_PTX_DRX_N0 SATA_PTX_C_DRX_P0 8
C233 1 2 0.01U_0402_16V7K 9 11
<12> SATA_PTX_DRX_P0 9 G11 12
10
10 G12
ACES_51530-01001-P01
SP010025K00
ME@
ESD C239
+5V_HDD 12
0.1U_0201_10V KX5R
@ESD@
3 3
4 4
Securiiity Clllassiiifiiicatiiion Compal Secret Data ComHpal Electronics, Inc.

D
D
A B C D E F G H
A B C D E F G H
ODD Connector (14" Only)
Place on TOP
1
JODD1 1
1
SATA_PTX_DRX_P1 C2146 1 2 0.01U_0402_16V7K14@ SATA_PTX_C_DRX_P1 2 GND
<12> SATA_PTX_DRX_P1 SATA_PTX_DRX_N1 SATA_PTX_C_DRX_N1 A+
<12> SATA_PTX_DRX_N1 C2145 1 2 0.01U_0402_16V7K14@ 3
4 A-
SATA_PRX_DTX_N1 C2143 1 2 0.01U_0402_16V7K14@ SATA_PRX_C_DTX_N1 5 GND
<12> SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 C2144 1 2 SATA_PRX_C_DTX_P1 6 B-
0.01U_0402_16V7K14@
<12> SATA_PRX_DTX_P1 7 B+
GND
HDD_ODD_DETECT 8
<11> HDD_ODD_DETECT 9 DP
+5V_ODD
10 +5V
11 +5V
12 MD 15
13 GND GND 14
GND GND
ALLTO_C185S1-113H9-L
SP011312061
ME@
ODD FFC Connector to Sub Board (15" Only) 2
Vinafix.com SATA_PTX_DRX_P1
SATA_PTX_DRX_N1
SATA_PRX_DTX_N1
SATA_PRX_DTX_P1
HDD_ODD_DETECT
+5V_ODD
1
2
3
4
5
6
7
8
9
10
JODD2
1
2
3
4
5
6
7
8
9
10
G11
G12
11
12
ACES_51530-01001-P01
SP010025K00
ME@
3 3
ODD MISC.
+5VS +5V_ODD
R420 1 @ 2 0_0805_5%
K
1000P_0402_50V7
0.1U_0201_10V K X5R
M
10U_0603_6.3V6
1 1 1
C2148
C2147
@ 14@ 14@ C2149

2 2 2
4 4

2018/03/09 2019/03/09 Tiitl e
Issued Date Decipii hered Date ODD
A B C D E F G H
+3VL +3VL +5VALW
L101
1 2
+3VALW _EC +EC_VCCA +3VALW_EC USB_EN#
BLM15AX601SN1D _2P R102 1 @ 2 0_0603_5% 1 R105 1 2 10K_0402_5%
SM01000KL00 C101
1 1 100P_0402_50V8J
C106 C107 1 1 1 1 @
VCIN1_BATT_TEMP
0.1U_0201_10V K X5R
C102
0.1U_0201_10V K X5R
C103
K
1000P_0402_50V7
C104
K
1000P_0402_50V7
C105
0.1U_0201_10V K X5R 1000P_0402_50V7K 2 C111 1 2 100P_0402_50V8J
@
2 2 VCIN1_AC_IN C112 1 2 100P_0402_50V8J
L102 2 2 @2 @2 +EC_VCCA
1 2 ECAGND R110 1 @ 2 4.7K_0402_5%
BLM15AX601SN1D _2P
SM01000KL00
111
125
22
33
96
67
9
ECAGND U11
VCC0
V CC_LPC
VCC
VCC
VCC
VCC
AVCC
1 21 VCCST_PWRGD
2 GATEA20/GPIO00 EC_VCCST_PG/GPIO0F 23 VCCST_PWRGD <10>
3 KBRST#/GPIO01 BEEP#/GPIO10 26 BEEP# <30>
<8> SERIRQ 4 SERIRQ EC_FAN_PWM1 <39>
PW M Output EC_FAN_PW M/GPIO12 27 EC_VCIN1_AC_BYPASS_R
EMI <8> LPC_FRAME#

<8> LPC_AD3
<8> LPC_AD2
5
7
8
LPC_FRAME#
LPC_AD3
LPC_AD2
AC_OFF/GPIO13
63
<8> LPC_AD1 10 LPC_AD1 VCIN1_BATT_TEMP/AD0/GPIO38 64 VCIN1_BATT_TEMP <42,43>
@EMI@ @EMI@
<8> LPC_AD0 LPC_ADL0 PC & MISC VCIN1_BATT_DROP/AD1/GPIO39 65 VCIN1_BATT_DROP <44>
C108 2 1 22P_0402_50V8J R103 2 1 10_0402_1% ADP_I <43>
12 ADP_I/AD2/GPIO3A 66
<8> CLK_LPC_EC AD Input CUST_TEMP3 <39>
PCI_RST# 13 CLK_PCI_EC AD_BID/AD3/GPIO3B 75
<10,21,31,33> PCI_RST# EC_RST# 37 PCIRST#/GPIO05 AD4/GPIO42 76
+3VALW _EC R104 1 @ 2 47K_0402_5%
20 EC_RST# AD5/GPIO43 CUST_TEMP2 <39>
<6,10> EC_SCI# 1 @ 2 PM_CLKRUN#_R 38 EC_SCI#/GPIO0E +3VALW
2 <8> PM_CLKRUN# CLKRUN#/GPIO1D
0.1U_0201_10V K X5R
C109
R428 0_0402_5%
68 NOVO#
DA0/GPIO3C NOVO# <39>
DA Output 70 TP_DISABLE# <38>
1 55 EN_DFAN1/DA1/GPIO3D 71
@
KSI0
56 KSI0/GPIO30 DA2/GPIO3E 72 USB_EN# DGPU_PWR_EN <11,26>
KSI1
KSI1/GPIO31 DA3/GPIO3F USB_EN# <37>
KSI2 57
KSI3 58 KSI2/GPIO32 83 LID_SW # R273 1 @ 2 100K_0402_5%
KSI4 59 KSI3/GPIO33 EC_MUTE#/PSCLK1/GPIO4A 84
60 KSI4/GPIO34 USB_EN#/PSDAT1/GPIO4B 85
KSI5
KSI6 61 KSI5/GPIO35 PSCLK2/GPIO4C 86
62 KSI6/GPIO36 PS2 Interface PSDAT2/GPIO4D 87
KSI7
KSO0 39 KSI7/GPIO37 TP_CLK/GPIO4E 88 EC_MUTE# R107 1 @ 2 10K_0402_5%
KSO0/GPIO20 TP_DATA/GPIO4F GPU_PROHOT# <24>
KSO1 40
KSO[0..17] KSO2 41 KSO1/GPIO21
<38> KSO[0..17] KSO3 42 KSO2/GPIO22 97 PCIE_WAKE# R117 2 1 1K_0402_5%
KSI[0..7] 43 KSO3/GPIO23 ENKBL/GPXIOA00 98 ENBKL <6>
KSO4
<38> KSI[0..7] KSO4/GPIO24 W OL_EN/GPXIOA01 99 SYS_PWROK <10>
KSO5 44 Int. K/B
45 KSO5/GPIO25 ME_EN/GPXIOA02 109 ME_EN <9>
ESD 1
0.1U_0201_10V K X5R
C116 @ESD@
KSO6
KSO7 46 KSO6/GPIO26 Matrix VCIN0_PH1/GPXIOD00 VCIN0_PH1 <42>
KSO7/GPIO27
Vinafix.com
KSO8 47 SPI Device Interface
KSO9 48 KSO8/GPIO28 119 2
49 KSO9/GPIO29 MISO/GPIO5B 120 EC_SPI_MISO <8>
KSO10
50 KSO10/GPIO2A MOSI/GPIO5C 126 EC_SPI_MOSI <8>
KSO11 SPI FlashROM
KSO11/GPIO2B SPICLK/GPIO58 128 EC_SPI_CLK <8>
KSO12 51
KSO12/GPIO2C SPICS#/GPIO5A EC_SPI_CS0# <8>
KSO13 52
KSO14 53 KSO13/GPIO2D
KSO15 54 KSO14/GPIO2E 73
81 KSO15/GPIO2F EC_CIR_RX/AD6/GPIO40 74 CUST_TEMP1 <39>
KSO16
KSO17 82 KSO16/GPIO48 SYS_PW ROK/AD7/GPIO41 89 EC_MUTE# +3VL
+3VL KSO17/GPIO49 GPIO50 90 BATT_CHG_LED# EC_MUTE# <30>
BATT_CHG_LED#/GPIO52 BATT_CHG_LED# <39>
91
EC_SMB_CK1 EC_SMB_CK1 CAPS_LED#/GPIO53 CAPS_LED# <38>
R108 1 2 2.2K_0402_5% 77 GPIO 92 NOVO# R1259 1 2 100K_0402_5%
PWR_LED# <38,39>
R109 1 2 2.2K_0402_5% EC_SMB_DA1 <42,43> EC_SMB_CK1 EC_SMB_DA1 78 EC_SMB_CLK1/GPIO44 PW R_LED#/GPIO54 93 BATT_LOW_LED#
<42,43> EC_SMB_DA1 BATT_LOW_LED# <39>
79 EC_SMB_DAT1/GPIO45 BATT_LOW_LED#/GPIO55 95 SYSON
<8,24> EC_SMB_CK2 SYSON <13,45>
80 EC_SMB_CLK2/GPIO46 SYSON/GPIO56 121
<8,24> EC_SMB_DA2 EC_SMB_DAT2/GPIO47 VR_ON/GPIO57 VR_ON <48>
127 AC_PRESENT <10,24> ON/OFF# R170 1 2 100K_0402_5%
DPW ROK_EC/GPIO59
SM Bus
6 100
<10> PM_SLP_S3# 14 PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 101 EC_RSMRST# <10>
15 GPIO07 GPXIOA04 102 3V/5VALW_PG <40,44,46>
<10> EC_CLEAR_CMOS# 16 GPIO08 VCIN1_ADP_PROCHOT/GPXIOA05 103 VCOUT1_PROCHOT# SUSP# R129 1 2 100K_0402_5%
17 GPIO0A VCOUT1_PROCHOT#/GPXIOA06 104 VCOUT1_PROCHOT# <43>
+3VS 18 GPIO0B VCOUT0_MAIN_PW R_ON/GPXIOA07 105 VCOUT0_MAIN_PWR_ON <44>
19 GPIO0C BKOFF#/GPXIOA08 106 BKOFF# <28>
AC_PRESENT/GPIO0D GPIO GPO GPXIOA09
25 107
R118 1 2 10K_0402_5% EC_FAN_SPEED1 EC_FAN_SPEED1 28 PW M2/GPIO11 PCH_PW R_EN/GPXIOA10 108 EC_PCIE_WAKE# 1 2 PCIE_WAKE#
<39> EC_FAN_SPEED1 VCIN1_AC_IN_R 29 FAN_SPEED1/GPIO14 PW R_VCCST_PG/GPXIOA11 PCIE_WAKE# <31,33>
R1260 0_0402_5%
30 FANFB1/GPIO15
<33> EC_TX 31 EC_TX/GPIO16 EC_VCIN1_AC_BYPASS
110
<33> EC_RX PCH_PWROK EC_RX/GPIO17 VCIN1_AC_IN/GPXIOD01
32 112
<10> PCH_PWROK PCH_PW ROK/GPIO18 EC_ON/GPXIOD02 EC_ON <44>
34 114 ON/OFF#
VR_PW RGD SUSP_LED#/GPIO19 ON/OFF#/GPXIOD03 ON/OFF# <38,40>
36 GPI 115
<48> VR_PWRGD NUM_LED#/GPIO1A LID_SW #/GPXIOD04 LID_SW# <38> VCOUT1_PROCHOT#
116 SUSP# R111 1 2 0_0402_5%
SUSP#/GPXIOD05 SUSP# <13,40,45>
117
GPXIOD06 118 PECI 1 2 NUM_LED# <38>
PBTN_OUT# PECI/GPXIOD07 H_PECI <6>
122 R114 43_0402_1% R112 1 2 0_0402_5% H_PROCHOT# <6>
+3VALW <10> PBTN_OUT# 123 PBTN_OUT#/GPIO5D VCC_IO2 <48> VR_HOT#
124 1 @ 2
<10,43,46> PM_SLP_S4# PM_SLP_S4#/GPIO5E V18R/VCC_IO2 +3VALW _EC
R115 0_0402_5% 1
AGND
1
GND
GND
GND
GND
GND
R106 1 @ 2 10K_0402_5% PBTN_OUT# C113 ESD@

C114
4.7U_0402_6.3V6M 100P_0402_50V8J
KB9022QD_LQFP128_14X14 2
11
24
35
94
2
113
SA000075S30
ECAGND 69
ESD
ESD
R425 1 @ 2 0_0402_5% EC_VCIN1_AC_BYPASS
<43> VCIN1_AC_IN pin110 3V/5VALW_PG PCI_RST# PCH_PWROK VR_PW RGD VCCST_PWRGD BATT_CHG_LED# BATT_LOW_LED# SYSON
VCIN1_AC_IN_R 1 1 1
100P_0402_50V8J
C120 @ESD@
ESD@
0.1U_0201_10V K X5R
C110
J
100P_0402_50V8
C121 ESD@
J
100P_0402_50V8
C117 @ESD@
0.1U_0201_10V K X5R
C115 ESD@
ESD@
0.1U_0201_10V K X5R
C122 SE00000SV00
J
100P_0402_50V8
C118 @ESD@
R426 1 @ 2 0_0402_5%
J
100P_0402_50V8
C119 ESD@
1 1 1 1 1
pin29
EC_VCIN1_AC_BYPASS_R R427 1 @ 2 0_0402_5% EC_VCIN1_AC_BYPASS
pin27 pin110 SE00000SV00 2 2 2
2 2 2 2 2
Securiiity Clllassiiifiiicatiiion Compal Secret Data ComEpal Electronics, Inc.

C
Datte::
K
Friiiday,,, March 0 9, 2018 Sheett 36 o ff55
B
5 4 3 2 1
USB 3.0 (PORT 2)

Intel_PCH_USB2.0
D
L301 EMI@ D
1 2 U2DN2
<12> USB20_N2 1 2
4 3 U2DP2
<12> USB20_P2 4 3
DLM0NSN900HY2D_4P
SM070005U00 +USB3_VCCA
W=80mils
Intel_PCH_USB3.0
D301 ESD@ D302 ESD@ JUSB1
USB3_RX2_N 9 10 1 1 USB3_RX2_N U2DP2 3 6 U3TXDP2_L 9
I/O2 I/O4 1 STDA_SSTX+
USB3_RX2_P 8 9 VBUS
2 2 USB3_RX2_P U3TXDN2_L 8
USB3_RX2_N U2DP2 3 STDA_SSTX-
<12> USB3_RX2_N U3TXDN2_L 7 7 U3TXDN2_L D+
4 4 2 5
+USB3_VCCA
4
GND VDD U2DN2 2 GND_1
USB3_RX2_P U3TXDP2_L 6 6 U3TXDP2_L USB3_RX2_P D-
5 5 6
STDA_SSRX+
<12> USB3_RX2_P 7
USB3_RX2_N GND_2
3 3 1 4 U2DN2 5
STDA_SSRX-
I/O1 I/O3
8 10
L30ESDL5V0C6-4_SOT23-6 GND1
11
SC300004W00 GND2
L05ESDL5V0NA-4 SLP2510P8 ESD 12
GND3
SC300002C00 13
GND4
ACON_TARAN-9R1391
DC23300EQ00
C301
0.1U_0201_10V KX5R ME@
1 2 U3TXDN2_L
<12> USB3_TX2_N
C302
0.1U_0201_10V KX5R
C 1 2 U3TXDP2_L C
<12> USB3_TX2_P
Vinafix.com
Place TX AC coupling Cap (C172,173). Close to connector
USB 3.0 (PORT 3) USB3_RX3_N

D304
9 10
ESD@
1 1 USB3_RX3_N USB 3.0 MISC.
USB3_RX3_P 8 9 2 2 USB3_RX3_P
U3TXDN3_L U3TXDN3_L
7 7 4 4
U3TXDP3_L U3TXDP3_L
6 6 5 5
Intel_PCH_USB2.0 3 3
L304 EMI@ L05ESDL5V0NA-4 SLP2510P8 ESD

1 2 U2DN3 SC300002C00
<12> USB20_N3 1 2
B B
4 3 U2DP3
<12> USB20_P3 4 3 +5VALW +USB3_VCCA
DLM0NSN900HY2D_4P 2A/Active Low
SM070005U00 W=80mils
D305 ESD@ W=80mils U301
U2DP3 3 6 1
I/O2 I/O4 5 OUT
IN 2
USB_EN# 4 GND R301
Intel_PCH_USB3.0 2 5
<36> USB_EN# EN 3 USB_OC1#_U301 1 2
GND VDD +USB3_VCCA 1 OCB USB_OC1# <12>
0_0402_5%
C305 S IC G524B2T11U SOT-23 5P POWER SWITCH @
0.1U_0201_10V KX5R SA00007BW00
USB3_RX3_N 1 4 2
K
470P_0402_50V7
U2DN3 1
<12> USB3_RX3_N I/O1 I/O3
220U_6.3V_M
1
+
C304
C303
USB3_RX3_P L30ESDL5V0C6-4_SOT23-6
<12> USB3_RX3_P SC300004W00 @
2 2
+USB3_VCCA
W=80mils
C2150
0.1U_0201_10V K X5R JUSB2
1 2 U3TXDN3_L U3TXDP3_L 9
<12> USB3_TX3_N STDA_SSTX+
C2151 1
0.1U_0201_10V K X5R U3TXDN3_L 8 VBUS
1 2 U3TXDP3_L U2DP3 3 STDA_SSTX-
<12> USB3_TX3_P D+
A 4 A
U2DN3 2 GND_1
USB3_RX3_P 6 D-
7 STDA_SSRX+
USB3_RX3_N GND_2
5
STDA_SSRX-
10
GND1
11
Place TX AC coupling Cap (C2150,2151). Close to connector 12
GND2
GND3
13
GND4 Security Classification Compal Secret Data
US
ACON_TARAN-9R1391 2018/03/09 2019/03/09 Tiitl e
t
DC23300EQ00
ME@ THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONICS,,, IIINC.. AND CONTAIIINS CONFIIIDENTIIIAL AND
TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIVIIISIIION OF R&D Siiize Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONICS,,, IINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIT CONTAIIINS Custtom 1..0
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IIINC.. LA-G202P
Datte:: Friiiday,,, March 09,, 2018
Sheett 37 o ff 55
5 4 3 2
B3 1
KEYBOARD
R278 2 @ 1 0_0402_5% JKB1
+5VALW PW R_CAPS_LED
+3VALW R271 2 @ 1 0_0402_5% 1
CAPS_LED# R274 1 2 470_0402_5% CAPS_LED#_R 2 1
<36> CAPS_LED#
KSO15 3 2
4 3
0.1U_0201_10V K X5R
KSO10
KSO11 5 4
1 KSO14 6 5
7 6
@ESD@
C271
KSO13
KSO12 8 7
KSO3 9 8
2 KSO6 10 9
KSO8 11 10
KSO7 12 11
KSO4 13 12
KSI[0..7] KSO2 14 13
KSI[0..7] <36> 15 14
KSI0
KSO[0..17] KSO1 16 15
KSO[0..17] <36>
KSO5 17 16
KSI3 18 17
KSI2 19 18
KSO0 20 19
KSI5 21 20
KSI4 22 21
KSO9 23 22
KSI6 24 23
KSI7 25 24
KSI1 26 25
KSO16 R275 1 @ 2 0_0402_5% KSO16_R 27 26 33
KSO17 R276 1 @ 2 0_0402_5% KSO17_R 28 27 GND 34
R277 1 15@ 2 470_0402_5% NUM_LED#_R 29 28 GND
<36> NUM_LED# 30 29
R272 1 2 470_0402_5%
<36,39> PWR_LED#
R283 1 @ 2 0_0402_5% 31 30
<36,40> ON/OFF#
32 31
32
2
1 1 JXT_FP257H-032S10M
D303 SP01002FA00
C272 C275 L03ESDL5V0CC3-2_SOT23-3 ME@
0.1U_0201_10V K X5R 2 0.1U_0201_10V K X5R 2 SCA00002900
@ESD@ @ESD@ ESD@
1
HALL SENSOR
Vinafix.com TOUCH PAD
+3VS
+3VS
R279 1 @ 2 0_0805_5%
0.1U_0201_10V K X5R
C280
1
R280 @
+3VALW 4.7K_0402_5%
2
JTP1
2
TP_VCC 6 8
5 6 GND 7
1 <11> I2C0_SCL_TP
VDD
4 5 GND 4
<11> I2C0_SDA_TP 3
C2152 3
LID_SW # TP_INT# 2
0.1U_0201_10V K X5R 3 2
2 OUTPUT LID_SW# <36> <11> TP_INT# 1
1
<36> TP_DISABLE#
GND
1 ACES_51522-00601-001
C2153 SP01001A800
U282 10P_0402_50V8J ME@
1 1
ESD
1
APX8132 SOT-23F 3P
SA00008K800 2 C281 C282
100P_0402_50V8J 100P_0402_50V8J
2
@2 2@
D281
PSOT24C_SOT23-3
1
@ESD@
Securiiity Clllassiiifiiicatiiion Compal Secret Data ComKpal Electronics, Inc.

B
Date:
/
Friiiday,,, March 09,,, 2018 Sheet 38 o f 55
5 4 3 2 1
THERMISTOR
CHARGER +EC_VCCA VRAM +EC_VCCA CPU CHOKE +EC_VCCA
D D
1
R364 R365 R368
16.5K_0402_1% 16.5K_0402_1% 16.5K_0402_1%
@ @ @
2
<36> CUST_TEMP1 <36> CUST_TEMP2 <36> CUST_TEMP3
1
R366 R367 R369
100K +-1% 0402 B25/50 4250K 100K +-1% 0402 B25/50 4250K 100K +-1% 0402 B25/50 4250K
SL200002H00 SL200002H00 SL200002H00
@ @ @
2
ECAGND ECAGND ECAGND
C C
FAN LED
Vinafix.com
JFAN1
+5VS 1
1
<36> EC_FAN_PWM1
2
3 2 Power ( White )
<36> EC_FAN_SPEED1 +5VS_FAN 3
1@2 4 LED2
4
R371 5 PWR_LED# 1 2 R377 1 2 412_0402_1%
0_0603_5% 6 GND1 <36,38> PWR_LED# +5VALW
2 GND2
C371
10U_0603_6.3V6M LTW -C193TS5-C_W HITE
ACES_50271-0040N-001
SC50000BB10
1 SP02000TS00
ME@
B B
Battery ( White )
LED3
BATT_CHG_LED# 1 2 R376 1 2 200_0402_1%
<36> BATT_CHG_LED# +VL
NOVO BUTTON
LTW -C193TS5-C_W HITE
SC50000BB10
SW 1
SN100006A10
S TACT SW TAFG1-12WQR4 SPST DIP H3.3 3P
Battery ( Amber )
LED4
1
BATT_LOW_LED# 1 2 R378 1 2 200_0402_1%
2 NOVO#
3
NOVO# <36> <36> BATT_LOW_LED#
A +VL
G
G
G
G
LTST-C191KFKT-2CA_ORANGE
7
6
5
4
ESD SC500005930
3
D1
A SCA00002900 A
ESD@
1

FAN / Thermal / LED / NOVO
5 4 3 2 1
A B C D E
DC to DC
1 1
+3VALW +3VS
J4
+VL
2
2 1
1
RF By-Pass / Cross Moat Caps
0.1U_0201_10V K X5R
10U_0603_6.3V6M
JUMP_43X79
10U_0603_6.3V6M
0.1U_0201_10V K X5R
1 1
+3VALW to +3VS 1 1
C381
C382
C384
C385
@ @
2 2 2 2 +3VS +3VS +5VALW +3VS +VCCGT +VGA_CORE
U381
+3VALW_3VS
0.1U_0201_10V K X5R
0.1U_0201_10V K X5R
1 14
0.1U_0201_10V K X5R
0.1U_0201_10V K X5R
0.1U_0201_10V K X5R
0.1U_0201_10V K X5R
2 VIN1 VOUT1 13
VIN1 VOUT1 2 2 2 2 2 2
@RF@
@RF@
CC99
@RF@
@RF@
@RF@
CC125
@RF@
CC53
CC100
CC105
CC121
3 12 C383 1 2 S CER CAP 1000P 50V K X7R 0402
ON1 CT1 SE074102K80
4 11 1 1 1 1 1 1
<13,36,45> SUSP# VBIAS GND +5VS
5 10 C386 1 2 S CER CAP 2200P 25V K X7R 0402
+5VALW ON2 CT2 SE075222K80 J5
6 9 +5VALW_5VS 2 1
VIN2 VOUT2 2 1
10U_0603_6.3V6M
7 8
VIN2 VOUT2
10U_0603_6.3V6M
0.1U_0201_10V K X5R
JUMP_43X79 1 1
0.1U_0201_10V K X5R
C389
C390
1 1 15
GPAD
C387
C388
@
@ S IC JW7110DFNC#TRPBF DFN14 DUAL LOAD SW
SA0000BEL00 2 2
2 2
+5VALW to +5VS
2 2
DISCHARGE CIRCUIT
For +1.8VALW Discharge

Vinafix.com MISC.
CPU
H1
HOLEA
H2
HOLEA
H3
HOLEA
VGA
H4
HOLEA
H5
HOLEA
LAN
H6
HOLEA
BATTERY
H7
HOLEA
ON/OFF# SHORT PADS
@
JP3 2 1 ON/OFF#
SHORT PADS
ON/OFF# <36,38>
1
1
1
H_3P3 H_3P3 H_3P3 H_3P3 H_3P3 H_2P5 H_2P5 @
3 JP4 2 1 ON/OFF# 3
+5VALW +1.8VALW
SHORT PADS
1
R401 @ R402 @
22_0603_1%
DC IN FAN
100K_0402_1%
2
2
H8 H9 H10 H11
HOLEA HOLEA HOLEA HOLEA
3
D FD1 FD2 FD3 FD4

1.8VALW_PWR_EN# 5
G
1
1
1
S H_3P2N
LASER BARCODE
4
@ Q401B
2N7002KDW _SOT363-6 H_2P5 H_2P5 H_2P5
CODE1 @ CODE2 @
6
D
2
<36,44,46> 3V/5VALW_PG G
S
MISC.
1
@ Q401A BARCODE_8X8 BARCODE_12X4

2N7002KDW _SOT363-6
H12 H13 H14 H15
HOLEA HOLEA HOLEA HOLEA
CODE3 @ CODE4 @
1
1
1
4 H_3P5X2P5N 4
H_2P5 H_2P5 H_3P2

BARCODE_20X4 BARCODE_10X10

DC to DC / Discharge / MISC
A B C D E
5 4 3 2 1
EMI@ PL101
5A_Z80_0805_2P
SINGA_2DC3169-000111F PF101 1 2 +19V_VIN
7A_32VDC_0437007.W RML
1 APDIN 1 2 +19V_APDIN
PIN+ 2 EMI@ PL102
SPRING- 5 5A_Z80_0805_2P
SPRING- 3 1 2
1000P_0402_50V7K
1000P_0402_50V7K
100P_0402_50V8J
100P_0402_50V8J
SHELL 4
SHELL
1
EMI@ PC101
EMI@ PC102
EMI@ PC103
EMI@ PC104
JDCIN1
2
2
2
D D
C C
2
PR107
+CHGRTC
Vinafix.com
45.3K_0603_1%
PR108
1.5K_0603_5%
1
1 2
PD101
+3VL
LRB715FT1G_SOT323-3
2 +CHGRTC_R
+RTCBATT 1
3 PR109
1K_0603_5% JRTC1 CONN@
1 2 1
2 1
3 2
4 GND
GND
ACES_50271-0020N-001
B B
A A

Issued Date 2018/03/09 Deciphered Date 2019/03/09 Tiitlle
THIIS SHEET OF ENGIINEERIING DRAWIING IIS THE PROPRIIETARY PROPERTY OF COMPAL ELECTRONIICS,, IINC.. AND CONTAIINS CONFIIDENTIIAL
PWR- DCIN / Vin Detector
Siiize Document Number R ev
AND TRADE SECRET IINFORMATIION.. THIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIVIISIION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIIZED BY COMPAL ELECTRONIICS,, IINC.. NEIITHER THIIS SHEET NOR THE IINFORMATIION IIT CONTAIINS
MAY BE USED BY OR DIISCLOSED TO ANY THIIRD PARTY WIITHOUT PRIIOR WRIITTEN CONSENT OF COMPAL ELECTRONIICS,, IINC..
KBL 1.0
Date: Friiiday, March 09, 2018 Sheet 41 o f 55

5 4 3 2 1
5 4 3 2 1
EMI@ PL201
VMB2 +8.4V_VMB 5A_Z80_0805_2P
PF201 1 2
JBAT1 F1206HB12V024TM 12A 24V UL FAST
1 1 2
1 2 +12.6V_BATT+
EMI@ PL202
2 3 EC_SMCA 5A_Z80_0805_2P
3 4 EC_SMDA 1 2
4 5
5 6
1
6 7
1
100_0402_1%
100_0402_1%
7 8
8 9 PC201 EMI@ PC202 EMI@
D
1000P_0402_50V7K 0.01U_0402_16V7K D
GND 10
2
PR201
PR202
GND 11
2
GND 12
GND
Change 16V for 2S1P
SUYIN_125022HB008M200ZL
CONN@
EC_SMB_CK1 <36,43>
EC_SMB_DA1 <36,43>
1 2
+3VL
PR203
1 2 200K_0402_1% +3VALW
PR204
@200K_0402_1%
1 2
PR205
VCIN1_BATT_TEMP <36,43> PH201 under CPU botten side :
10K_0402_5% CPU thermal protection at 93 +-3 degree C
Recovery at 56 +-3 degree C
+EC_VCCA
16.5K_0402_1%
1
C C
PR206
2
Vinafix.com
<36> VCIN0_PH1
1
PH201
100K +-1% 0402 B25/50 4250K
2
ECAGND
B B
A A

PWR- BATTERY CONN/OTP
Custom
KBL 1.0

5 4 3 2 1
A B C D
Module model information

ISL95520A_Hybrid_Boost_V2.mdd
Protection for reverse input
1 Vgs = 20V 1
Vds = 60V
Id = 250mA
D
1
2 PQ707
G L2N7002W T1G_SC70-3
S max Power loss 0.22W for 90W;0.12W for 65W system;0.05W for 45W B+
3
Rds(on) = 15.8mohm max CSR rating: 1W
1 2 1 2
Vgs = 20V VCSIP-VCSIN spec < 81mV
PR738 PR737 Vds = 30V
1M_0402_1% 3M_0402_5% ID = 10.5A (Ta=70C)
+19V_P1 PQ712
Need check the SOA for inrush PQ740 AON7506_DFN33-8-5 PR703
EMB04N03H_N_DFN56-8-5 5 1 1 +19V_P2 0.01_1206_1% B+
2 2
3 3 5 1 4
+19V_VIN
PC765 @EMI@
2 3
PC705 EMI@
2200P_0402_25V7K
4
0.1U_0402_25V7K
4
10U_0805_25V6
10U_0805_25V6
1
PC762
PC760
CSIN_CHG_R
CSIP_CHG_R
2 1
2 1
21
2
K
K
1
1
2_0402_5
PR740
0_0402_5
PR772
1
%
287K_0402_1
2%
PR729
ASGATE_CHG_R
2
PC747
PQ705
% 2
1 2
4.02K_0402_1%
PR762 4.02K_0402_1%
2
AON7506_DFN33-8-5 2
1
0.1U_0402_25V6
1
1
2
5 3
Vinafix.com
PR745
PR729 and PR732 are ACDET set t i ng base on your proj ect to set. 100_0402_1%
2
2
4
PC750 0.22U_0603_25V7K
PR763
1 2 +12.6V_BATT+ Rds(on) = 32mohm max
Vgs = 20V
Vds = 30V
CMSRC_CHG ID = 8A (Ta=70C)
1
@PC779
2200P_0402_50V7K
49.9K_0402_1
PR732
PC715
ASGATE_CHG
1
1 2
2 1
BGATE_CHG
% 2
0.1U_0402_25V7K
OPCN_CHG 2
CSIN_CHG
CSIP_CHG
OPCP_CHG
0x3CH <BIT9> PSYS current gain
VBAT_CHG
Rs1 = 10mΩ and Rs2 = 5mΩ or Rs 1 = 10m Ω and Rs2 = 10mΩ BIT0 Rds(on) = 32mohm max
VDD_CHG
= 1.14uA/W Vgs = 20V

BIT1 = 0.285uA/W
Vds = 30V
5
=========================================================
Rs1 = 20mΩ and Rs2 = 10mΩ or Rs 1 = 20m Ω and Rs2 = 20mΩ PU703
ID = 8A (Ta=70C) PQ704
BIT0 = 2.28uA/W support Turbo boost : 2200P no Support max charge 3.5A
32
31
30
29
28
27
26
25
1
support Turbo boost : 0.1u

100K_0402_1
ISL88739AHRZ-T_QFN32_4X4
BIT1 = 0.57uA/W
AON7408L_DFN8-5 7X7X3 Power loss: 0.245W
PR741
CSR rating: 1W
OPCN
QPCP
BGATE
CSIN
CSIP
ASGATE
CMSRC
VBAT
PC721 4
PR771 0_0603_5% 0.22U_0603_25V7K Isat: 6.5A VCSPP-VCSON spec < 81mV
ACIN_CHG 1 24 BST_CHG 1 2 BST_CHG_R 1 2 DCR: 28mohm
%
2
Ipsys = KPSYS x ( VAD P x IAD P + VBA T x IBAT ) ACIN BOOT PR765

23 UG_CHG PL700
R_Psys = 1.2V / Ipsys 2 0.01_1206_1%
<36> VCIN1_AC_IN
3
2
1
ACOK UGATE
KPSYS = 1.14uA/W
22 LX_CHG
4.7UH_5.5A_20%_7X7X3_M
+17.4V_BATT_CHG 1
+12.6V_BATT+
1
adapter wattage = 45W PR769 1 2 0_0402_5% 3 1 2 4

<36,42> EC_SMB_DA1 SDA PHASE
158K_0402_1
PR731
Battery wattage = 40Wh 21 LG_CHG

PR770 1 2 0_0402_5% 4 2 3
680P_0603_50V7K 4.7_1206_5%
Ipsys = 1.14 x (45+40) = 96.9uA SCL LGATE
1
<36,42> EC_SMB_CK1
R_Psys = 1.2V / 96.9uA = 12.3K-ohm. 20 VDDP_CHG
10U_0805_25V6
10U_0805_25V6
10U_0805_25V6
3
PR777 1 2 0_0402_5% 5 PQ706 3
=====================================
@EMI@ PC767 @EMI@ PR766

% 2
<36> VCOUT1_PROCHOT# PROCHOT# VDDP
AON7752_DFN3X3EP8-5
adapter wattage = 65W 1 2 1K_0402_1%AMON_ISL95520 6 19 VDD_CHG 1 2
PC775
PC776
PC761
PR780
Battery wattage = 40Wh <36> ADP_I AMON VDD
Ipsys = 1.14 x (65+40) = 119.7uA
21
21
21
7 18 PR760 4.7_0402_5%
BMON DCIN
1
R_Psys = 1.2V / 96.9uA = 10K-ohm. 4
K
Close to EC. 8 17 PC768
BATGONE
PC769
PSYS NTC
1
1U_0402_16V6K 1U_0402_16V6K
2
CCLIM
ACLIM
COMP
PROG
AGND
CSON
CSOP
PR757
FSET
0.1U_0201_10V6K
1
100K_0402_1%
2
3
2
1
1
10K_0402_1
1
PR727
PC748
PD703
33
10
11
12
13
14
15
16
9
**Design Notes** Follow adapter and PR743 10_1206_5% 3 +19V_VIN

2
battery wattage in @ 1 2 1
For 45W/65W /90W system, 2S/3S/4S battery
3
Close to Vsys current source. 2
2%
BA PQ710
Maximum Charging current 3.5A EC.
VF = 0.38V
2
FSET_CHG
PC757
Base on CPU Core VR design.
1U_0603_25V6
Maximum Battery discharge power 55W The resistor is pop on CPU VR schematic. LRB715FT1G_SOT323-3 LMUN5113T1G PNP SOT323-3
1
2
#Register Setting
1
PR778
1. 0X3DH bit10 set 0 (default 1) to enable turbo boost function 10K_0402_1% A31 connect to BA
2. Disable turbo when AC only VDD=5V VDD_CHG
1
#Circuit Design Other team connect to bat t conn
2
1. ACLIM and CCLIM are devider voltage control.
1
CCLIM_CHG
2.Use 7X7 choke and 3X3 H/L side MOSFET <10,36,46> PM_SLP_S4# 2
200K_0402_1%
Charge current 3A ACLIM_CHG

1
1
Power loss : 1.79W (H/S=0.227W,L/S=1.2738W,Choke=0.297W)

PR749
PR750
PROG_CHG CSOP_CHG 1 2 CSOP_CHG_R PQ711
200K_0402_1%
Power density : 0.61 (23X16)
BA
3
COMP_CHG
#Protect function PR742 2_0402_5% LMUN5236T1G NPN SOT323-3
1. ACOVP : VCC voltage > 24V
2
2
1
499_0402_1%
2. SMBus timeout : 0X3DH bit15 set 0 (default 0) to enable 175s(default). @ PR779 Fs=729KHZ ~ +/- 15% PC708 BA
38.3K_0402_1%
1
76.8K_0402_1% 0.1U_0402_25V6
3. ACOC : OX3CH bit4 set1 release adapter limit function (default:Enable).
2
2 PR755 1
PR754
1 2 PR776
4. CHGOCP : based on charge current setting CSON_CHG CSON_CHG_R
1
1 2
165K_0402_1%
5. BATOVP : 4.6V/Cell
560P_0402_50V7
PR753
6. BATLOWV : No. @ PQ741

PC751
0_0402_5%
2
2 1
1
1
D
76.8K_0402_1%
4 4
7. TSHUT : 150C
1
VCIN1_AC_2IN PR752 For A31 only.

2
VCIN1_BATT_TEMP <36,42>
0.015U_0402_25V7
G 162K_0402_1% Turn off Charger IC on battery only.

1
Depend on customer design for

PC752
PR751
S
3
L2N7002W T1G_SC70-3 BATGONE(BATT_TEMP) system power consumption.

K
2
logic high: above 2.4V

2
2
Hybrid boost power mode logic low: under 0.8V

Cell = 2s
(Rs1 = 10mΩ and Rs2 = 5mΩ or Rs 1 = 20m Ω and Rs2 = 10mΩ).
CC_LIM = VccLIM / 64 x Rs2
K
=============================================================
(Rs1 = 10mΩ and Rs2 = 10mΩ or Rs 1 = 20m Ω and Rs2 = 20mΩ). Securiiity Clllassiiifiiicatiiion Compal Secret Data Compal Electronics, Inc.
CC_LIM = VccLIM / 32 x Rs2 2018/03/09 2019/03/09 Tiiitttlle
=============== =============================================
Battery current limimed by CCLIm ~ 3.89A.
t
PWR_CHARGER
AC_LIM = Vac_LIM / 32 x Rs1 THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IINC... AND CONTAIIINS CONFIIIDENTIIIAL
Adapter current limimed by ACLIm ~ 4.33A. AND TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D Siiize Documenttt Number Re v
(PR779 and PQ741 are for change ACLIm when AC in) DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIT CONTAIIINS 1..0
A B C D
A B C D E

SY8286B_V3_single.mdd
SY8286B_V3_dual.mdd
1 1
keep short pad,

snubber is for EMI only.
B+ PU401
EMI@ PL401 SY8286BRAC_QFN20_3X3 @ PR401 PC401
5A_Z80_0805_2P 0_0402_5% 0.1U_0402_25V6
+19VB_3V BST_3V 2 BST_3V_R 1
1 2 1 2 Use 7x7x3 size when the layout space is enough.
2200P_0402_50V7K
@EMI@ PC403
0.1U_0402_25V6
10U_0805_25V6K
1
1
1
EMI@ PC404
PL402
PC405
1.5UH_6A_20%_5X5X3_M
BS
IN
IN
IN
IN
2
2
LX_3V6 20 LX_3V 1 4
LX LX +3VALWP
7 19 2 3
GND LX
4.7_1206_5%
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
8 18
@EMI@
PR405
+3VL GND GND
PC407
PC408
PC409
PC410
9 17
+3VLP
2
PG LDO
1
10 16
NC NC
Check pull up resistor of SPOK at HW side
3V_SN2
1
PC411
OUT
EN2
EN1
21
NC
4.7U_0603_6.3V6K
FF
2
PR406 GND
680P_0603_50V7K
100K_0402_5%
11
12
13
14
15
1
Vout is 3.234V~3.366V
2
3.3V LDO 150mA~300mA
@EMI@
PC412
<36,40,46> 3V/5VALW_PG
2
2 ENLDO_3V5V PC402 PR403 TDC=6A Iocp=10A 2
1000P_0402_50V7K 1K_0402_1%
5V_3V_EN 3V_FB 1 2 3V_FB_1 1 2
Vinafix.com
EN1 and EN2 dont't be floating.
EN :H>0.8V ; L<0.4V Fsw : 600K Hz @ PJ401
1 2
+3VALWP 12 +3VALW
Module model information JUMP_43X118
SY8286C_V3_single.mdd
@ PJP402
SY8286C_V3_dual.mdd JUMP_43X39
1 2
keep short pad, +3VLP 1 2 +3VL
2 Cell battery : Cin=10uF*2pcs snubber is for EMI only.
3 Cell ~ 4 Cell battery : Cin=10uF*1pcs
B+ +19VB_5V
EMI@ PL403 @PR408 PC418
5A_Z80_0805_2P PU402 SY8286CRAC_QFN20_3X3 0_0402_5% 0.1U_0402_25V6
1 2 +19VB_5V BST_5V1 2 BST_5V_R 1 2
5
1
BS
IN
IN
IN
IN
PL404
LX_5V 6 20
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
LX LX 1.5UH_6A_20%_5X5X3_M
7 19 LX_5V
GND LX
1 4 +5VALWP
1
1
1
PC414
EMI@ PC416
PC415
@EMI@ PC417
8 18 2 3
3 GND GND PC419 3
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
2
2
2
VCC_5V 1 2
1
1
9 17
PG VCC
1
PR402
PC420
PC422
PC423
PC424
PC421
PC425
PR409
4.7_1206_5%
499K_0402_1% 10 16
@EMI@
2
2
1 2 ENLDO_3V5V NC NC 2.2U_0402_6.3V6M
B+
OUT
LDO
EN2
EN1
21 @ @
FF
GND
1
2
1
PR404
11
12
13
14
150K_0402_1% PC429
1U_0201_6.3V6M +5VLP
15V_SN
1 15
4.7U_0603_6.3V6K
2
5V LDO 150mA~300mA
2
3V/5VALW _PG
PC427
680P_0603_50V7K
ENLDO_3V5V
@EMI@
PC426
2
Vout is 4.998V~5.202V
2
5V_3V_EN
PR410
2.2K_0402_5%
1 2 TDC=6A Iocp=10A
<36> EC_ON @ PR411 EN1 and EN2 dont't be floating. PC413 PR407
0_0402_5% EN :H>0.8V ; L<0.4V 1000P_0402_50V7K 1K_0402_1%
1 2 5V_FB 1 2 5V_FB_1 1 2
<36> VCOUT0_MAIN_PWR_ON
Fsw : 600K Hz
5V_3V_EN
@ PJ403
+19VB_5V 1 2
1M_0402_1%
+5VALWP +5VALW
4.7U_0402_6.3V6M
12
1
1
PR412
JUMP_43X118
PC428
4 BATTDROP@ @PJP404 4
2
1
JUMP_43X39
2
PR451 1 2
+5VLP 1 2 +VL
560K_0402_5%
2
VCIN1_BATT_DROP <36>
1
BATTDROP@ BATTDROP@ Issued Date 2018/03/09 Deciphered Date 2019/03/09 Tiitlle

PC451
PR452
1000P_0402_50V7K +3VALW/+5VALW
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
105K_0402_1% Siiize Document Number R ev
2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A B C D E
5 4 3 2 1

RT8207P_single_V3.mdd For Single layer
RT8207P_dual_V3.mdd For Dual layer
D D
Pin19 need pull separate from +1.35VP.

If you have +1.35V and +0.675V sequence question, 0.675Volt +/- 5%
EMI@ PL501 you can change from +1.35VP to +1.35VS. TDC 0.7A
B+ 5A_Z80_0805_2P
+12.6VB_DDR Peak Current 1A
1 2 PR501
2.2_0603_5%
BST_DDR_R 1 2 BST_DDR
+1.2VP
0.1U_0402_25V
2200P_0402_50V7
10U_0805_25V6
10U_0805_25V6
1
1
1
1
@EMI@PC501
PC503
PC504
EMI@PC502
UG_DDR +0.6VSP
2
2
2
2
6
K
LX_DDR
10U_0603_6.3V6
10U_0603_6.3V6
1
1
PC505
5
0.1U_0402_25V7K
PC506
PC507
16
18
17
19
20
2
C PU501 C
2
PQ501
BOOT
VLDOIN
VTT
UGATE
PHASE
21
AON7408L_DFN8-5 PAD
M
LG_DDR 15 1
Vinafix.com
4
LGATE VTTGND
PL502 14 2
1UH_11A_20%_7X7X3_M PR502 PGND VTTSNS
1
2
3
12.7K_0402_1%
1 4 1 2 CS_DDR 13 3
+1.2VP PC508 CS RT8207PGQW_WQFN20_3X3 GND
1
2 3 1U_0201_6.3V6K
5
1 2 12 4 VTTREF_DDR
VDDP VTTREF
22U_0603_6.3V6
22U_0603_6.3V6
22U_0603_6.3V6
22U_0603_6.3V6
22U_0603_6.3V6
22U_0603_6.3V6
RF@ PR503 30MA_30V_0.5UA_0.4V_SOD323-2 PD501

1
1
1
4.7_1206_5% PR504 2 1
PC513
PC509
PC510
PC511
PC512
PC514
5.1_0603_5% 11 5
VDD VDDQ
+1.2VP
1
1 2
1 2 VDD_DDR
PGOOD
+5VALW
2
2
4 PC515
+5VALW PR505
TON
1
RF@ PC517 0.033U_0402_16V7K
FB
S5
S3
2
M
M
680P_0402_50V7K PQ502 PC516 1 2

2
1U_0201_6.3V6K 2.2_0603_5%
10
6
2
7
1
2
3
AON7506_DFN3X3-8-5
EN_DDR
FB_DDR
EN_0.675VSP
TON_DDR
PR506
1 2 +1.2VP
PR507 470K_0402_1%
B +12.6VB_DDR1 2 B
6.04K_0402_1%
1
@ PR508
0_0402_5%
Choke: 7x7x3 1 2 PR509
<13,36> SYSON
Rdc=6.7mohm(Typ), 7.4mohm(Max) 10K_0402_1%
Mode Level +0.675VSP VTTREF_1.35V
2
1
@ PC518
Switching Frequency:540kHz
S5 L off off 0.1U_0402_10V7K
Ipeak=8A
S3 L off on
2
Iocp~9.6A
S0 H on on
OVP: 113%~120% @ PR510
Note: S3 - sleep ; S5 - power off VFB=0.75V, Vout=1.3545V 0_0402_5%
1 2
<13,36,40> SUSP#
@PJ501
@ PR511 1 2
+1.2VP 1 2 +1.2V
0_0402_5%
1 2 JUMP_43X118
<7> DDR_VTT_PG_CTRL
1
@ PC519
0.1U_0402_10V7K
2
PJ50@3
1 2
+0.6VSP 1 2 +0.6VS
A
JUMP_43X39 A

Issued Date 2019/03/09 Tiiitllle
2018/03/09 Deciphered Date
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
RT8207P
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPET ENT DIVISION OF R&D SiiizeDocument Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friiiday, March 09, 2018 Sheet 45 of 55
5 4 3 2 1
5 4 3 2 1

APL5930_V2.mdd
D D
+3VALW +5VALW
Ultra Low Dropout 0.23V(typical) at 3A Output Current
1
PC801
1
JUMP_43X79 1U_0201_6.3V6M
2
@ PJ801
2
2
PU801
G9661MF11U_SO8
1
C PC802 4 5 C
3 VPP NC 6
4.7U_0603_6.3V6K PJ802
@ PR801 2 VIN VO 7 +1.8VALWP @
GND
2
VEN ADJ
1
1 2
Vinafix.com
0_0402_5% 1 8 +1.8VALWP +1.8VALW
12.7K_0402_1%
0.01U_0402_16V7K
POK GND 1 2
1
<36,40,44> 3V/5VALW_PG 1 2
JUMP_43X79
PR802
PC803
22U_0603_6.3V6M
9
Rup
2
1
1
0.1U_0402_16V7K
2
PR803
PC804
PC805
2
1M_0402_5%
2
@ PR804
2
1
100K_0402_5%
10K_0402_1%
1
PR805
Rdown
2
+3VALW
PGOOD <47>
Vout=0.8V* (1+Rup/Rdown)
+3VALW +5VALW
B B
1
PC806
1
JUMP_43X79 1U_0201_6.3V6M
2
@ PJ803
2
Vout=0.8V* (1+Rup/Rdown)
2
PU802
G9661MF11U_SO8
1
PC807 4 5
3 VPP NC 6
4.7U_0603_6.3V6K
@ PR806 2 VIN VO 7 +2.5VP
GND
2
VEN ADJ
1
0_0402_5% 1 8
3.4K_0402_1%
0.01U_0402_16V7K
POK GND
1
1 2
<10,36,43> PM_SLP_S4#
PR807
PC808
22U_0603_6.3V6M
9
Rup
1
1
0.1U_0402_16V7K
2
PC809
PC810
PR808
47K_0402_5% PJ804 @
2
2
1 2
+2.5VP +2.5V
2
1 2
1
1.6K_0402_1%
JUMP_43X79
PR809
Rdown
2
A A

Issued Date 2018/03/09 Deciphered Date 2019/03/09 Tiiitllle
APL5930
Custom
KBL 1.0

5 4 3 2 1
A B C D E

SY8286_V2_single.mdd
SY8286_V2_dual.mdd
+3VALWConfirm HW side
+19VB_1V keep short pad,
1
@EMI@ PR605 @EMI@ PC602
1 1
@ PR611 snubber is for EMI only. 4.7_1206_5% 680P_0603_50V7K
100K_0402_5% 1 2 SNUB_1V 12
@PJ602 PU601
2
+19VB_1V Use 7x7x3 size when the layout space is enough.
B+ 1
1 2
2 2
IN PG
9 @ PR606
0_0402_5%
PC603
0.1U_0402_25V6
10U_0805_25V6
3 1 BST_1V 1 2 BST_1V_R 1 2
0.1U_0402_25
JUMP_43X79 IN BS PL602
1
1
2200P_0402_50V
PC606
EMI@ PC604
@EMI@ PC605
4 6 LX_1V
IN LX
1 2
+1.0VALWP
2 1
2
2
5 19 1UH_6.6A_20%_5X5X3_M
IN LX
22U_0603_6.3V6
22U_0603_6.3V6
22U_0603_6.3V6
22U_0603_6.3V6
14.3K_0402_1
V6
330P_0402_50V
K
7 20
PC608
PC610
PR608
PC609
PC611
PC612
GND LX
R1
7K
2 1
2 1
2 1
2 1
2 1
8 14 FB_1V
GND FB
2
LDO_3V
%
@ PR603 18 17
7K
GND VCC
M
0_0402_5%
1
1
EN_1V 11 10
<46> PGOOD 1 2
EN NC
PC613
ILMT_1V 13 12 PR612
2.2U_0402_6.3V6M
2
ILMT NC
1
@ PC601 1K_0402_1%
PR601 0.1U_0402_25V6 15 16
+3VALW BYP NC
2
1M_0402_1% FB=0.6V
2
21 @ PJ601
+3VALW PAD JUMP_43X118
2
EN :H>0.8V ; L<0.4V SY8286RAC_QFN20_3X3

+1.0VALWP
1
1 2
2
+1.0VALW
1
PC614
EN pin don't floating Vout=0.6V* (1+R1/R2) R2
1
1U_0201_6.3V6M PR610
2
If have pull down resistor at HW side, @ PR607 20K_0402_1%
please delete PR601. 0_0402_5% =0.6*(1+(14/20))
2
Vout=1.02V
2
1
2 @ PR609 2
0_0402_5%
2
Vinafix.com
The current limit is set to 6A, 9A or 12A when this pin
is pull low, floating or pull high.
3 3
4 4
2018/03/09
Compal Secret Data
2019/03/09 Tiiitttllle
CCoommppaalEEleeccttrroonniccss,Inc.
t
SY8286
Dattte::: Friiiday,,, March 09,,, 2018 Sheett 47 o ff55
A B C D E
1 2 3 4 5
RT3602_VREF Vref=0.6V
PCZ3
953_0402_1%
0.1U_0402_25V7K
15K_0402_1%
6.8K_04 02_1%
1
1
1
1
PRZ2
PRZ4
PRZ3
2
AISPVCCSA <49> @
A A
<49> AVCCSA PCZ4
2
0.47U_0402_25V6K
1 2
12
1 2
+VCCSA
1
> 0.47U_0402_25V6K
PRZ1 PRZ8 PRZ10 PRZ14
<13
VSSSA_SENSE
11K_0402_1%
10_0402_1%
5K_0402_1%
0_0402_5% RT3602_VREF
<15>
100_0402_1% 10K_0402_1% 48.7K_0402_1%
PCZ193
PRZ6
PRZ11
VSSCORE_SENSE
1 2 VCCSA_SENSE_R 2 1 1 2
PRZ5
1 2 1 2
2 1
PRZ13
RT3602_SET1 PRZ15
2
2
1 2 1 2 59K_0402_1%
RT3602_SET2 1 2
RT3602_SET3 <13> VCCSA_SENSE
100_0402_1%
PCZ5 390P_0402_50V7K PCZ6 68P_0402_50V8J
VR_PSYS 0_0402_5% @ PCZ1 @PRZ16
0_0402_5%
+3VS
RT3602_VREF 3.9_0402_1%
0.1U_0402_10V6K 10K_0402_1% PRZ23
PRZ24
1
1
1
1 2 1 2 10K_0402_5%
colose to core1 MOSFET
1
1
1
PRZ22 100_0402_1%
10K_0402_1
1 2
FB_SA
499_0402_1% 5.23K_0402_1%
PRZ20
PRZ19
PRZ18
2.1K_0402_1% 1.1K_0402_1%
PRZ17
3K_0402_1% 464_0402_1%
VR_PWRGD <36>
2
1
@ PHZ1 PRZ26
2
2
0_0402_5
100K_0402_1%_B25/50 4250K 5.9K_0402_1%
%
PRZ21
PRZ94
PRZ95
2 PHZ1_R 1 PRZ25
2
@ PCZ7 1 2
RT3602_VREF
12
12
0.1U_0402_10V6K U22@ PRZ35 1 2 VR_ON <36>

2
1
%
20K_0402_1%
+1.0V_VCCST
IMON_SA
0_0402_5
RT3602_EN
PRZ31
PRZ30
PRZ29
1 2 IMON_CORE_R 1 2 0_0402_5%
PRZ28
VSEN_CORE
PRZ33 U42@ PRZ35 RGND_MAIN
FB_SA
COMP_SA
RGND_SA
VR_PSYS
%
17.4K_0402_1%
21.5K_0402_1%
2
2
1
1
1
110_0402_1
75_0402_1
45.3_0402_1
100_0402_1
@ PCZ9
PRZ37
@ PCZ8 @PRZ40 0.1U_0402_10V6K PCZ194
PUZ1
2 1
0.1U_0402_10V6K 10K_0402_1%
48
40
45
44
43
1 2 0.1U_0201_10V6K
49
IMON_SA 3839
PRZ36
PRZ38
PRZ39
COMP_SA 42
RGND_MAIN 47
RT3602AEGQW_WQFN48_6X6
%
121 2 @
VSEN_MAIN 46
VREF06/PSET 41
VR_READY 37
%
2
2
%
PRZ43 PRZ45
%
EN
PSYS
FB_SA
RGND_SA
GND
ISENP_SA
ISENN_SA
10K_0402_1% 51K_0402_1% VR_SVID_CLK <15>
VSEN_CORE 1 2 1 2 VR_ALERT# <15>
+VCCCORE PRZ41 VR_SVID_DATA <15>
IMON_CORE 1 36
100_0402_1% PCZ12 82P_0402_50V8J RT3602_SET1 PWM_SA <49>
1 2 2 IMON_MAIN PW M_SA 35 VR_HOT# <36>
1 2 1 2 FB_CORE SET1 DRVEN DRVEN <49>
PRZ47 3 34 1 2
0_0402_5% U42@ PCZ13 COMP_CORE 4 FB_MAIN VCLK 33 PRZ98
49.9_0402_1% RT3602_VREF
PCZ11 220P_0402_50V8J <49> AVCORE1 RT3602_SET2 5 COMP_MAIN
<15> VCCCORE_SENSE 1 2 0.1U_0402_25V7K
1 2
Ra RT3602_SET3 6 SET2
ALERT#
VDIO
32
31
PRZ991 210_0402_1%
PR1Z100 100_20402_1%
PRZ48
30K_0402_1% PRZ49 17.4K_0402_1%
U42@ PRZ106 7 SET3 VR_HOT# 30 IMON_GT 1 2 1 2
U22@ PCZ11
270P_0402_50V8J 1 2 1 2 ISEN1N_MAIN 8 ISEN1N_MAIN IMON_AUXI 29 @ PCZ15 0.47U_0402_25V6K
U42@ 0_0402_5% 9 ISEN2N_MAIN ISENP_AUXI 28 1 2
PCZ16 0.1U_0402_25V7K 10 ISEN2P_MAIN ISENN_AUXI 27 VSEN_GT
<49> AVCORE2 TSEN_CORE 11 ISEN1P_MAIN VSEN_AUXI 26 COMP_GT
Ra Rb/Rc RT3602_VIN12 TSEN_MAIN COMP_AUXI 25 AISP1 <49>
Rb VIN RGND_AUXI AVGT1 <49> PRZ50
17 PW M1_MAIN
B 1 2 0_0402_5% B
18PW DRVEN_SET
+5VALW VSEN_GT
1
U22@ PRZ105 10K_0402_1% 1 2 1 2
M2_MAIN
VCCGT_SENSE <15>
0.22U_0402_25VAK
FB_AUXI
U22 N/A Stuff
1
2.2_0805_1
PCZ18
PW M_AUXI
<49> AISPCORE2
FB_GT 24 TSEN_AUXI
0.1U_0402_25V7K PRZ54 PRZ56 PRZ59
PRZ53
+VCCGT
VCC
100_0402_1%
Rc 10K_0402_1%
NC
NC
15.8K_0402_1%
NC
NC
NC
1 RGND_AUXI
PCZ19
2
1
1 2 1 2 1 2
0_0402_5%
1 2
+5VALW
2
U42 Stuff N/A
%
U22@ PRZ104 10K_0402_1%
20
15
PRZ93
19
14
21
13
16
TSEN_GT 23 22
DRVEN_SET
<49> AISPCORE1
1 2
1 2
RT3602_VREF
Vinafix.com
PRZ51 PRZ52
2
1RT3602_VCC
TSEN_CORE_R 4.3M_0402_1% 1.3M_0402_1% PCZ20 82P_0402_50V8J
1 2 1 2 PCZ21 270P_0402_50V7K
+19VB_CPU
PRZ60
PHZ2
100_0402_1%
1 2 1 2 12
2
1
1
0_0402_5
FB_GT
VSSGT_SENSE <15> @ PRZ61 @ PCZ22
PRZ62
100K_0402_1%_B25/50 4250K
10K_0402_1% 0.1U_0402_10V6K
PRZ64
100_0402_1% 9.1K_0402_1%
<49>
<49>
<49>
PWM_GT
PWM_CORE1
PWM_CORE2
PRZ63
%
+5VALW
2
PRZ65
VCC_CPU_R
2
10_0402_1%
1 2
1
1
3.9K_0402_1%
PRZ68
PRZ67
1
PCZ23
TSEN_CORE_R
2 1
2
4.7U_0402_10V6M PRZ66
TSEN_GT_R
4.3M_0402_1%
1
100K_0402_1%_B25/504250K
5K_0402_1%
1
1
750K_0402_1%
PRZ71
+5VALW
12
PRZ70
3.92K_0402_1% 200K_0402_1%
2
PHZ3
PRZ69
2
1.3M_0402_1%
1
1 2
@ PRZ72
2
1
0_0402_5%
68.1K_0402_1%
PRZ74
PRZ73
DRVEN_SET
TSEN_GT_R
2
12
@ PRZ75
0_0402_5%
C C
2
D D
SecuriiitttyClllassiiifffiiicatttiiion Compalll Secret Data Compal Electronics, Inc.

2018/03/09 2019/03/09 Tiittle
IIIssued Dattte Deciiiphererr d Dattte
CPU_CORE
THISII SHEET OF ENGINII EERINII G DRAWINIIG IST
I HE PROPRIETII ARY PROPERTY OF COMPAL ELECTRONICS,,,II INC...IIAND CONTAINSII CONFIDENTI IALIIAND TRADE
SECRET INIFORMATION...II THISIISHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISIONIIIIIIOF R&D DEPARTMENT EXCEPT AS Siiize Documenttt Numberrr Re v
AUTHORIZII ED BY COMPAL ELECTRONICS,,,II INC...IINEITII HER THISII SHEET NOR THE INFIIORMATIONII ITICONTAINSII
MAY BE USED BY OR DISCIILOSED TO ANY THIRDII PARTY WITIIHOUT PRIORII WRITIITEN CONSENT OF COMPAL ELECTRONICS,,,II INIC... 1...0
Dattte::: Frrriiday,,,Marrrch 09,,, 2018 Sheettt 48 o ff 55
1 2 3 4 5
5 4 3 2 1
EMI@ PLZ4 5A_Z80_0805_2P B+

+19VB_CPU
1 2
+19VB_CPU
PRZ76 1 2
PCZ205
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6
2.2_0603_5%
PCZ31
D CORE1_BST CORE1_BST_R 1
0.1U_0402_25V6
D
@EMI@ PCZ29
1 2 EMI@ PLZ3 5A_Z80_0805_2P
EMI@ PCZ30
+
100U_25V_NC_6.3X6
U42@ PRZ77
2 1
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
PUZ2 PQZ1
10U_0805_25V6
2.2_0603_5%
PCZ26
PCZ32
EMIU42@ PCZ33
@EMIU42@ PCZ36
CORE2_BST CORE2_BST_R
@ PCZ206
2 1
2 1
2 1
0.1U_0402_25V6
RT9610CGQW_WDFN8_2X2 PCZ28 1 2
U42@ PCZ37
U42@ PCZ34
2 1
5
0.1U_0402_25V6 2
1
AON6380_DFN5X6-8-5
K
U42@ PUZ3 U42@
4 3 CORE1_UG CORE1_UG_R
2 1
2 1
2 1
2 1
2 1
4 RT9610CGQW_WDFN8_2X2 PCZ35 @
2
BOOT UGATE
2 1
0.1U_0402_25V6
CORE1_LX
K
5 2
<48> PWM_CORE1 PW M PHASE 4 3 CORE2_UG CORE2_UG_R 4
BOOT UGATE
+5VALW
<48> DRVEN
1
EN PGND
6 Rdc=0.98 mohm CORE2_LX
U42@
3
2
1
+VCCCORE 5 2 PQZ3
1 PRZ8 0 2 VCC_CORE1 8 7
PLZ1 <48> PWM_CORE2 PW M PHASE
AON6380_DFN5X6-8-5
VCC LGATE 9 1 4 +5VALW DRVEN1 6 Rdc=0.98 mohm
3
2
1
GND EN PGND +VCCCORE
1_0402_5%
2 3 1 2 VCC_CORE2 8 7 U42@ PLZ2
VCC LGATE 9
1
PQZ2 1 4
4.7_1206_5%
RF@
PRZ82
GND
1
PCZ40 U42@ PRZ81
0.15UH_NA 36A_20% 1_0402_5% 2 3
2.2U_0402_6.3V6M
2
AISPCORE1_R
U42@
AON6314_N_DFN56-8-5
4.7_1206_5%
5
1
U42RF@ PRZ84
PCZ41
0.15UH_NA 36A_20%
2 1
AISPCORE2_R
CORE1_LG 2.2U_0402_6.3V6M
4 PCZ42
1CORE1_SNUB 2
0.1U_0402_25V6K
1 2 1 2 1 2
CORE2_LG 4 U42@ PRZ87 U42@ PRZ103 U42@ PCZ43
1CORE2_SNUB 2
PRZ85 PRZ102 @ PRZ88 1.2K_0402_1% 1.2K_0402_1% 0.1U_0402_25V6K
3
2
1
1.2K_0402_1% 1.2K_0402_1% 560_0402_1% 1 2 1 2 1 2
U42@ U42@ 1 2 U42@
PQZ4 @ PRZ90
3
2
1
PCZ44 RF@ AON6314_N_DFN56-8-5 10_0402_1%
680P_0402_50V7K 1 2
2
U22@ PRZ85 U22@ PRZ102 PCZ45 U42RF@
1K_0402_1% 1K_0402_1% 680P_0402_50V7K
2
AVCORE1 <48>
AVCORE2 <48>
H/S AON6280:
AISPCORE1 <48> R DS(ON) (at V GS =10V) < 6.8m
AISPCORE2 <48>
R DS(ON) (at V GS =4.5V) < 10.5m
L/S AON6214:
R DS(ON) (at V GS =10V) < 2.8m?
R DS(ON) (at V GS =4.5V) < 3.5m?
C C
+19VB_CPU
VCC_CORE VCC_GT VCC_SA
FSW=450kHz FSW=450kHz FSW=600kHz
Vinafix.com
Choke=0.15uH Choke=0.15uH DCR=6.2 mohm +/- 5%
PRG2 DCR=0.67 mohm +/- 5% DCR=0.67 mohm +/- 5%
PCG6
PCG
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
2.2_0603_5%
U22
0.1U_0402_25V6
GT_BST GT_BST_R
@EMI@ PCG3
1 2
EMI@ PCG4
U22 U22
5
LL=10.3 mohm
2 1
1
PUG1 PQG1
LL=2.4 mohm LL=3.1 mohm
2 1
2 1
2 1
RT9610CGQW_WDFN8_2X2 PCG2
TDC=4A
0.1U_0402_25V6
TDC=21A TDC=18A
AON6380_DFN5X6-8-5
ICCMAX=5A
2
5
GT_UG GT_UG_R
4 BOOT UGATE 3 4 ICCMAX=32A ICCMAX=31A OCP=10A
<48> PWM_GT
5 PW M PHASE 2 GT_LX OCP=40A OCP=39A
+5VALW DRVEN 1 6 Rdc=0.98 mohm U42
U42 U42
3
2
1
EN PGND
1 PRG1 2 VCC_GT PLG1
+VCCGT
LL=10.3 mohm
8
VCC LGATE
7
9 1 4 LL=2.4 mohm LL=3.1 mohm TDC=4A
1_0402_5% GND
2 3
TDC=42A TDC=12A ICCMAX=5A
PQG2 ICCMAX=64A ICCMAX=28A OCP=10A
4.7_1206_5%
5
RF@ PRG4
PCG1
0.15UH_NA 36A_20% OCP=70A OCP=39A
2 1
2.2U_0402_6.3V6M
AON6314_N_DFN56-8-5
AISP1_R
GT_LG
2
4 PRG6 PRG9 PCG8

1K_0402_1% 2.05K_0402_1% 0.1U_0402_25V6K
1 2 1 2 1 2
1GT_SNUB
PRG7 PRG8
3
2
1
3K_0402_1% 10K_0402_1%
1 2 1 2
AVGT1_R
PCG9 RF@
680P_0402_50V7K
2
1 2
PHG1
10K_0402_1%_B25/50 3370K
B AVGT1 <48> B
AISP1 <48>
+19VB_CPU
10U_0805_25V6K
2200P_0402_50V7K
PRA2
10U_0805_25V6
@EMI@ PCA6
0.1U_0402_25V6
2.2_0603_5%
SA_BST SA_BST_R
EMI@ PCA2
1
1 2
PCA5
PCA4
1
2 1
2 1
2 1
PUA1
2
RT9610CGQW_WDFN8_2X2 PCA3
K
0.1U_0402_25V6
2
4 3 SA_UG SA_UG_R
BOOT UGATE
5 2 SA_LX
<48> PWM_SA PW M PHASE
Rdc=0.98 mohm
1
+5VALW DRVEN 1 6 PQA1

D1
D1
D1
G1
EN PGND +VCCSA
AONH36334_DFN3X3A8-10
1 2 VCC_SA 8 7 PLA1
VCC LGATE 9 9 10 1 4
PRA1 1_0402_5% GND D2/S1 D1
2 3
G2
S2
S2
S2
4.7_1206_5%
1
RF@ PRA4
PCA1
2 1
0.47UH_NA 12.2A_20%
2.2U_0402_6.3V6M
8
AISPVCCSA_R
SA_LG
2
PCA7
0.1U_0402_25V6K
1 2 1 2 1 2
1 SA_SNUB
PRA6 PRA9 PRA7 PRA8

A 1K_0402_1% 1K_0402_1% 825_0402_1% 1K_0402_1% A
1 2 1 2
AVCCSA_R
PCA8 RF@
680P_0402_50V7K
2
1 2
PHA1
1K_0402_5%_TSM0B102J3652RE
AVCCSA <48>
SecuriiitttyClllassiifffiiicatttiiion Compalll Secret Data Compal Electronics, Inc.

AISPVCCSA <48> Tiitttlle
IIIssued Dattte 2018/03/09 Deciiiphered Datett 2019/03/09
CPU Power stage
THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIISTHE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC...AND CONTAIIINS CONFIIIDENTIIIAL AND
TRAD E SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETEN T DIIIVIIISIIION OF R&D
DEPARTMEN T EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC...NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIITCONTAIIINS 1...0
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IIINC...
Dattte::: Frrriiday,,,Marrrch 09,,, 2018 Sheettt 49 offf 55
5 4 3 2 1
5 4 3 2 1
Current Limit threshold setting Different VGA Chip (different EDP-Peak Current) need select different solution
PWM-VID Spec and component Values
Rocset= (Ivalley * Rds(on) + 40 mV) / 10uA
PWM-VID Spec Config A Config B Config C
VGA Chip N14P-GV N14M-LP N14P-LP
I_ripple=(19-0.9)*0.9/
Vmin 0.6V 0.6V 0.65V (304.89Khz*0.36u*19)=7.811A Config B Config B Config B
Vmax 1.2V 1.2V 1.15V
Iocp=42A per phase Rated TDPPower atTj=102C 18W 13W 18.9W
Vboot 0.875V 0.9V 0.9V Ivalley=42A-7.811A/2=38.0945A
Voltage step 6.25mV 6.25mV 25mV Boosted GPU Total at Tj=102C 25W 20W 23W
D D
N ofVoltage level 96 96 20
EDP-Continuous at Tj=102C 24A 22A 25A
Rrefadj PR8 39K 20K 39K
Rref1 PR7 39K 20K 30K EDP-Peak at Tj=102C 35A 35A 35A
Rboot PR10 1.5K 2K 3K
Istep max (Evaluation) 15A 20A 14A
RT8812A-1P_V2A.mdd for IC portion PR20 30K 18K 24K
Rref2=PR20+PR21
PR21 1.5K 0 Choke: 0.22uH (Size:10*10*4)
3K OCP SettingCurrent 42A 42A 42A
RT8812A-1P_V2B.mdd for SW portion Rdc=0.82 ± 5 %
C PC9 1.5nf 2.7nf 1.8nf
+3VS_DGPU_AON
Heat Rating Current=40A Rocset （PR12） 10.2K 10.2K 10.2K
OpenVReg Configurations Saturation Current=90A
Operation phase Number PSI Voltagesetting C=3*330uF (9mohm)=990uF Recommendation 1phase 2H2L 1phase 2H2L 1phase 2H2L
Vripple=Iripple*ESR(min)=7.811A*3mohm=23.4mV
1
1 phasewith DEM 0V to 0.8V
PR22
1 phase with CCM VGA_B+
PR3 @VGA@
10K_0402_5% 1.2V to 1.8V PolymerCap (330uF) 6mohm * 2 6mohm * 2 6mohm * 2
0_0402_5% Active phasewith CCM 2.4V to 5.5V
10U_0805_25V6
10U_0805_25V6
1 2
1
1
<24> PSI
1 2
MX130@ PC4
MX130@ PC3
Or OSCON (390uF) 10mohm * 3 10mohm * 3 10mohm * 3
PR23 Pull high on HW side
2
10K_0402_5% PR2 Whether needs 3 OSCON capacitors depend on DC ripple test results!
C 1K_0402_5% VEMI@PL1 C
K
1 2 DH1_VGA 5A_Z80_0805_2P
DGPU_MAIN_EN <24,26>
2
VGA_B+ 1 2
B+
Vinafix.com
2200P_0402_50V7
0.1U_0402_25V
10U_0805_25V6
10U_0805_25V6
1
1
PR4 @VGA@
VEMI@ PC6
@VEMI@ PC7
1
1
1
PR7 0_0402_1% PC5 @VGA@ MX130@ PQ1202
PC1314
PC1315
Rref1 <24> GPU_VID0
G1
D1
20K_0402_1% 1 2 .1U_0402_16V7K AON6994_DFN5X6D-8-7
2
2
2
7 LX1_VGA
2
+3VS_VGA 1 D2/S1 DH1_VGA

Rboot Rrefadj 2 +VGA_CORE MX110
6
K
K
PR10
EDP-Continuous 18.8A
K
2K_0402_1% PR1 @VGA@
G2
S2
S2
S2
1 2 1 2 1K_0402_5% EDP-Peak 31A
DH1_VGA
OCP min 40A
6
GPU_VID
GPU_PSI
GPU_EN
PR8
18K_0402_1%
1
0.01U_0402_16V7
20K_0402_1% PR6
2700P_0402_50V7K
1
2.2_0603_5%
PR20
1
1
BST_VGA 1 2 BST_VGA-1 DL1_VGA MX110@ PQ1201
G1
D1
@VGA@ PC19
PL2
N16_VGA@ PC9
Rref2 AON6962_DFN5X6D-8-7
1 0.22UH WSRPG1004-R22M-AG-R82 40A +VGA_CORE
REFADJ
1 2
2 7 LX1_VGA 1 4
C
@VGA@ PR21
D2/S1
5
PU1 PC8 MX130@ PQ1201

0_0402_1%
1SN2UB_VGA 1
0.22U_0603_25V7K AON6994_DFN5X6D-8-7 2 3
VID
EN
BOOT1
PSI
UGATE1
G2
1 1 1
S2
S2
S2
6 20 LX1_VGA PR11 VRF@ + PC11 + PC12 + PC13
2
6
RGND REFADJ PHASE1 4.7_1206_5% 330U_2V_M 330U_2V_M 330U_2V_M
B REFIN 7 19 DL1_VGA DL1_VGA 2 2 2 B
PC10 REFIN LGATE1 PC15 VRF@
1U_0201_6.3V6M 680P_0402_50V7K
2
1
1 2 VREF_VGA 8 18 GPU_PVCC
VREF RT8812AGQW_WQFN20_3X3 PVCC
12.4K_0402_0.5
Rocset +VGA_CORE MX130
PR13
PR12
@VGA@ PR26
VGA_B+ 1 2 1 2 TON 9 17 EDP-Continuous 27.2A
499K_0402_1% TON LGATE2 EDP-Peak 53A
2
1
0_0805_5% Rton OCP min 65A

10 16
@VGA@ PC42
RGND PHASE2 +VGA_CORE
%
UGATE2
PGOOD
1U_0603_25V6K
BOOT2
Under GPU Core GB2B-64 package

2
@VGA@ PR15 MX110@

VSNS
GND
0_0402_1%
SS
1 2
RGND
<21> GND_SENSE_GPU MX130@ PR12
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
PC2
PC2
PC2
PC2
PC2
PC2
PC2
PC2
PC2
PC2
@VGA@ PR14 14.3K_0402_1%
21
11
12
13
14
15
1
1
1
0_0402_5%
1 2 1 2
PR16 +5VALW
2
2
2
10_0402_1%
0.01U_0402_16V7K
1000P_0402_50V7
1
PC16
8
3
9
2
@VGA@ PC18
1
Css 1U_0402_6.3V6K
2
@VGA@ PC17
2
2
PR17
10K_0402_5%
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
PC3
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
PC3
PC3
PC3
PC3
PC3
PC3
PC3
PC3
PC3
PC4
K
PR19 1 2
1
1
1
1
1
1
1
1
10_0402_1% +3VS
1 2 GPU_VSENSE
A +VGA_CORE A
2
2
2
2
2
2
2
DGPU_PWROK <21,25,26>
<21> VDD_SENSE_GPU 1 2
3
2
0
5
4
9
6
0
@VGA@ PR18
0_0402_1%
Issued Date 2019/03/09 Tiiitllle
2018/03/09 Deciphered Date
Remark: 2. Soft-Start time (Internal) is 0.7ms (PC18 un-pop) VGA_CORE
1. Switching frequency setting: Tss=(Css*Vrefin)/Iss+2.3ms THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPET ENT DIVISION OF R&D SiiizeDocument Number Re v
Fsw=(Vin-0.5)/(2*Vin*Rton*3.2p) =0.01U*0.9V/5uA+2.3ms=4.1ms (PC18 pop) Custom 1.0
=304.89Khz
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W IT HOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC. VGA_CORE
Date: Friiiday, March 09, 2018 Sheet 51 of 55
5 4 3 2 1
A B C D E

SY8286_V2_single.mdd
SY8286_V2_dual.mdd
+3VS Confirm HW side
+19VB_VRAM keep short pad,
1
@VEMI@ PR1302 @VEMI@ PC1302
1 1
PR1301 snubber is for EMI only. 4.7_1206_5% 680P_0603_50V7K
100K_0402_5% 1 2 SNUB_VRAM 1 2
@
PU1301
PJ1301 +1.35VGS_PGOOD <26>
2
1 2 +19VB_VRAM 2 9 Use 7x7x3 size when the layout space is enough.
B+ 1 2 IN PG
@VGA@ PR1303
0_0402_5%
PC1305
0.1U_0402_25V6
0.1U_0402_25V6
10U_0805_25V6
3 1 BST_VRAM 1 2 BST_VRAM_R1 2
JUMP_43X79 IN BS PL1301
1
1
2200P_0402_50V
PC1304
2 1
4 6 LX_VRAM 1 2
+1.35VGSP
VEMI@ PC1301
@VEMI@ PC1303
IN LX
2
5 19 1UH_6.6A_20%_5X5X3_M
IN LX
22U_0603_6.3V6
22U_0603_6.3V6
22U_0603_6.3V6
22U_0603_6.3V6
27K_0402_1
330P_0402_50V
K
7 20
PC1306
PC1307
PC1308
PC1309
PC1310
PR1304
GND LX
R1
7K
2 1
2 1
2 1
2 1
2 1
8 14 FB_VRAM
GND FB
%
2
PR1305 18 17 LDO_3V_VRAM
7K
GND VCC
M
10K_0402_1%
1
1
1 2 EN_VRAM 11 10
<25,26> 1.35V_PWR_EN EN NC
PC1311
ILMT_VRAM 13 12 PR1306
2.2U_0402_6.3V6M
2
ILMT NC
1
PC1312 1K_0402_1%
PR1307 0.1U_0402_25V6 15 16
+3VALW NC
2
BYP
1M_0402_1% FB=0.6V
2
21 @ PJ1302
+3VALW PAD
JUMP_43X118
PC131
1U_0201_6.3V6M
2
EN :H>0.8V ; L<0.4V SY8286RAC_QFN20_3X3

+1.35VGSP
1
1 2
2
+1.35VS_VRAM
1
EN pin don't floating Vout=0.6V* (1+R1/R2) R2
2 1
1
@VGA@ PR1308
If have pull down resistor at HW side, PR1309 21.5K_0402_1%
please delete PR601. 0_0402_5% =0.6*(1+(27/21.5))
2
3
Vout=1.353V
2
1
@VGA@
2 PR1310 2
0_0402_5%
2
Vinafix.com
The current limit is set to 6A, 9A or 12A when this pin
is pull low, floating or pull high.
3 3
4 4
2018/03/09
Compal Secret Data
2019/03/09 Tiiitttllle
CCoommppaalEEleeccttrroonniccss,Inc.
t
SY8286
Dattte::: Friiiday,,, March 09,,, 2018 Sheett 52 o ff55
A B C D E
5 4 3 2 1
<7,18> DDR_A_MA[0..16]
D D
+1.2V
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
SE00000UC00
SE00000UC00
SE00000UC00
SE00000UC00
SE00000UC00
SE00000UC00
SE00000UC00
SE00000UC00
SE00000UC00
SE00000UC00
SE00000UC00
SE00000UC00
SE00000UC00
SE00000UC00
SE00000UC00
SE00000UC00
1
1
1
1
+0.6VS
CU197
CU200
CD216
CD217
CD218
CU198 @
CU195
CU199
CU196
CU201
CD211
CD210 @
CD212
CD213
CD214
CD215
2
2
2
RP17
DDR_A_MA9
1 8
DDR_A_MA2 7
2
DDR_A_MA4 3 6
DDR_A_BA1 4 5
<7,18> DDR_A_BA1
4 as near each on board RAM device as possible
36_0804_8P4R_5%
RP18
DDR_A_MA10 1 8
DDR_A_MA3 2 7
DDR_A_MA12 3 6
DDR_A_BG0 4 5
1 <7,18> DDR_A_BG0
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1 1 1 1 1
+ CU89 36_0804_8P4R_5%
CD39
CD25
CD26
CD27
CD40
220U_6.3V_M
@
2 2 2 2 2 2
RP19
DDR_A_MA16 1 8
M_A_ACT# 2 7
<7,18> M_A_ACT# DDR_A_CS#0 3 6
<7,18> DDR_A_CS#0 DDR_A_MA15 4 5
36_0804_8P4R_5%
DDR_A_BG1_R 1 DDP@ 2
C <18> DDR_A_BG1_R C
RD211 36_0402_1%
RP20
DDR_A_CKE0 1 8
<7,18> DDR_A_CKE0 DDR_A_ODT0 2 7
<7,18> DDR_A_ODT0
3 6
DDR_A_MA14 4 5
Vinafix.com
36_0804_8P4R_5%
RP21
DDR_A_MA13 1 8
DDR_A_MA8 2 7
+2.5V +0.6VS DDR_A_PARITY 3 6
<7,18> DDR_A_PARITY DDR_A_MA11 4 5
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
36_0804_8P4R_5%
SE00000UC00
SE00000UC00
SE00000UC00
SE00000UC00
SE00000UC00
SE00000UC00
SE00000UC00
SE00000UC00
SE00000UC00
SE00000UC00
SE00000UC00
SE00000UC00
SE00000UC00
SE00000UC00
SE00000UC00
SE00000UC00
1
1
1
1
1
1
CU205
CU204 @
CU213 @
CU203
CU209
CU218
CU215
CU217
CU206 @
CU208
CU207
CU210
CU216
CU212 @
CU214
CU211
2
2
2
2
2
2
RP22
DDR_A_MA1
1 8
DDR_A_BA0
2 as near each on board RAM device as possible <7,18> DDR_A_BA0
2 7
2 as near each on board RAM device as possible DDR_A_MA7
3 6
4 5
36_0804_8P4R_5%
RP24
DDR_A_MA5 1 8
2 7
DDR_A_MA6 3 6
DDR_A_MA0 5
10U_0603_6.3V6M
10U_0603_6.3V6M
4
10U_0603_6.3V6M
10U_0603_6.3V6M
SE000005T80
SE000005T80
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1 1 1 1 1 1 1
CD219 @
CD220 @
36_0804_8P4R_5%
CD41 @
CD42
CD43
CD46 @
CD47
B B
2 2 2 2 2 2 2
A A
LA---G201P
Securiiittty Clllassiiifffiiicatttiiion Compalll Secret Data
DDR4 MISC
SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D DEPARTMENT EXCEPT
Custttom
LA-D562P 1..0
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IIINC... Dattte::: Frrriiday,,, Marrrch 09,,,2018 Sheettt 20 offf 55
5 4 3 2 1
B
A
D
C
1
1
+VCCCORE
21 21 21 21
2
1
2
1
2
1
1
PCZ 1 8 8 PCZ 1 7 6 PCZ 1 6 1 PCZ 1 4 1 PCZ 1 2 4 PCZ 1 0 0 PCZ 8 0 PCZ 5 8
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
21 21 21 21
2 U2 2 @ 2
2
1
1
2
1
2
1
U2 2 B@ @
21 21 21 21
2
1
1
2
1
2
1
2@

21 21 21 21
2
1
1
2
1
2
1
2@
2
1
@
+

1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M U4 2 @ PCZ 4 8
21 21 21 21 330U_D1_2VY_R9M
2
1
2
1
2
1
1

21 21 21
2 U2 2 B@ 2
2
1
2
1
1
2
1
PCZ 1 8 3 PCZ 1 6 6 PCZ 1 4 6 PCZ 1 2 9 PCZ 1 0 5 PCZ 8 5 PCZ 6 3
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
U42
U22
21 21 21
2
1
1
2
1
2
1
PCZ 1 8 6 PCZ 1 6 7 PCZ 1 4 7 PCZ 1 3 0 PCZ 1 0 6 PCZ 8 6 PCZ 6 4

1uF*35
1uF*35
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

22uF*28
22uF*28
330uF*1
21 21 21
2
1
2
1
1
2 U2 2 @ 2 @
PCZ 1 7 9 PCZ 1 6 8 PCZ 1 4 8 PCZ 1 0 7 PCZ 8 7 PCZ 6 5

VCCCORE：
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

21 21 21
2
1
1
2
1
2@

21 21 21
1
2@
PCZ 1 8 0 PCZ 1 7 0 PCZ 1 5 0 PCZ 6 7

1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
2
2
+VCCGT
21 21
2
1
2
1
2
1
2
1
2
1

21 21
+ PCZ 49
2
1
2
1
2
1
1

21 21
+VCCCO RE
2
1
2
1
2
1
2
1
330U_D1_2VY_R9M

21
U22/U42 co-lay
2
1
2
1
2
1
2
1
+VCCG T
PCZ 1 5 4 PCZ 1 3 4 PCZ 1 1 2 PCZ 9 2 PCZ 5 3
1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
PRZ 2 01
21
2
1
2
1
2
1
2
1
1uF*13
PCZ 1 1 3 PCZ 9 3
22uF*33
330uF*1
PCZ 1 5 5 PCZ 1 3 5 PCZ 5 4

21
VCCGT：
U22 & U42
2
1
2
1
2
1
2
1
22U_0603_6.3V6M
22U_0603_6.3V6M
SX000000300
PRZ 2 03 SX000000300 1
PRZ 2 02 SX000000300 1
1
KBL R@ PCZ 20 3
KBL R@ PCZ 20 2
21
2
1
2
1
2
1
2
1
12
12
12
21
U22B@
U42B@
U42B@
2
1
2
1
2
1
2
1
2
1

21
U4 2 @ U4 2 @
1
2
2
1
2
1
2
1

21
2
1
2
1
2
1
PCZ 1 6 0 PCZ 1 4 0 PCZ 6 9

PCZ 2 0 3 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
+VCCGT_VCCCORE U42
22U_0603_6.3V6M
2 SOL DER_PREFORMS_04 02
2 SOL DER_PREFORMS_ 0402

2 SOL DER_PREFORMS_ 0402
U4 2 @ U4 2 @
2
1
3
3
PCZ 2 0 4
22U_0603_6.3V6M
co-lay
+VCCGT_ VCCCORE
+VCCSA
21
2
1
2
1
PCZ 1 1 7 PCZ 9 8 PCZ 7 0

1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
21
2
1
2
1
PCZ 1 1 8 PCZ 9 9 PCZ 7 1

1uF*7
1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

22uF*9
21
2
1
VCCSA：
U22 & U42
PCZ 1 1 9 PCZ 7 2
1U_0201_6.3V6M 22U_0603_6.3V6M
21
2
1
PCZ 1 2 0 PCZ 7 3
1U_0201_6.3V6M 22U_0603_6.3V6M
21
2
1
PCZ 1 2 1 PCZ 7 4
1U_0201_6.3V6M 22U_0603_6.3V6M
21
2
1
PCZ 1 2 2 PCZ 7 5
IIssued Datte
1U_0201_6.3V6M 22U_0603_6.3V6M
21
2
1
Securiiitty Clllassiiiffiiicattiiion
PCZ 1 2 3 PCZ 7 6
1U_0201_6.3V6M 22U_0603_6.3V6M
1
PCZ 7 7
22U_0603_6.3V6M
2
1
PCZ 7 8
22U_0603_6.3V6M
4
4
2
1
2018/03/09
PCZ 7 9
22U_0603_6.3V6M
Vinafix.com
AUTHORIIIZED BY COMPAL ELECTRONIIICS,,,IIINC...NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIITCONTAIIINS

Compalll Secret Data
Deciiiphered Datett
2019/03/09
SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D DEPARTMENT EXCEPT AS
Tiitttlle
Siiize Documenttt Numberrr
Dattte::: Frrriiiday,,, Marrrch 09,,, 2018

5
5
PROCESSOR DECOUPLING
Sh e e t
50
of
55
1...0
R ev
B
A
D
C
5 4 3 2 1
Version change list (P.I.R. List) Page 1 of 1

for PWR
Item Reason for change PG# Modify List Date Phase
1 Down size for material shortage P49 Change PRA6,PRA9,PRG6 from 1K +-1% 0603 to 1K +-1% 0402 2018.03.05 SVT
D D
2
Down size for material shortage P49 Change PRZ102,PRZ85 from 1.2K +-1% 0603 to 1.2K +-1% 0402 2018.03.05 SVT
3 Down size for material shortage(U42 SKU) P49 Change PRZ103,PRZ87 from 1.2K +-1% 0603 to 1.2K +-1% 0402 2018.03.05 SVT
4 Down size for material shortage P49 Change PRG9 from 2.05K +-1% 0603 to 2.05K +-1% 0402 2018.03.05 SVT
P43 Change PR404 from 499K +-1% 0402 to 150K +-1% 0402
5 Down size for material shortage Change PC429 from 1U 16V K X5R 0402 to 1U 6.3V M X5R 0201 2018.03.05 SVT
P50
6 Down size for material shortage Change PC10,PC1313,PC30,PC31,PC32,PC33,PC614,PC801,PC806,PCZ117,PCZ151,
PCZ166,PCZ167,PCZ170,PCZ179 from 1U 6.3V K X5R 0402 to 1U 6.3V M X5R 0201 2018.03.05 SVT
P51
Change PCA1,PCG1,PCZ40,PCZ41 from 2.2U 16V K X5R 0402 to SVT

7 Down size for material shortage P49 2.2U 6.3V M X5R 0402 2018.03.05
C C
Change PC401,PC418,PC603,PC1305 from 0.1U 10V K X5R 0201 to

Change size for common design P44 0.1U 25V K X5R 0402 2018.03.05 SVT
8
Vinafix.com
9 Down size for material shortage P48 Change PCZ23 from 4.7U 10V K X5R 0603 to S CER CAP 4.7U 10V M X5R 0402 2018.03.05 SVT
10 Change PC20,PC28,PC36,PC37,PC38,PC39,PC40 from 4.7U 6.3V K X5R 0603

Down size for material shortage P51 to 4.7U 6.3V M X5R 0402 2018.03.05 SVT
11 Change PC505 from CAP .1U 25V K X7R 0603 to 0.1U 25V K X7R 0402
Down size for material shortage P45 2018.03.05 SVT
B B
16
17
A A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
PIR (PWR)
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
Z_BDW 1.0

5 4 1
5 4 3 2 1
Version change list Page 1 of 2 for

(P.I.R. List) HW
1 ME Request 41 Add Screw Hole H15. 2017/12/13 EVT -> PVT
2 ME Request 41 Remove Screw Hole H16. 2017/12/15 EVT -> PVT
D 3 0 Ohm Reduction 31 Replace RA2 with R-Short. 2017/12/18 EVT -> PVT D
4 0 Ohm Reduction 34 Replace R242 with R-Short. 2017/12/18 EVT -> PVT
5 0 Ohm Reduction 29 Replace R203, R211, R212 with R-Short. 2017/12/18 EVT -> PVT
6 Phase Out Un-Necessary X4E Level 3 Remove X4EABQ38L51 and X4EABQ38L52. 2017/12/19 EVT -> PVT
7 Update 14" PCB DA Part Number. 3 DA6001YG000 -> DA6001YG100 2017/12/19 EVT -> PVT
8 Cost Down Plan 36 C2147, C2149 -> 14" Only (BOM Structure Modify) 2017/12/20 EVT -> PVT
10 Cost Down Plan 20 Un-Pop CU206, CU204, CD41, CU198, CD210, CU213, CU212, CD46 2017/12/21 EVT -> PVT
11 Cost Down Plan 19 Un-Pop C2140, CD19, CD10, CD32, CD33, CD23 2017/12/21 EVT -> PVT
12 Cost Down Plan 18 Un-Pop CD127 2017/12/21 EVT -> PVT
C
13 Cost Down Plan 13 Replace CC45 with 10uF 2017/12/21 EVT -> PVT C
Vinafix.com
15 0 Ohm Reduction 39 Replace R275, R276, R277, R279 with R-Short. 2017/12/21 EVT -> PVT
16 0 Ohm Reduction 10 Replace RC103 with R-Short. 2017/12/21 EVT -> PVT
17 0 Ohm Reduction 19 Replace RD108, RD140 with R-Short. 2017/12/21 EVT -> PVT
19 0 Ohm Reduction 37 Replace R425, R428, R102 with R-Short. 2017/12/21 EVT -> PVT
20 0 Ohm Reduction 32 Replace RL18 with R-Short. 2017/12/21 EVT -> PVT
22 Cost Down Plan 28 Un-Pop CV703, CV707, CV708, CV718 (DIS@) 2017/12/21 EVT -> PVT
B B
23 Cost Down Plan 27 Un-Pop CV603, CV607, CV614, CV616, CV617 (DIS@) 2017/12/21 EVT -> PVT
24 Cost Down Plan 22 Un-Pop CV35 (DIS@) 2017/12/21 EVT -> PVT
25 Cost Down Plan 28 Replace CV701 with 10uF 2017/12/21 EVT -> PVT
26 Cost Down Plan 27 Replace CV602 with 10uF 2017/12/21 EVT -> PVT
27 Cost Down Plan 41 Un-Pop Q401, R401, R402 2017/12/21 EVT -> PVT
28 Cost Down Plan 13 Un-Pop CC40 2017/12/21 EVT -> PVT
29 Cost Down Plan 18 Replace RD200, RD201, RD202, RD203, RD205 with R-Short. (SDP@/DDP@) 2017/12/21 EVT -> PVT
30 Cost Down Plan 20 RD211 -> DDP Only (BOM Structure Modify) 2017/12/21 EVT -> PVT
A A
31 VRAM EOL 27, 28 Remove VRAM UV8, UV9 (Replace with x32 DIE *2) 2017/12/22 EVT -> PVT

PIR (HW)
Custttom 1..0
LA-G202P
Dattte::: Frrriiday,,, Marrrch 09,,, 2018 Sheettt 54 o ff 55
5 4 3 2 1
5 4 3 2 1
Version change list Page 2 of 2 for

(P.I.R. List) HW
1 ME Request 38 Replace Touch Pad Connector Symbol (JTP1) - SP01001A800 2017/12/22 EVT -> PVT
2 VRAM EOL 24 Replace ROM_SI (RV65) BOM Structure with 256M*32 2017/12/25 EVT -> PVT
D 3 VRAM EOL 3 Replace 2GB VRAM X76 BOM Structure with @ (X7677538L01, L02, L03) 2017/12/25 EVT -> PVT D
4 Layout Footprint Update 34, 35 Swap JHDD1, JODD2 Pin Define 2017/12/25 EVT -> PVT
5 VRAM EOL 27 Replace UV7 Data Lanes / EDC / DBI / RV130.2 - Pull High +1.35VS_VRAM 2017/12/26 EVT -> PVT
6 Fine Tune YL1 Crystal Capacitor Value 31 CL13 / CL14 : 10pF -> 27pF 2017/12/26 EVT -> PVT
7 Card Reader IC Controlled by X76 3, 32 Realtek -> X7677538LA1 , Genesys -> X7677538LA2. 2017/12/26 EVT -> PVT
8 EMI Cost Down Plan 30 Replace CA41, CA42 with R-Short (Location Changed to RA65, RA66) 2017/12/28 EVT -> PVT
9 Prevent +3VS_WLAN Drop 33 Reserve C245, C246 2017/12/29 EVT -> PVT
10 ME Request 34, 35 Replace JODD2, JHDD1 Symbol with SP010025K00 2017/12/31 EVT -> PVT
11 VRAM BOM Structure Update 3 Replace X7677538L04, L05, L06 BOM Structure with 2GB 2018/01/08 EVT -> PVT
12 Card Reader IC BOM Structure Update 32 Controlled by Main/Substitute, No X76 Anymore 2018/01/08 EVT -> PVT
C
13 VRAM BOM Structure Update 3 Delete X7677538L01, L02, L03 (EVT VRAM*4 - 2GB) 2018/01/08 EVT -> PVT C
14 On Board RAM P/N Update 11 Replace On Board RAM P/N with R3 2018/01/08 EVT -> PVT
Vinafix.com
15 Cap P/N Update 40 Replace C383 470pF with 1nF (SE074102K80) 2018/01/08 EVT -> PVT
16 Cap P/N Update 40 Replace C386 220pF with 2.2nF (SE075222K80) 2018/01/08 EVT -> PVT
17 Dual Load Switch P/N Update 13, 40 Replace UC5, U381 SA00006U300 with SA00007PM00 2018/01/08 EVT -> PVT
18 Update CPU R3 Part Number 3 Add SA0000BKN30 (i3-8130U R3) and SA0000BLH50 (i3-7020U R3). 2018/02/22 PVT -> Pre-MP
19 Resistor Fine Tune - LED3 and LED4 39 Replace R376 and R378 with 200 Ohm. (SD034200080) 2018/02/22 PVT -> Pre-MP
20 Dual Load Switch P/N Update. (Source Priority Changes) 13, 40 Replace UC5, U381 - SA00007PM00 with SA0000BEL00. 2018/02/22 PVT -> Pre-MP
21 Keyboard Resistor Value Update 38 Replace R271 with 0 Ohm (@) 2018/02/22 PVT -> Pre-MP
22 Keyboard Resistor Value Update 38 Replace R278 with R-Short. 2018/02/22 PVT -> Pre-MP
B B
23 Keyboard Resistor Value Update 38 Replace R272, R274, "R277 (15@)" with 470 Ohm. 2018/02/22 PVT -> Pre-MP
24 Co-Lay Remove 17 Remove LC99 2018/02/27 PVT -> Pre-MP
25 Replace BOM Structure 3 Replace SA0000BLH50 BOM Structure with i3_7020U_U22@. 2018/03/09 PVT -> Pre-MP
26 Add CPU 3 Add SA0000BLD60 (SR3LD) - i3_7020U_U42@ 2018/03/09 PVT -> Pre-MP
27 Replace DA Part Number with DAZ P/N 3 Replace with DAZ29900201 (14_DAZ@) & DAZ29A00201 (15_DAZ@). 2018/03/09 PVT -> Pre-MP
28 ESD Request 36 Add C122 (0.1uF) 2018/03/09 PVT -> Pre-MP
29
30
A A
31
Securiity Cllassiiifiicattiion Compal Secret Data Compal Electronics, Inc.

Issued Date 2018//03/09 Deciiphei red Date 2019//03//09 Tiitttlle
PIR (HW)
THIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIETARY PROPERTY OF COMPAL ELECTRONIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
Siiize Documentt Numberr Rev
TRADE SECRET IIINFORMATIIION.. THIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D
Custttom 1..0
DEPARTMENT EXCEPT AS AUTHORIIZED BY COMPAL ELECTRONIICS,,, IIINC.. NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIIT CONTAIIINS
MAY BE USED BY OR DIISCLOSED TO ANY THIIRD PARTY WIIITHOUT PRIIOR WRIITTEN CONSENT OF COMPAL ELECTRONIICS,,, IIINC..
LA-G202P
Dattte::: Frrriiday,,, Marrch 09,,2018 Sheettt 55 o ff 55
5 4 3 2 1

130-15ikb Compal Dlid4 Dlid5 La-G202p

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A B C D E

Intel KabyLake U/KabyLake R Processor with DDR4

Security Classification Compal Secret Data Compal Electronics, Inc.

Memory Bus (Channel A)

Memory Bus (Channel B)

LAN PCIe X1 (1 Lane) 1356 Pin BGA

ODD Conn. SATA X1

HDD Conn. SATA X1 USB2.0 x1 Card Reader

LED Int. KBD Hall Sensor

Securiiity Clllassiiifiiicatiiion Compal Secret Data Compal Electronics, Inc.

G3->S0 S0->S3/DS3 S0/DS3->S0 S0->S5

PCH_PWR_EN (SLP_SUS#) PCH_PWR_EN (SLP_SUS#)

EXT_PWR_GATE# If EXT_PWR_GATE# Toffmin is too small, Pwr EXT_PWR_GATE#

Securiiittty Clllassiifffiiicatttiiion Compalll Secret Data Compal Electronics,Inc.

Voltage Rails BOM Structure Table

SMBUS Control Table

SMB_EC_DA1 +3VALW +3VALW +19 V_VIN X X

*N16V - MX110 Device ID:0x174E

Securiiity Clllassiiifiiicatiiion Compalll Secret Data

Trace width=20 mils, Spacing=25mil, Maxlength=100mils

If routed MS, PECI requires 18 mils spacing to other signals

1 2 H_THERMTRIP# 1 2 H_PROCHOT#_R C65 PECI

Securiiity Clllassiiifiiicatiiion Compal Secret Data Compal Electronics, Inc.

Recommended By Intel Max

Security Classification Compal Secret Data Compal Electronics, Inc.

Dattte::: Friiiday,,, March 09, 2018 Sheet 7 off 55

SML0ALERT# (Internal Pull Down):

0 = LPC is selected for EC ==> Default

RC21 1 @ 2 1K_0402_5% SOC_SPI_IO2 +3VS

RPC1, RPC3 and RC30 are close to UC3

< SPI ROM - 8MB > - Main Source - XMC

Securiiity Clllassiiifiiicatiiion Compal Secret Data Compal Electronics, Inc.

Datte:: Friiiday,,, March 09,,,2018 Sheett 8 o ff 55

SPKR (Internal Pull Down):

Datte:: Friiiday,,, March 09,,,2018 Sheett 9 o ff 55

Stuff 60.4 ohm (RC110) PD for CannonLake-U

RC37 1 2 20K_0402_5% SOC_RTCRST# RC38 1 2 0_0402_5% EC_CLEAR_CMOS# <36> +3VS

+3VALW S CRYSTAL 32.768KHZ 9PF X1A000141000200

Securiiity Clllassiiifiiicatiiion Compal Secret Data Compal Electronics, Inc.

Date: Friiiday,,, March 09,,,2018 Sheet 10 o ff 55

Capacity Description X76 PART NUMBER R3

N/A N/A N/A

Function MODEL SETTING

SOC_GPIOC10 RC204 1 2 0_0402_5% GPU_EVENT#

Securiiity Clllassiiifiiicatiiion Compal Secret Data Compal Electronics, Inc.

Datte:: Friiiday,,, March 09,,,2018 Sheett 11 o ff 55

When PCIE8/SATA1A is used as SATA Port 1 (ODD), then

Securiiity Clllassiiifiiicatiiion Compal Secret Data Compal Electronics, Inc.

Date: Friiiday,,, March 09,,,2018 Sheet 12 o f 55

I(Max) : 3.04 A(+1.0VS_VCCIO)

Datte:: Friiiday,,, March 09,,,2018 Sheett 13 o ff 55

VCCPRIM_1P0_Y18 VCCCLK3 +1.0V_APLL

MURATA BLM15EG221SN1D CC67 1 2 1U_0201_6.3V6M

+1.0V_CLK6_24TBT RTC Battery

+1.0VALW +3VALW +1.8VALW +3VALW W=20mils

Safty suggestion remove EE side, Keep PWR side

Datte:: Friiiday,,, March 09,,,2018 Sheett 14 o ff 55

Trace Length Match < 25 mils SKL-U_BGA1356

SVID DATA Place the PU