Scan-based Testing of Synthesized Design

Raunak Gupta, Soumik Sarkar

Department of Electrical Engineering
IIT Bombay
November 24, 2015

Abstract
We describe a simple mechanism to validate a digital system on the Krypton CPLD
board. In this mechanism, the system being validated (the device under test or DUT)
is implemented together with a scan chain, and a host computer is used in conjunction
with a microcontroller card to apply test patterns to the DUT, and to verify that the
outputs from the DUT are as expected.

Introduction

Testing a complex digital system using switches and LEDs is not possible for two reasons:
complex systems can have many inputs and outputs, and to test them, one has to apply
several test patterns. An automated mechanism for testing complex systems is necessary.
Such a mechanism is called a tester. We will describe a simple tester that you can use to
test your design on the Krypton CPLD card.
The mechanism uses three steps:
The design that you wish to test (the DUT) is to be implemented in the Krypton card
by connecting a scan-chain to it. The scan-chain is used to send the input pattern to
the DUT and to extract the response of the DUT. This is done by instantiating the
VHDL description of the DUT with a scan-chain component which will be provided to
you.
A test-pattern file needs to be created on a host computer. The test-pattern file specifies
the input patterns and the expected outputs. You can generate the test pattern file
using a VHDL simulation of the DUT together with a testbench.
The host computer needs to be connected to the Krypton card using a microcontroller
bridge which allows the host to download patterns to the Krypton card and extract
the response from the Krypton card.
In this document we describe, using an example, the three step mechanism outlined
above. In Section 2, we describe how the scan-chain is to be interfaced to the DUT at
the VHDL description level. In Section 3, we describe the format of the test-pattern file.
In Section 4, we describe the way in which the microcontroller bridge card can be used to
connect the host computer to the Krypton card. Finally, in Section 5, we illustrate the test
procedure from the host computer.

in.txt
out.txt

uC

Python
script

Krypton
TDI
TCLK
TMS
TRST

USB link

Scan Chain

PC

DUT

TDO
Figure 1: Tester Architecture [3]

Scan Chain Insertion

The user has to write a top level entity which uses the DUT and Scan Chain module as
components. The top level entity will have only these two components communicating with
each other. It will have 5 interface signals (1 bit each) TDI, TMS, TCLK, TRST and TDO; and
should be connected to pins of the CPLD using Pin Assignment feature of Altera-Quartus.
TopLevel
TDI
dut_in

TMS
TRST

Scan_Chain

TCLK

DUT

dut_out
TDO

Figure 2: Top Level entity inside Krypton

Suppose you wish to test a particular design of addition of two 16-bit vectors.
Consider the following DUT entity description:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity DUT is
port (
clock, reset: in std_logic;
A, B: in std_logic_vector(15 downto 0);
Sum: out std_logic_vector(15 downto 0));
2

end entity;
architecture Behave of DUT is
signal sumvector: std_logic_vector(15 downto 0);
begin
process(clock, reset)
begin
if (reset = 1) then
sumvector <= std_logic_vector(to_unsigned(0, sumvectorlength));
elsif (clockevent and clock = 1) then
sumvector <= std_logic_vector(unsigned(A) + unsigned(B));
end if;
end process;
Sum <= sumvector;
end Behave;
This DUT has 34 inputs and 16 outputs. To test it we will use a scan chain.
The scan chain module has two configurable parameters (in pins & out pins) indicating
the number of input and output bits to the DUT, which can be generic mapped. It also
has one output (dut in) and one input (dut out) that should be connected to the DUT.
Internally it contains an FSM, one input scan register and one output scan register. The
entity of the scan chain module is given below:
entity Scan_Chain is
generic (
in_pins : integer; -- Number of input pins
out_pins : integer -- Number of output pins
);
port (
TDI : in std_logic; -- Test Data In
TDO : out std_logic; -- Test Data Out
TMS : in std_logic; -- TAP controller signal
TCLK : in std_logic; -- Test clock
TRST : in std_logic; -- Test reset
dut_in : out std_logic_vector(in_pins-1 downto 0); -- Input for the DUT
dut_out : in std_logic_vector(out_pins-1 downto 0); -- Output from the DUT
);
end Scan_Chain;
The scan-chain and the DUT are instantiated together in a top-level entity as follows
entity TopLevel is
port (
TDI : in std_logic; -- Test Data In
TDO : out std_logic; -- Test Data Out
TMS : in std_logic; -- TAP controller signal
TCLK : in std_logic; -- Test clock
TRST : in std_logic; -- Test reset
);
end TopLevel;
architecture Struct of TopLevel is
3

-- declare DUT component

component DUT is
port (
clock, reset: in std_logic;
A, B: in std_logic_vector(15 downto 0);
Sum: out std_logic_vector(15 downto 0));
end component;
-- declare Scan-chain component.
component Scan_Chain is
generic (
in_pins : integer; -- Number of input pins
out_pins : integer -- Number of output pins
);
port (
TDI : in std_logic; -- Test Data In
TDO : out std_logic; -- Test Data Out
TMS : in std_logic; -- TAP controller signal
TCLK : in std_logic; -- Test clock
TRST : in std_logic; -- Test reset
dut_in : out std_logic_vector(in_pins-1 downto 0); -- Input for the DUT
dut_out : in std_logic_vector(out_pins-1 downto 0); -- Output from the DUT
);
end component;
-- declare I/O signals to DUT component
signal clock, reset: std_logic;
signal A, B, Sum: std_logic_vector(15 downto 0);
-- declare signals to Scan-chain component.
signal scan_chain_parallel_in : std_logic_vector(33 downto 0);
signal scan_chain_parallel_out: std_logic_vector(15 downto 0);
begin
scan_instance: Scan_Chain
generic map(in_pins => 34, out_pins => 16)
port map (TDI => TDI,
TDO => TDO,
TMS => TMS,
TCLK => TCLK,
TRST => TRST,
dut_in => scan_chain_parallel_in,
dut_out => scan_chain_parallel_out);
dut_instance: DUT
port map(clock => clock, reset => reset, A => A, B => B, Sum => Sum);
-- connections between DUT and Scan_Chain
reset <= scan_chain_parallel_in(33);
clock <= scan_chain_parallel_in(32);
A <= scan_chain_parallel_in(31 downto 16);
B <= scan_chain_parallel_in(15 downto 0);
scan_chain_parallel_out <= Sum;
end Struct;

2.1

Project using Quartus

Open Quartus.
Go to File -> Open New Project Wizard.
Specify the working directory for the project.
Write the name of top-level entity in the name of the project. (TopLevel in the present
example)
Click Next.
Ensure the Project type is Empty Project. Click Next.
Add all the VHDL files that you created for this project. The files include all the VHDL
files related to your DUT, the TopLevel entity, the Scan Chain entity (Scan Chain.vhd )
and the Scan Register entity (Scan Reg.vhd ). The Scan Chain and Scan Register VHDL
files are provided to you. Click Next.
In the Family & Device Settings, select Family -> MAX V, Package -> TQFP, Pin
count -> 144, Core Speed Grade -> 5, and select device 5M1270ZT144C5. Click Next
twice & Finish.
Now compile the design by pressing Ctrl+L.
After compilation, if there are no errors observed, we will do the pin assignment by going
to the menu Assignments -> Pin Planner. The Pin Planner will open in a new window. You
will see the port names of the top-level entity already specified in the Node Name column.
Fill the values in the location column as given in Table 1.
Node Name
TDO
TDI
TMS
TRST
TCLK

Location
PIN 3
PIN 5
PIN 7
PIN 21
PIN 23

Table 1: Pin Planning

Compile the design again (Press Ctrl+L).

Go to Tools -> Programmer. A new window opens up and you should see the name of
your top-level entity (TopLevel.pof ). If you dont, go to Add File in the left panel, select
the .pof file (TopLevel.pof ). You can find it in the Output Files.
To create a flashable file, go to File -> Create JAM, JBC, SVF or ISC file menu. Select
.svf format from the File Format drop down menu. Do not change any other parameters
and click OK. You should see a .svf file generated in your project folder.
Flash the .svf file into CPLD using UrJTAG. Follow UrJTAG User Manual [1].

Test Input Format

The text file to be passed to the python script for test execution has to be written in following
format. Specify only the values written in italics.
5

SDR inpins TDI(input) outpins TDO(output) MASK(maskbits)

The inpins & outpins contain the number of input & output pins of the DUT, respectively, in decimal format. The attributes (input) & (output) contain the input vector
to be applied and its expected output vector, respectively, in hex notation. The maskbits
are used to specify if any of the output bits of the CPLD need to be compared with the
expected output. A bit value 1 signifies that comparison is required. The mask bits are
also specified in hex notation.
This instruction loads the input into the Scan Chain register inside the CPLD. Also, if
any of the mask bits are set, it reads data from the Scan Chain register.
RUNTEST delay msec
As the previous instruction loads the input and samples the output, this instruction is used
to apply the input combination to the DUT and run the test for delay msec.
For example, the input text file for the design described in Section 2, and the waveform
in Fig.3 will be written as follows:

reset
clock
A
B
Time

t0

t1

t2

t3

Figure 3: Example Waveform

# @t0
SDR 34 TDI(200000000)
RUNTEST 1 MSEC
# @t1
SDR 34 TDI(051267A5C)
RUNTEST 1 MSEC
# @t2
SDR 34 TDI(151267A5C)
RUNTEST 1 MSEC
# @t3
SDR 34 TDI(051267A5C)
RUNTEST 1 MSEC

16 TDO(0000) MASK(0000)

16 TDO(0000) MASK(0000)

16 TDO(0000) MASK(0000)

16 TDO(CB82) MASK(FFFF)

Note that you can use # for a single-line comment.

Hardware connections

The physical connections among the host PC, microcontroller board and the user module(CPLD) are specified as follows. The host PC is connected to the microcontroller board
through USB cable. Use 8-Pin Female Connector for connecting microcontroller board to
CPLD.
Two different microcontroller boards are available, Tiva-C and Ptx-128. You can use
any one of the two.

4.1
4.1.1

Using Tiva-C microcontroller

Host-PC with Tiva-C

Tiva-C has 2 ports for USB connection. Make sure you use the Device Port as encircled in
Fig.4.

Figure 4: Tiva-C Evaluation Board (taken from [2])

4.1.2

CPLD with Tiva-C

Make the connections as shown in Table 2 and Fig.5.

CPLD Pin
Header 0: 3
Header 0: 5
Header 0: 7
Header 0: 13
Header 0: 15
Header 0: 25

Tiva-C Pin
J1:PB5
J1:PB0
J1:PB1
J1:PB4
J1:PA5
J2:GND

Function
TDO
TDI
TMS
TRST
TCLK
GND

Table 2: Hardware Connections

Figure 5: Hardware Connection between CPLD and Tiva-C using 8-PIN Female Connector

4.2
4.2.1

Using Ptx-128 microcontroller

Host-PC with Ptx-128

Use USB Cable for connection.

4.2.2

CPLD with Ptx-128

Make the connections as shown in Table 3 and Fig.6.

CPLD Pin
Header 0: 3
Header 0: 5
Header 0: 7
Header 0: 13
Header 0: 15
Header 0: 25

Ptx-128 Pin
PORTC:PC0
PORTD:PD0
PORTD:PD1
PORTD:PD4
PORTD:PD5
POWER CONNECTOR:GND
Table 3: Hardware Connections

Function
TDO
TDI
TMS
TRST
TCLK
GND

Figure 6: Hardware Connection between CPLD and Ptx-128 using 8-PIN Female Connector

Running the test

5.1

Installation

1. goto http://sourceforge.net/projects/pyusb/ or google Pyusb

2. Download 1.0.0 version and extract it to any folder
3. Open folder and you will see docs,usb,setup.py etc. file and folder.
4. Open terminal, goto the present directory and run following two commands:
(a) Install Python and other dependencies:
sudo apt-get install python libusb-1.0.0
(b) Install PyUSB:
sudo python setup.py install

5.2

Running the Python script

After the installation run the scan.py script with the following command.
For Tiva-C : sudo python scan.py input file output file tiva
For Ptx-128: sudo python scan.py input file output file ptx
Where the input file should contain all the commands to be executed as described in
Section 3, output file should be an empty file for storing the results back.

5.3

Seeing Results

The output file lists the results under the following headers
Expected Output
Received Output
Remarks
============================================
The first column under Expected Output lists the outputs that are expected from the
CPLD, the second column under Received Output lists the bits received from the CPLD,
and the third column under Remarks specifies the result. If the Expected Output matches
with the Received Output, the Remark is Success, and if not, the Remark is Failure.
For example, the correct result of the example input text file described in Section 3, and
the waveform in Fig.3 will be as follows:
Expected Output
Received Output
Remarks
============================================
1100101110000010
1100101110000010
Success

References
[1] Debapratim Ghosh. Using quartus ii and urjtag for krypton, 2013.
[2] Texas Instruments. Tiva-c series tm4c123g launchpad evaluation board users guide,
2013. [Online, accessed 21-October-2015].
[3] Titto Thomas. Scan chain based testing mechanism for digital systems, 2015.

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