SoC design using RISC-V based core and 10-bit DAC Sky130 IP

The purpose of this project is to integrate rvmyth (RISC-V) with digital to analog converter (DAC) and perform PNR using end-to-end open-source EDA tools. It also discusses the steps to modify the current IP layouts inorder to ensure its acceptance by the EDA tools.

Methodology

First, we will need to generate a verilog module for DAC and obtain the analog output reciprocation for some arbitrary digital inputs to test it. Later we will give the digital output of rvmyth to the 10-bit DAC by creating an interface between the two analog and digital blocks.

Required Tools

iverilog and gtkwave

Steps to follow

Install iverilog and gtkwave
Simulate rvmyth using the following steps:
1. git clone https://github.com/kunalg123/rvmyth/
2. cd rvmyth
3. iverilog mythcore_test.v tb_mythcore_test.v
4. ./a.out
5. gtkwave tb_mythcore_test.vcd

10-bit digital codes observed at the output of rvmyth.

Design the 10-bit DAC using the given specs in verilog and test for its correct functionality.
1. iverilog avsddac.v avsddac_tb_test.v
2. ./a.out
3. gtkwave avsddac_tb_test.vcd

DAC Output:

Finally integrate both rvymth and DAC using a Top level module and test it to verify the correctness of the integration.
1. iverilog rvmyth_avsddac.v rvmyth_avsddac_TB.v
2. ./a.out
3. gtkwave rvmyth_avsddac.vcd

out [9:0] --> rvymth 10-bit digital output

D [9:0] --> DAC 10-bit digital input

Out --> DAC analog output`

Further steps require openLANE and skywater130 PDK.

OpenLANE and sky130 installation

OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault,SPEF-Extractor and custom methodology scripts for design exploration and optimization. The OpenLANE and sky130 installation can be done by following the steps in this repository https://github.com/nickson-jose/openlane_build_script.
More information on OpenLANE can be found in this repository https://github.com/efabless/openlane .
After finishing off the installation, the first step in the design flow is to synthesize the generated RTL code.

Synthesis in yosys

In OpenLANE the RTL synthesis is performed by yosys.
The technolgy mapping is performed by abc.
Finally, the timing reports are generated for the resulting synthesized netlist by OpenSTA.

Inorder to perform synthesis, you will need:

Verilog file(.v) of the avsddac and its LIB(.lib) file.
To generate the LIB file run the perl script given on this link, with the command given below.

perl verilog_to_lib.pl avsddac.v avsddac

To perform synthesys in yosys --> Just type yosys in linux shell. --> Then follow the script

The synthesized netlist can be found here.

--> Now, simulate the generated netlist in iverilog & gtkwave to compare the pre - synthesis and post- synthesis simulations.

For that you'd need to create a verilog code for gate level simulation that must include the synthesized netlist verilog file obtained from yosys. The files necessary for pre and post synthesis can be found here.

Both pre-synth and post-synth simulations must give out the same output.

Pre -synthesis Simulation:

Post-synthesis Simulation: To perform post synthesis you also need to include verilog files for standard cell library.

iverilog -o gls.v sky130_fd_sc_hd.v primitives.v
./a.out
gtkwave gls.vcd

SoC Physical Design

Inorder to carry out the physical design flow, following input files are required to get started:

Top level verilog module : rvmyth_avsddac.v
LIB file : avsddac.lib
LEF file : avsddac.lef

Obtaining IP

The Digital to Analog Converter (DAC) for sky130 techonology is available in this repository, it contains all the magic layout files which will be subsequently required for obtaining the avsddac.lef for the 10-bit DAC. The magic layout files can be found here.

Using the magic layout files and the tech file i.e. sky130A.tech lef file can be generated after implementing certain modifications to the layout.

Obtaining verilog files

The project related design files can be found here.

Generating LEF file

i. Firstly, git clone this repository https://github.com/vsdip/avsddac_3v3_sky130_v1.git

git clone https://github.com/vsdip/avsddac_3v3_sky130_v1.git

ii. Then open Magic Tool using the below command:

magic -T `/sky130A.tech ~/10bitdac_cap_layout_design.mag

Two windows will open; the layout window and the tckon window.

In the layout window press 'v' on the keyboard for the full view or go to the option Window ---> Full view.

now, using left and right mouse click make a box around the layout:

then, go to : Cell ---> Expand to see the complete layout of 10-bit DAC:

Now, using the following command in tckon window dump out the .lef file :

lef write avsddac.lef

Limitations of current IP Layouts

After opening the lef file ( avsddac.lef ) it is observed that there are no pins descriptions available for the design, instead only the labels are present in the layout window. Also certain fields which must be present in the lef file are found missing. Hence, the first task is to convert the labels into pins by carefully modifying the layout.

These changes must be executed else the LEF file would not be accepted by the PnR tools.

Resolving the pin issue

Before beginning with the layout modifications, one must be familiar with the following useful shortcut keys in magic:

s : To select a particular layer. ( Place the cursor on that layer and type s )
z : To zoom in the layout.
Shift+z : To zoom out the layout.
g : To enable grid option.
Use the arrow keys to navigate across the layout.

To convert the labels into ports, select that particular layer where the label is present and then go to the Edit-->Text. A text helper window opens up in which specify the following field :

Text string: Here give the desirable port name for the selected layer.
Size (um) : This specifies the size of the port name.
Attach to layer : Here check the sticky, uncheck the default and specify the layer. (here the selected layer is locali)
Port : Check the enable option.

Apply and Okay

To verify if the port is made, in the tckon window:

port name

Similarly repeat the above steps for all the required pins.

Again dump out the LEF file by:

lef write avsddac.lef

Other important fields of LEF file

In addition to the making of ports, there are certain other fields which are to be included in the LEF file for it to be accepted by the openlane tool. Use the tckon window to add the following commands:

CLASS CORE

 property LEFclass CORE

DIRECTION
- For input pins:
```
port class input
```
- For output pins:
```
port class output
```
- For power and ground pins:
```
port class inout
```

USE

For power pin:
```
port use power
```
For ground pin:
```
port use ground
```
For other pins:
```
port use signal
```

Experiments with openlane and sky130

Adding a new project

In the designs directory, create a folder with the name of the project.

cd designs
mkdir rvmyth_avsddac

Setting up the new project

Go to the ~/openlane_working_dir/openlane and execute the following commands:

export PDK_ROOT=<absolute path to where skywater-pdk and open_pdks reside>

docker run -it -v $(pwd):/openLANE_flow -v $PDK_ROOT:$PDK_ROOT -e PDK_ROOT=$PDK_ROOT -u $(id -u $USER):$(id -g $USER) openlane:rc6

 ./flow.tcl -design rvmyth_avsddac -init_design_config

This creates a config.tcl file with default settings, here the setting of environment variables will be done. This file also contains the reason for some configurations as comments.

The information about the environment variables and their default values can be found here.

Adding the input files

Verilog files

The .v and .libs input files are to added under ~/designs/rvmyth_avsddac/src/verilog directory.

The top level module is rvmyth_avsddac.v.
The verilog file of the macro is avsddac.v.
mythcore_test.v , sp_verilog.vh , clk_gate.v , mythcore_test_gen.v , sandpiper_gen.vh ,sandpiper.vh are the files to be included in the design.

LEF file

The LEF file avsddac.v obtained must be included in ~/designs/rvmyth_avsddac/src/lef directory.

The Flow

To harden the macro, the interactive flow in openlane is used:

Go to the ~/openlane_working_dir/openlane and execute the following:

export PDK_ROOT=<absolute path to where skywater-pdk and open_pdks reside>

docker run -it -v $(pwd):/openLANE_flow -v $PDK_ROOT:$PDK_ROOT -e PDK_ROOT=$PDK_ROOT -u $(id -u $USER):$(id -g $USER) openlane:rc6

A bash window will open where the interactive flow is executed.

 ./flow.tcl -design rvmyth_avsddac -interactive

Setting up the Flow

Execute the following commands:

package require openlane 0.9

prep -design rvmyth_avsddac -overwrite

Adding the LEF file for macro:

set lefs 	 [glob $::env(DESIGN_DIR)/src/lef/*.lef]

add_lefs -src $lefs

SYNTHESIS

run_synthesis

The output file can be found here.

FLOORPLANNING

init_floorplan

After floorplanning, the layout can be viewed in magic using the merged.lef and the DEF file. The DEF file can be found here.

magic -T ~/sky130A.tech lef read ~/merged.lef def read rvmyth_avsddac.floorplan.def

IO Placement

place_io

Placement

global_placement_or

detailed_placement

tap_decap_or

detailed_placement

After final placement, the layout can be viewed in magic using merged LEF and DEF file. The DEF file can be found here.

magic -T ~/sky130A.tech lef read ~/merged.lef def read rvmyth_avsddac.placement.def

Key points to remember

Keep the design name and verilog file name same as the top module name, else there will be some errors during synthesis.
Make sure that the port names are same as the ones used in the RTL code, else the floorplanning stage would prompt an error.

Future work

To complete the PNR flow proceeding with routing and completing the SoC design with final layout generation. (The-OpenROAD-Project/OpenLane#426)

References

Acknowledgement

Kunal Ghosh, Founder, VSD Corp. Pvt. Ltd
Steve Hoover, Founder, Redwood EDA
Shivani Shah, IIIT Bangalore
Shalini Kanna, Master of Science in Computer Engineering, University of Massachusetts Lowell, Lowell,MA, USA

Contributors

Mansi Mohapatra, M.Tech VLSI Design, Indira Gandhi Delhi Technical University for Women (IGDTUW)
Mili Anand, M.Tech VLSI Design, Indira Gandhi Delhi Technical University for Women (IGDTUW)
Kunal Ghosh, Founder, VSD Corp. Pvt. Ltd

Name		Name	Last commit message	Last commit date
Latest commit History 247 Commits
LEF		LEF
LIB		LIB
OpenSTA		OpenSTA
design		design
iverilog		iverilog
openlane		openlane
README.md		README.md
rvmyth_avsddac.ys		rvmyth_avsddac.ys

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SoC design using RISC-V based core and 10-bit DAC Sky130 IP

Table of contents

Problem Statement

DAC Specs Provided