Repository regarding the Practical Works of the Computer Organization discipline

DOOM based cpu benchmark made for RISC-V emulators

VHDL_Lab Course

datapath risc-v with pipeline

A project dedicated to building LLVM toolchain for 32-bit RISCV embedded targets.

LZ4 decoder in assembly for RiscV RV32IC

Programs for the FOMU, DE10NANO and ULX3S FPGA boards, written in Silice https://github.com/sylefeb/Silice

Design implementation of the RV32I Core in Verilog HDL with Zicsr extension

Simple risc-v emulator, able to run linux, written in C.

RISC-V Assembler and Runtime Simulator

RISC-V Guide. Learn all about the RISC-V computer architecture along with the Development Tools and Operating Systems to develop on RISC-V hardware.

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.