prefix-adder

Here are 3 public repositories matching this topic...

neeraj1397 / Performance-Analysis-of-Parallel-Prefix-Adders-Using-Zynq-7000-APSoC

Performed a comparative study of Parallel Prefix Adders using Verilog HDL on Zynq-7000 APSoC (PL) from XIlinx. Circuits are simulated, synthesized and implemented using Vivado Design Suite.

fpga verilog vivado prefix-tree adder xilinx-fpga xilinx-vivado zynq-7000 han-carlson brent-kung kogge-stone-adder ladner-fischer carry-look-ahead-adder ripple-carry-adder carry-save-adder prefix-adder

Updated Apr 13, 2021
Verilog

ParimalaS27 / Parallel-Prefix-Adder-8bit-UE19CS206-DDCOLab

Star

This repo consists of the iverilog implementation of a Parallel Prefix adder - 8bit (I/P - O/P). This was done as a part of a project Under UE19CS206 - Digital Design and Computer Organization Laboratory Course at PES University.

verilog prefix icarus-verilog 8bit iverilog parallel-prefixsum prefix-adder ddco

Updated Jan 6, 2021
Verilog

majabojarska / verilog-prefix-adder

Star

6-bit prefix adder implemented via Verilog HDL.

verilog qflow prefix-adder

Updated Jun 11, 2020
Verilog

Improve this page

Add a description, image, and links to the prefix-adder topic page so that developers can more easily learn about it.

Curate this topic

Add this topic to your repo

To associate your repository with the prefix-adder topic, visit your repo's landing page and select "manage topics."

Learn more

Provide feedback

Saved searches

Use saved searches to filter your results more quickly