Lightweight and performant dynamic binary translation for RISC–V code on x86–64
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Updated
Mar 29, 2021 - C++
Lightweight and performant dynamic binary translation for RISC–V code on x86–64
JIT-accelerated RISC-V instruction set simulator
A System Level RISCV32 Emulator Over x86_64: capable of booting RISCV Linux
Ratel - a new framework for instruction-level interposition on enclaved applications
Dynamic binary translator from ARM Cortex-M architecture to WebAssembly. University project.
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