Chisel Designer's Library

Superscalar OoO RISCV processor written in Chisel

Przykład użycia generatora Chisel

RISC-V 1 and 5-stage CPUs Described in Chisel for Implementation in an Altera FPGA

Misc sysdig chisels

Chisel RTL demo with blinking and interactivity. Use https://github.com/ucb-bar/chisel-template for a blank Chisel project template

shadowsocks server over chisel.

Worpress theme starter with Chisel and Timber

Final project of the Network Management course of the Computer Science Bachelor's Degree @ University of Pisa

A template for building new projects/platforms using the BOOM core.

Collection of utilities to simplify FPGA accelerator design

This is my graduation project, a simple processor soft core, which implements RV32I ISA.

Make writing trivial inst{ruction,rumentation}s for RocketChip as simple as writing the C code

Support Repository of "How to make RISC-V Microcomputer using FPGA for programmer"

『プログラマのためのFPGAによるRISC-Vマイコンの作り方』のサポート・リポジトリ

Declarative containerized chisel for punching holes through networks

This repo contains the files of the RV32I Single-cycle processor in CHISEL.

Boilerplate for a full project with chisel and a DE0 Nano

Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel