Custom 64-bit pipelined RISC processor
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Updated
Jul 18, 2024 - VHDL
Custom 64-bit pipelined RISC processor
Trabalho de Organização e Arquitetura de Computadores, UnB - 2020/2
Dual-core 16-bit RISC processor
4 bits ALU with 2 entries of selection using structural vhdl
A simulation to PDP-11 microprocessor with modelsim, The design is a micro-programmed based with an average of 9 clock cycles per instruction.
Computer Architecture Laboratory Material and Reports
Some of small codes and implementation of modules in Computer Aided Design in VHDL by ActiveHDL
8-bit MISC processor with pipelining
Accumulator-based 4-bit processor
This Repository contains custom-defined (AUBIE) processor components as defined by the ModelSimPE VHDL([Very High Speed Integrated Circuit] Hardware Description Language) Simulation Environment
My first processor written in HDL language
Simple ALU in VHDL
Computer Architecture
16-bit RISC processor with von Neumann architecture
ALU is the core of all operations, it elaborate two operands and performs logical and arithmetic operations based on the instruction passed to it by the CU.
This is an implementation of a floating point numbers ALU, according to IEEE-754 standard
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