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[bug] [arm]： pfr0_el1.gic will never be true because of the value is used before it can be initiated

arch-armThe ARM ISAThe ARM ISA

bug

Status: Open.

#1941 In gem5/gem5;

· gxflying opened on Jan 21, 2025

Spinlock in SE mode when switching the CPU on RISC-V architecture.

bug

Status: Open.

#1937 In gem5/gem5;

· pepesy00 opened on Jan 17, 2025

Make resource download reason more explicit

enhancement

resourcesThe gem5 Resources. Auxiliary resources for simulationThe gem5 Resources. Auxiliary resources for simulation

Status: Open.

#1934 In gem5/gem5;

· powerjg opened on Jan 16, 2025

"uniform_random" synthetic traffic simulation of ruby garnet3.0 is not random under version v24.0.0.1

bug

Status: Open.

#1919 In gem5/gem5;

· Lzingnow opened on Jan 10, 2025

[bug] using a private method of Random in util/tlm/examples/master_port/traffic_generator.c

bug

Status: Open.

#1908 In gem5/gem5;

· gxflying opened on Jan 8, 2025

Potential memory leaks

bug

Status: Open.

#1903 In gem5/gem5;

· powerjg opened on Jan 6, 2025

TlmToGem5 protocol error

bug

Status: Open.

#1899 In gem5/gem5;

· GkyHub opened on Jan 6, 2025

Better error handling for wrong address ranges

enhancement

Status: Open.

#1871 In gem5/gem5;

· erin-le opened on Dec 18, 2024

Implement PCIe architecture model

enhancement

Status: Open.

#1862 In gem5/gem5;

· clemdiep opened on Dec 16, 2024

[RISC-V] Incorrect results on latest stable branch (commit 63d25922)

bug

Status: Open.

#1856 In gem5/gem5;

· psharath1 opened on Dec 13, 2024

Large physical memory requirements because physical pages are not reallocated in SE mode

bug

Status: Open.

#1824 In gem5/gem5;

· nmosier opened on Nov 29, 2024

NVM config script (sweep_hybrid.py) throws fatal error when running.

bug

Status: Open.

#1805 In gem5/gem5;

· mostafadx opened on Nov 24, 2024