Unlike in the C parser, "struct" in SystemVerilog refers to declarations
of struct/union *objects*, not definitions of struct/union "types".
The same goes for enum declarations.

Unlike in C, there is no way to define a "struct type" (or union/enum)
except by using a typedef.  Therefore, all "structure definitions" use
typedef; otherwise they're simply declaring struct objects.

This puts the ctags "struct" and "enum" in the same category as "net" or
"register"; the tm_parser should reflect this.

- Put Enums on the same tm_parser group as Structs and Unions, separate
  from Typedefs.
- Change the icon for the Structs/Unions/Enums to "three gray boxes"
  (OTHER), so that it resembles an "aggregate of multiple signals" or
  "a grayed-out (anonymous/signal-ified) type".

Currently, for a Verilog line like `a_module inst (clk, d, q);`,
ctags will emit both an "instance" tag and a "module" reference,
which Geany incorrectly interprets as a module definition.

Disable ctags roles for Verilog (and SystemVerilog) modules to prevent
this.