Fix asymmetric SPI transfers

ftdi-rs · Oct 30, 2023 · a07db8d · a07db8d
1 parent fca0b1f
commit a07db8d
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Showing 3 changed files with 9 additions and 2 deletions.
diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -11,6 +11,9 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 ### Changed
 - Changed `ErrorKind::I2cNoAck` to have an inner type of `eh1::i2c::NoAcknowledgeSource`.
 
+### Fixed
+- Fixed asymmetric SPI transfers (read size > write size) with `eh1`.
+
 ## [0.17.0] - 2023-08-15
 ### Changed
 - Updated the alpha release of `embedded-hal` from `1.0.0-alpha.11` to `1.0.0-rc.1`.

diff --git a/examples/spi-eh1-loopback.rs b/examples/spi-eh1-loopback.rs
@@ -44,7 +44,6 @@ fn main() {
         // bytes are still in the read buffer, which breaks tests afterwards.
         // Spi::flush(&mut spi) doesn't help either
 
-        /*
         // --- Asymmetric transfer (Read more than we write) ---
         print!("Starting asymetric transfer (read > write)...");
         let mut read: [u8; 4] = [0x00; 4];
@@ -55,7 +54,6 @@ fn main() {
         assert_eq!(read[2], 0x00u8);
         println!(" SUCCESS");
         sleep(delay);
-        */
 
         // --- Symmetric transfer with huge buffer ---
         // Only your RAM is the limit!

diff --git a/src/spi.rs b/src/spi.rs
@@ -279,6 +279,12 @@ where
         lock.ft.send(cmd.as_slice())?;
         lock.ft.recv(read)?;
 
+        let remain: usize = write.len().saturating_sub(read.len());
+        if remain != 0 {
+            let mut remain_buf: Vec<u8> = vec![0; remain];
+            lock.ft.recv(&mut remain_buf)?;
+        }
+
         Ok(())
     }
 }