V1_4_6b changes. #451
Merged
V1_4_6b changes. #451
Conversation
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
adding kernel version warning for SDAccel runtime setup Adding instance placement group documentation to virtual ethernet application guide.
kristopk
approved these changes
Feb 2, 2019
kyyalama2
pushed a commit
that referenced
this pull request
May 24, 2022
* sdk/apps/virtual-ethernet: added sdk/apps directory for virtual ethernet
* Update Virtual_Ethernet_Application_Guide.md
* Update Virtual_Ethernet_Application_Guide.md
* sdk/apps/virtual-ethernet: pktgen updates
* use dpdk-v18.0.5 and the latest compatible version of pktgen
* pktgen patches for ENA
* pktgen memory leak fixes
* Update Virtual_Ethernet_Application_Guide.md
* Update Virtual_Ethernet_Application_Guide.md
* sdk/apps/virtual-ethernet: modified the VID/DIDs for the SDE loopback CL
* Porting CL_SDE from chimera to github CL examples. Adding ILA ips needed under CL.
Full validation not yet done. commiting for license header review.
new file: cl_sde/build/constraints/cl_pnr_user.xdc
new file: cl_sde/build/constraints/cl_synth_user.xdc
new file: cl_sde/build/scripts/aws_build_dcp_from_cl.sh
new file: cl_sde/build/scripts/create_dcp_from_cl.tcl
new file: cl_sde/build/scripts/encrypt.tcl
new file: cl_sde/build/scripts/synth_cl_sde.tcl
new file: cl_sde/design/axi_prot_chk.sv
new file: cl_sde/design/cl_id_defines.vh
new file: cl_sde/design/cl_sde.sv
new file: cl_sde/design/cl_sde_srm.sv
new file: cl_sde/design/sde.sv
new file: cl_sde/design/sde_c2h.sv
new file: cl_sde/design/sde_c2h_axis.sv
new file: cl_sde/design/sde_c2h_buf.sv
new file: cl_sde/design/sde_c2h_cfg.sv
new file: cl_sde/design/sde_c2h_data.sv
new file: cl_sde/design/sde_desc.sv
new file: cl_sde/design/sde_h2c.sv
new file: cl_sde/design/sde_h2c_axis.sv
new file: cl_sde/design/sde_h2c_buf.sv
new file: cl_sde/design/sde_h2c_cfg.sv
new file: cl_sde/design/sde_h2c_data.sv
new file: cl_sde/design/sde_pkg.sv
new file: cl_sde/design/sde_pm.sv
new file: cl_sde/design/sde_ps.sv
new file: cl_sde/design/sde_ps_acc.sv
new file: cl_sde/design/sde_wb.sv
new file: cl_sde/ip/ila_axi4/doc/ila_v6_2_changelog.txt
new file: cl_sde/ip/ila_axi4/hdl/blk_mem_gen_v8_3_vhsyn_rfs.vhd
new file: cl_sde/ip/ila_axi4/hdl/fifo_generator_v13_1_vhsyn_rfs.vhd
new file: cl_sde/ip/ila_axi4/hdl/ila_v6_2_syn_rfs.v
new file: cl_sde/ip/ila_axi4/hdl/ltlib_v1_0_vl_rfs.v
new file: cl_sde/ip/ila_axi4/hdl/verilog/ila_v6_2_5_ila_in.vh
new file: cl_sde/ip/ila_axi4/hdl/verilog/ila_v6_2_5_ila_lib_fn.vh
new file: cl_sde/ip/ila_axi4/hdl/verilog/ila_v6_2_5_ila_lparam.vh
new file: cl_sde/ip/ila_axi4/hdl/verilog/ila_v6_2_5_ila_param.vh
new file: cl_sde/ip/ila_axi4/hdl/verilog/ila_v6_2_5_ila_ver.vh
new file: cl_sde/ip/ila_axi4/hdl/verilog/ltlib_v1_0_0_lib_fn.vh
new file: cl_sde/ip/ila_axi4/hdl/verilog/ltlib_v1_0_0_ver.vh
new file: cl_sde/ip/ila_axi4/hdl/verilog/xsdbm_v3_0_0_bs.vh
new file: cl_sde/ip/ila_axi4/hdl/verilog/xsdbm_v3_0_0_bs_core.vh
new file: cl_sde/ip/ila_axi4/hdl/verilog/xsdbm_v3_0_0_bs_core_vec.vh
new file: cl_sde/ip/ila_axi4/hdl/verilog/xsdbm_v3_0_0_bs_ports.vh
new file: cl_sde/ip/ila_axi4/hdl/verilog/xsdbm_v3_0_0_bs_vec.vh
new file: cl_sde/ip/ila_axi4/hdl/verilog/xsdbm_v3_0_0_bsid_ports.vh
new file: cl_sde/ip/ila_axi4/hdl/verilog/xsdbm_v3_0_0_bsid_vec_ports.vh
new file: cl_sde/ip/ila_axi4/hdl/verilog/xsdbm_v3_0_0_i2x.vh
new file: cl_sde/ip/ila_axi4/hdl/verilog/xsdbm_v3_0_0_icn.vh
new file: cl_sde/ip/ila_axi4/hdl/verilog/xsdbm_v3_0_0_id_map.vh
new file: cl_sde/ip/ila_axi4/hdl/verilog/xsdbm_v3_0_0_id_vec_map.vh
new file: cl_sde/ip/ila_axi4/hdl/verilog/xsdbm_v3_0_0_in.vh
new file: cl_sde/ip/ila_axi4/hdl/verilog/xsdbm_v3_0_0_sl_prt_map.vh
new file: cl_sde/ip/ila_axi4/hdl/verilog/xsdbs_v1_0_2_i2x.vh
new file: cl_sde/ip/ila_axi4/hdl/verilog/xsdbs_v1_0_2_in.vh
new file: cl_sde/ip/ila_axi4/hdl/xsdbm_v3_0_vl_rfs.v
new file: cl_sde/ip/ila_axi4/hdl/xsdbs_v1_0_vl_rfs.v
new file: cl_sde/ip/ila_axi4/ila_axi4.veo
new file: cl_sde/ip/ila_axi4/ila_axi4.xci
new file: cl_sde/ip/ila_axi4/ila_axi4.xml
new file: cl_sde/ip/ila_axi4/ila_axi4_ooc.xdc
new file: cl_sde/ip/ila_axi4/ila_v6_2/constraints/ila.xdc
new file: cl_sde/ip/ila_axi4/ila_v6_2/constraints/ila_impl.xdc
new file: cl_sde/ip/ila_axi4/sim/ila_axi4.v
new file: cl_sde/ip/ila_axi4/synth/ila_axi4.v
new file: cl_sde/ip/ila_axi4_512/doc/ila_v6_2_changelog.txt
new file: cl_sde/ip/ila_axi4_512/hdl/blk_mem_gen_v8_3_vhsyn_rfs.vhd
new file: cl_sde/ip/ila_axi4_512/hdl/fifo_generator_v13_1_vhsyn_rfs.vhd
new file: cl_sde/ip/ila_axi4_512/hdl/ila_v6_2_syn_rfs.v
new file: cl_sde/ip/ila_axi4_512/hdl/ltlib_v1_0_vl_rfs.v
new file: cl_sde/ip/ila_axi4_512/hdl/verilog/ila_v6_2_5_ila_in.vh
new file: cl_sde/ip/ila_axi4_512/hdl/verilog/ila_v6_2_5_ila_lib_fn.vh
new file: cl_sde/ip/ila_axi4_512/hdl/verilog/ila_v6_2_5_ila_lparam.vh
new file: cl_sde/ip/ila_axi4_512/hdl/verilog/ila_v6_2_5_ila_param.vh
new file: cl_sde/ip/ila_axi4_512/hdl/verilog/ila_v6_2_5_ila_ver.vh
new file: cl_sde/ip/ila_axi4_512/hdl/verilog/ltlib_v1_0_0_lib_fn.vh
new file: cl_sde/ip/ila_axi4_512/hdl/verilog/ltlib_v1_0_0_ver.vh
new file: cl_sde/ip/ila_axi4_512/hdl/verilog/xsdbm_v3_0_0_bs.vh
new file: cl_sde/ip/ila_axi4_512/hdl/verilog/xsdbm_v3_0_0_bs_core.vh
new file: cl_sde/ip/ila_axi4_512/hdl/verilog/xsdbm_v3_0_0_bs_core_vec.vh
new file: cl_sde/ip/ila_axi4_512/hdl/verilog/xsdbm_v3_0_0_bs_ports.vh
new file: cl_sde/ip/ila_axi4_512/hdl/verilog/xsdbm_v3_0_0_bs_vec.vh
new file: cl_sde/ip/ila_axi4_512/hdl/verilog/xsdbm_v3_0_0_bsid_ports.vh
new file: cl_sde/ip/ila_axi4_512/hdl/verilog/xsdbm_v3_0_0_bsid_vec_ports.vh
new file: cl_sde/ip/ila_axi4_512/hdl/verilog/xsdbm_v3_0_0_i2x.vh
new file: cl_sde/ip/ila_axi4_512/hdl/verilog/xsdbm_v3_0_0_icn.vh
new file: cl_sde/ip/ila_axi4_512/hdl/verilog/xsdbm_v3_0_0_id_map.vh
new file: cl_sde/ip/ila_axi4_512/hdl/verilog/xsdbm_v3_0_0_id_vec_map.vh
new file: cl_sde/ip/ila_axi4_512/hdl/verilog/xsdbm_v3_0_0_in.vh
new file: cl_sde/ip/ila_axi4_512/hdl/verilog/xsdbm_v3_0_0_sl_prt_map.vh
new file: cl_sde/ip/ila_axi4_512/hdl/verilog/xsdbs_v1_0_2_i2x.vh
new file: cl_sde/ip/ila_axi4_512/hdl/verilog/xsdbs_v1_0_2_in.vh
new file: cl_sde/ip/ila_axi4_512/hdl/xsdbm_v3_0_vl_rfs.v
new file: cl_sde/ip/ila_axi4_512/hdl/xsdbs_v1_0_vl_rfs.v
new file: cl_sde/ip/ila_axi4_512/ila_axi4_512.veo
new file: cl_sde/ip/ila_axi4_512/ila_axi4_512.xci
new file: cl_sde/ip/ila_axi4_512/ila_axi4_512.xml
new file: cl_sde/ip/ila_axi4_512/ila_axi4_512_ooc.xdc
new file: cl_sde/ip/ila_axi4_512/ila_v6_2/constraints/ila.xdc
new file: cl_sde/ip/ila_axi4_512/ila_v6_2/constraints/ila_impl.xdc
new file: cl_sde/ip/ila_axi4_512/sim/ila_axi4_512.v
new file: cl_sde/ip/ila_axi4_512/synth/ila_axi4_512.v
new file: cl_sde/ip/ila_axis/doc/ila_v6_2_changelog.txt
new file: cl_sde/ip/ila_axis/hdl/blk_mem_gen_v8_3_vhsyn_rfs.vhd
new file: cl_sde/ip/ila_axis/hdl/fifo_generator_v13_1_vhsyn_rfs.vhd
new file: cl_sde/ip/ila_axis/hdl/ila_v6_2_syn_rfs.v
new file: cl_sde/ip/ila_axis/hdl/ltlib_v1_0_vl_rfs.v
new file: cl_sde/ip/ila_axis/hdl/verilog/ila_v6_2_5_ila_in.vh
new file: cl_sde/ip/ila_axis/hdl/verilog/ila_v6_2_5_ila_lib_fn.vh
new file: cl_sde/ip/ila_axis/hdl/verilog/ila_v6_2_5_ila_lparam.vh
new file: cl_sde/ip/ila_axis/hdl/verilog/ila_v6_2_5_ila_param.vh
new file: cl_sde/ip/ila_axis/hdl/verilog/ila_v6_2_5_ila_ver.vh
new file: cl_sde/ip/ila_axis/hdl/verilog/ltlib_v1_0_0_lib_fn.vh
new file: cl_sde/ip/ila_axis/hdl/verilog/ltlib_v1_0_0_ver.vh
new file: cl_sde/ip/ila_axis/hdl/verilog/xsdbm_v3_0_0_bs.vh
new file: cl_sde/ip/ila_axis/hdl/verilog/xsdbm_v3_0_0_bs_core.vh
new file: cl_sde/ip/ila_axis/hdl/verilog/xsdbm_v3_0_0_bs_core_vec.vh
new file: cl_sde/ip/ila_axis/hdl/verilog/xsdbm_v3_0_0_bs_ports.vh
new file: cl_sde/ip/ila_axis/hdl/verilog/xsdbm_v3_0_0_bs_vec.vh
new file: cl_sde/ip/ila_axis/hdl/verilog/xsdbm_v3_0_0_bsid_ports.vh
new file: cl_sde/ip/ila_axis/hdl/verilog/xsdbm_v3_0_0_bsid_vec_ports.vh
new file: cl_sde/ip/ila_axis/hdl/verilog/xsdbm_v3_0_0_i2x.vh
new file: cl_sde/ip/ila_axis/hdl/verilog/xsdbm_v3_0_0_icn.vh
new file: cl_sde/ip/ila_axis/hdl/verilog/xsdbm_v3_0_0_id_map.vh
new file: cl_sde/ip/ila_axis/hdl/verilog/xsdbm_v3_0_0_id_vec_map.vh
new file: cl_sde/ip/ila_axis/hdl/verilog/xsdbm_v3_0_0_in.vh
new file: cl_sde/ip/ila_axis/hdl/verilog/xsdbm_v3_0_0_sl_prt_map.vh
new file: cl_sde/ip/ila_axis/hdl/verilog/xsdbs_v1_0_2_i2x.vh
new file: cl_sde/ip/ila_axis/hdl/verilog/xsdbs_v1_0_2_in.vh
new file: cl_sde/ip/ila_axis/hdl/xsdbm_v3_0_vl_rfs.v
new file: cl_sde/ip/ila_axis/hdl/xsdbs_v1_0_vl_rfs.v
new file: cl_sde/ip/ila_axis/ila_axis.veo
new file: cl_sde/ip/ila_axis/ila_axis.xci
new file: cl_sde/ip/ila_axis/ila_axis.xml
new file: cl_sde/ip/ila_axis/ila_axis_ooc.xdc
new file: cl_sde/ip/ila_axis/ila_v6_2/constraints/ila.xdc
new file: cl_sde/ip/ila_axis/ila_v6_2/constraints/ila_impl.xdc
new file: cl_sde/ip/ila_axis/sim/ila_axis.v
new file: cl_sde/ip/ila_axis/synth/ila_axis.v
new file: cl_sde/ip/ila_sde_c2h_buf/doc/ila_v6_2_changelog.txt
new file: cl_sde/ip/ila_sde_c2h_buf/hdl/blk_mem_gen_v8_3_vhsyn_rfs.vhd
new file: cl_sde/ip/ila_sde_c2h_buf/hdl/fifo_generator_v13_1_vhsyn_rfs.vhd
new file: cl_sde/ip/ila_sde_c2h_buf/hdl/ila_v6_2_syn_rfs.v
new file: cl_sde/ip/ila_sde_c2h_buf/hdl/ltlib_v1_0_vl_rfs.v
new file: cl_sde/ip/ila_sde_c2h_buf/hdl/verilog/ila_v6_2_5_ila_in.vh
new file: cl_sde/ip/ila_sde_c2h_buf/hdl/verilog/ila_v6_2_5_ila_lib_fn.vh
new file: cl_sde/ip/ila_sde_c2h_buf/hdl/verilog/ila_v6_2_5_ila_lparam.vh
new file: cl_sde/ip/ila_sde_c2h_buf/hdl/verilog/ila_v6_2_5_ila_param.vh
new file: cl_sde/ip/ila_sde_c2h_buf/hdl/verilog/ila_v6_2_5_ila_ver.vh
new file: cl_sde/ip/ila_sde_c2h_buf/hdl/verilog/ltlib_v1_0_0_lib_fn.vh
new file: cl_sde/ip/ila_sde_c2h_buf/hdl/verilog/ltlib_v1_0_0_ver.vh
new file: cl_sde/ip/ila_sde_c2h_buf/hdl/verilog/xsdbm_v3_0_0_bs.vh
new file: cl_sde/ip/ila_sde_c2h_buf/hdl/verilog/xsdbm_v3_0_0_bs_core.vh
new file: cl_sde/ip/ila_sde_c2h_buf/hdl/verilog/xsdbm_v3_0_0_bs_core_vec.vh
new file: cl_sde/ip/ila_sde_c2h_buf/hdl/verilog/xsdbm_v3_0_0_bs_ports.vh
new file: cl_sde/ip/ila_sde_c2h_buf/hdl/verilog/xsdbm_v3_0_0_bs_vec.vh
new file: cl_sde/ip/ila_sde_c2h_buf/hdl/verilog/xsdbm_v3_0_0_bsid_ports.vh
new file: cl_sde/ip/ila_sde_c2h_buf/hdl/verilog/xsdbm_v3_0_0_bsid_vec_ports.vh
new file: cl_sde/ip/ila_sde_c2h_buf/hdl/verilog/xsdbm_v3_0_0_i2x.vh
new file: cl_sde/ip/ila_sde_c2h_buf/hdl/verilog/xsdbm_v3_0_0_icn.vh
new file: cl_sde/ip/ila_sde_c2h_buf/hdl/verilog/xsdbm_v3_0_0_id_map.vh
new file: cl_sde/ip/ila_sde_c2h_buf/hdl/verilog/xsdbm_v3_0_0_id_vec_map.vh
new file: cl_sde/ip/ila_sde_c2h_buf/hdl/verilog/xsdbm_v3_0_0_in.vh
new file: cl_sde/ip/ila_sde_c2h_buf/hdl/verilog/xsdbm_v3_0_0_sl_prt_map.vh
new file: cl_sde/ip/ila_sde_c2h_buf/hdl/verilog/xsdbs_v1_0_2_i2x.vh
new file: cl_sde/ip/ila_sde_c2h_buf/hdl/verilog/xsdbs_v1_0_2_in.vh
new file: cl_sde/ip/ila_sde_c2h_buf/hdl/xsdbm_v3_0_vl_rfs.v
new file: cl_sde/ip/ila_sde_c2h_buf/hdl/xsdbs_v1_0_vl_rfs.v
new file: cl_sde/ip/ila_sde_c2h_buf/ila_sde_c2h_buf.veo
new file: cl_sde/ip/ila_sde_c2h_buf/ila_sde_c2h_buf.xci
new file: cl_sde/ip/ila_sde_c2h_buf/ila_sde_c2h_buf.xml
new file: cl_sde/ip/ila_sde_c2h_buf/ila_sde_c2h_buf_ooc.xdc
new file: cl_sde/ip/ila_sde_c2h_buf/ila_v6_2/constraints/ila.xdc
new file: cl_sde/ip/ila_sde_c2h_buf/ila_v6_2/constraints/ila_impl.xdc
new file: cl_sde/ip/ila_sde_c2h_buf/sim/ila_sde_c2h_buf.v
new file: cl_sde/ip/ila_sde_c2h_buf/synth/ila_sde_c2h_buf.v
new file: cl_sde/ip/ila_sde_c2h_dm/doc/ila_v6_2_changelog.txt
new file: cl_sde/ip/ila_sde_c2h_dm/hdl/blk_mem_gen_v8_3_vhsyn_rfs.vhd
new file: cl_sde/ip/ila_sde_c2h_dm/hdl/fifo_generator_v13_1_vhsyn_rfs.vhd
new file: cl_sde/ip/ila_sde_c2h_dm/hdl/ila_v6_2_syn_rfs.v
new file: cl_sde/ip/ila_sde_c2h_dm/hdl/ltlib_v1_0_vl_rfs.v
new file: cl_sde/ip/ila_sde_c2h_dm/hdl/verilog/ila_v6_2_5_ila_in.vh
new file: cl_sde/ip/ila_sde_c2h_dm/hdl/verilog/ila_v6_2_5_ila_lib_fn.vh
new file: cl_sde/ip/ila_sde_c2h_dm/hdl/verilog/ila_v6_2_5_ila_lparam.vh
new file: cl_sde/ip/ila_sde_c2h_dm/hdl/verilog/ila_v6_2_5_ila_param.vh
new file: cl_sde/ip/ila_sde_c2h_dm/hdl/verilog/ila_v6_2_5_ila_ver.vh
new file: cl_sde/ip/ila_sde_c2h_dm/hdl/verilog/ltlib_v1_0_0_lib_fn.vh
new file: cl_sde/ip/ila_sde_c2h_dm/hdl/verilog/ltlib_v1_0_0_ver.vh
new file: cl_sde/ip/ila_sde_c2h_dm/hdl/verilog/xsdbm_v3_0_0_bs.vh
new file: cl_sde/ip/ila_sde_c2h_dm/hdl/verilog/xsdbm_v3_0_0_bs_core.vh
new file: cl_sde/ip/ila_sde_c2h_dm/hdl/verilog/xsdbm_v3_0_0_bs_core_vec.vh
new file: cl_sde/ip/ila_sde_c2h_dm/hdl/verilog/xsdbm_v3_0_0_bs_ports.vh
new file: cl_sde/ip/ila_sde_c2h_dm/hdl/verilog/xsdbm_v3_0_0_bs_vec.vh
new file: cl_sde/ip/ila_sde_c2h_dm/hdl/verilog/xsdbm_v3_0_0_bsid_ports.vh
new file: cl_sde/ip/ila_sde_c2h_dm/hdl/verilog/xsdbm_v3_0_0_bsid_vec_ports.vh
new file: cl_sde/ip/ila_sde_c2h_dm/hdl/verilog/xsdbm_v3_0_0_i2x.vh
new file: cl_sde/ip/ila_sde_c2h_dm/hdl/verilog/xsdbm_v3_0_0_icn.vh
new file: cl_sde/ip/ila_sde_c2h_dm/hdl/verilog/xsdbm_v3_0_0_id_map.vh
new file: cl_sde/ip/ila_sde_c2h_dm/hdl/verilog/xsdbm_v3_0_0_id_vec_map.vh
new file: cl_sde/ip/ila_sde_c2h_dm/hdl/verilog/xsdbm_v3_0_0_in.vh
new file: cl_sde/ip/ila_sde_c2h_dm/hdl/verilog/xsdbm_v3_0_0_sl_prt_map.vh
new file: cl_sde/ip/ila_sde_c2h_dm/hdl/verilog/xsdbs_v1_0_2_i2x.vh
new file: cl_sde/ip/ila_sde_c2h_dm/hdl/verilog/xsdbs_v1_0_2_in.vh
new file: cl_sde/ip/ila_sde_c2h_dm/hdl/xsdbm_v3_0_vl_rfs.v
new file: cl_sde/ip/ila_sde_c2h_dm/hdl/xsdbs_v1_0_vl_rfs.v
new file: cl_sde/ip/ila_sde_c2h_dm/ila_sde_c2h_dm.veo
new file: cl_sde/ip/ila_sde_c2h_dm/ila_sde_c2h_dm.xci
new file: cl_sde/ip/ila_sde_c2h_dm/ila_sde_c2h_dm.xml
new file: cl_sde/ip/ila_sde_c2h_dm/ila_sde_c2h_dm_ooc.xdc
new file: cl_sde/ip/ila_sde_c2h_dm/ila_v6_2/constraints/ila.xdc
new file: cl_sde/ip/ila_sde_c2h_dm/ila_v6_2/constraints/ila_impl.xdc
new file: cl_sde/ip/ila_sde_c2h_dm/sim/ila_sde_c2h_dm.v
new file: cl_sde/ip/ila_sde_c2h_dm/synth/ila_sde_c2h_dm.v
new file: cl_sde/ip/ila_sde_h2c_buf/doc/ila_v6_2_changelog.txt
new file: cl_sde/ip/ila_sde_h2c_buf/hdl/blk_mem_gen_v8_3_vhsyn_rfs.vhd
new file: cl_sde/ip/ila_sde_h2c_buf/hdl/fifo_generator_v13_1_vhsyn_rfs.vhd
new file: cl_sde/ip/ila_sde_h2c_buf/hdl/ila_v6_2_syn_rfs.v
new file: cl_sde/ip/ila_sde_h2c_buf/hdl/ltlib_v1_0_vl_rfs.v
new file: cl_sde/ip/ila_sde_h2c_buf/hdl/verilog/ila_v6_2_5_ila_in.vh
new file: cl_sde/ip/ila_sde_h2c_buf/hdl/verilog/ila_v6_2_5_ila_lib_fn.vh
new file: cl_sde/ip/ila_sde_h2c_buf/hdl/verilog/ila_v6_2_5_ila_lparam.vh
new file: cl_sde/ip/ila_sde_h2c_buf/hdl/verilog/ila_v6_2_5_ila_param.vh
new file: cl_sde/ip/ila_sde_h2c_buf/hdl/verilog/ila_v6_2_5_ila_ver.vh
new file: cl_sde/ip/ila_sde_h2c_buf/hdl/verilog/ltlib_v1_0_0_lib_fn.vh
new file: cl_sde/ip/ila_sde_h2c_buf/hdl/verilog/ltlib_v1_0_0_ver.vh
new file: cl_sde/ip/ila_sde_h2c_buf/hdl/verilog/xsdbm_v3_0_0_bs.vh
new file: cl_sde/ip/ila_sde_h2c_buf/hdl/verilog/xsdbm_v3_0_0_bs_core.vh
new file: cl_sde/ip/ila_sde_h2c_buf/hdl/verilog/xsdbm_v3_0_0_bs_core_vec.vh
new file: cl_sde/ip/ila_sde_h2c_buf/hdl/verilog/xsdbm_v3_0_0_bs_ports.vh
new file: cl_sde/ip/ila_sde_h2c_buf/hdl/verilog/xsdbm_v3_0_0_bs_vec.vh
new file: cl_sde/ip/ila_sde_h2c_buf/hdl/verilog/xsdbm_v3_0_0_bsid_ports.vh
new file: cl_sde/ip/ila_sde_h2c_buf/hdl/verilog/xsdbm_v3_0_0_bsid_vec_ports.vh
new file: cl_sde/ip/ila_sde_h2c_buf/hdl/verilog/xsdbm_v3_0_0_i2x.vh
new file: cl_sde/ip/ila_sde_h2c_buf/hdl/verilog/xsdbm_v3_0_0_icn.vh
new file: cl_sde/ip/ila_sde_h2c_buf/hdl/verilog/xsdbm_v3_0_0_id_map.vh
new file: cl_sde/ip/ila_sde_h2c_buf/hdl/verilog/xsdbm_v3_0_0_id_vec_map.vh
new file: cl_sde/ip/ila_sde_h2c_buf/hdl/verilog/xsdbm_v3_0_0_in.vh
new file: cl_sde/ip/ila_sde_h2c_buf/hdl/verilog/xsdbm_v3_0_0_sl_prt_map.vh
new file: cl_sde/ip/ila_sde_h2c_buf/hdl/verilog/xsdbs_v1_0_2_i2x.vh
new file: cl_sde/ip/ila_sde_h2c_buf/hdl/verilog/xsdbs_v1_0_2_in.vh
new file: cl_sde/ip/ila_sde_h2c_buf/hdl/xsdbm_v3_0_vl_rfs.v
new file: cl_sde/ip/ila_sde_h2c_buf/hdl/xsdbs_v1_0_vl_rfs.v
new file: cl_sde/ip/ila_sde_h2c_buf/ila_sde_h2c_buf.veo
new file: cl_sde/ip/ila_sde_h2c_buf/ila_sde_h2c_buf.xci
new file: cl_sde/ip/ila_sde_h2c_buf/ila_sde_h2c_buf.xml
new file: cl_sde/ip/ila_sde_h2c_buf/ila_sde_h2c_buf_ooc.xdc
new file: cl_sde/ip/ila_sde_h2c_buf/ila_v6_2/constraints/ila.xdc
new file: cl_sde/ip/ila_sde_h2c_buf/ila_v6_2/constraints/ila_impl.xdc
new file: cl_sde/ip/ila_sde_h2c_buf/sim/ila_sde_h2c_buf.v
new file: cl_sde/ip/ila_sde_h2c_buf/synth/ila_sde_h2c_buf.v
new file: cl_sde/ip/ila_sde_h2c_dm/doc/ila_v6_2_changelog.txt
new file: cl_sde/ip/ila_sde_h2c_dm/hdl/blk_mem_gen_v8_3_vhsyn_rfs.vhd
new file: cl_sde/ip/ila_sde_h2c_dm/hdl/fifo_generator_v13_1_vhsyn_rfs.vhd
new file: cl_sde/ip/ila_sde_h2c_dm/hdl/ila_v6_2_syn_rfs.v
new file: cl_sde/ip/ila_sde_h2c_dm/hdl/ltlib_v1_0_vl_rfs.v
new file: cl_sde/ip/ila_sde_h2c_dm/hdl/verilog/ila_v6_2_5_ila_in.vh
new file: cl_sde/ip/ila_sde_h2c_dm/hdl/verilog/ila_v6_2_5_ila_lib_fn.vh
new file: cl_sde/ip/ila_sde_h2c_dm/hdl/verilog/ila_v6_2_5_ila_lparam.vh
new file: cl_sde/ip/ila_sde_h2c_dm/hdl/verilog/ila_v6_2_5_ila_param.vh
new file: cl_sde/ip/ila_sde_h2c_dm/hdl/verilog/ila_v6_2_5_ila_ver.vh
new file: cl_sde/ip/ila_sde_h2c_dm/hdl/verilog/ltlib_v1_0_0_lib_fn.vh
new file: cl_sde/ip/ila_sde_h2c_dm/hdl/verilog/ltlib_v1_0_0_ver.vh
new file: cl_sde/ip/ila_sde_h2c_dm/hdl/verilog/xsdbm_v3_0_0_bs.vh
new file: cl_sde/ip/ila_sde_h2c_dm/hdl/verilog/xsdbm_v3_0_0_bs_core.vh
new file: cl_sde/ip/ila_sde_h2c_dm/hdl/verilog/xsdbm_v3_0_0_bs_core_vec.vh
new file: cl_sde/ip/ila_sde_h2c_dm/hdl/verilog/xsdbm_v3_0_0_bs_ports.vh
new file: cl_sde/ip/ila_sde_h2c_dm/hdl/verilog/xsdbm_v3_0_0_bs_vec.vh
new file: cl_sde/ip/ila_sde_h2c_dm/hdl/verilog/xsdbm_v3_0_0_bsid_ports.vh
new file: cl_sde/ip/ila_sde_h2c_dm/hdl/verilog/xsdbm_v3_0_0_bsid_vec_ports.vh
new file: cl_sde/ip/ila_sde_h2c_dm/hdl/verilog/xsdbm_v3_0_0_i2x.vh
new file: cl_sde/ip/ila_sde_h2c_dm/hdl/verilog/xsdbm_v3_0_0_icn.vh
new file: cl_sde/ip/ila_sde_h2c_dm/hdl/verilog/xsdbm_v3_0_0_id_map.vh
new file: cl_sde/ip/ila_sde_h2c_dm/hdl/verilog/xsdbm_v3_0_0_id_vec_map.vh
new file: cl_sde/ip/ila_sde_h2c_dm/hdl/verilog/xsdbm_v3_0_0_in.vh
new file: cl_sde/ip/ila_sde_h2c_dm/hdl/verilog/xsdbm_v3_0_0_sl_prt_map.vh
new file: cl_sde/ip/ila_sde_h2c_dm/hdl/verilog/xsdbs_v1_0_2_i2x.vh
new file: cl_sde/ip/ila_sde_h2c_dm/hdl/verilog/xsdbs_v1_0_2_in.vh
new file: cl_sde/ip/ila_sde_h2c_dm/hdl/xsdbm_v3_0_vl_rfs.v
new file: cl_sde/ip/ila_sde_h2c_dm/hdl/xsdbs_v1_0_vl_rfs.v
new file: cl_sde/ip/ila_sde_h2c_dm/ila_sde_h2c_dm.veo
new file: cl_sde/ip/ila_sde_h2c_dm/ila_sde_h2c_dm.xci
new file: cl_sde/ip/ila_sde_h2c_dm/ila_sde_h2c_dm.xml
new file: cl_sde/ip/ila_sde_h2c_dm/ila_sde_h2c_dm_ooc.xdc
new file: cl_sde/ip/ila_sde_h2c_dm/ila_v6_2/constraints/ila.xdc
new file: cl_sde/ip/ila_sde_h2c_dm/ila_v6_2/constraints/ila_impl.xdc
new file: cl_sde/ip/ila_sde_h2c_dm/sim/ila_sde_h2c_dm.v
new file: cl_sde/ip/ila_sde_h2c_dm/synth/ila_sde_h2c_dm.v
new file: cl_sde/ip/ila_sde_ps/doc/ila_v6_2_changelog.txt
new file: cl_sde/ip/ila_sde_ps/hdl/blk_mem_gen_v8_3_vhsyn_rfs.vhd
new file: cl_sde/ip/ila_sde_ps/hdl/fifo_generator_v13_1_vhsyn_rfs.vhd
new file: cl_sde/ip/ila_sde_ps/hdl/ila_v6_2_syn_rfs.v
new file: cl_sde/ip/ila_sde_ps/hdl/ltlib_v1_0_vl_rfs.v
new file: cl_sde/ip/ila_sde_ps/hdl/verilog/ila_v6_2_5_ila_in.vh
new file: cl_sde/ip/ila_sde_ps/hdl/verilog/ila_v6_2_5_ila_lib_fn.vh
new file: cl_sde/ip/ila_sde_ps/hdl/verilog/ila_v6_2_5_ila_lparam.vh
new file: cl_sde/ip/ila_sde_ps/hdl/verilog/ila_v6_2_5_ila_param.vh
new file: cl_sde/ip/ila_sde_ps/hdl/verilog/ila_v6_2_5_ila_ver.vh
new file: cl_sde/ip/ila_sde_ps/hdl/verilog/ltlib_v1_0_0_lib_fn.vh
new file: cl_sde/ip/ila_sde_ps/hdl/verilog/ltlib_v1_0_0_ver.vh
new file: cl_sde/ip/ila_sde_ps/hdl/verilog/xsdbm_v3_0_0_bs.vh
new file: cl_sde/ip/ila_sde_ps/hdl/verilog/xsdbm_v3_0_0_bs_core.vh
new file: cl_sde/ip/ila_sde_ps/hdl/verilog/xsdbm_v3_0_0_bs_core_vec.vh
new file: cl_sde/ip/ila_sde_ps/hdl/verilog/xsdbm_v3_0_0_bs_ports.vh
new file: cl_sde/ip/ila_sde_ps/hdl/verilog/xsdbm_v3_0_0_bs_vec.vh
new file: cl_sde/ip/ila_sde_ps/hdl/verilog/xsdbm_v3_0_0_bsid_ports.vh
new file: cl_sde/ip/ila_sde_ps/hdl/verilog/xsdbm_v3_0_0_bsid_vec_ports.vh
new file: cl_sde/ip/ila_sde_ps/hdl/verilog/xsdbm_v3_0_0_i2x.vh
new file: cl_sde/ip/ila_sde_ps/hdl/verilog/xsdbm_v3_0_0_icn.vh
new file: cl_sde/ip/ila_sde_ps/hdl/verilog/xsdbm_v3_0_0_id_map.vh
new file: cl_sde/ip/ila_sde_ps/hdl/verilog/xsdbm_v3_0_0_id_vec_map.vh
new file: cl_sde/ip/ila_sde_ps/hdl/verilog/xsdbm_v3_0_0_in.vh
new file: cl_sde/ip/ila_sde_ps/hdl/verilog/xsdbm_v3_0_0_sl_prt_map.vh
new file: cl_sde/ip/ila_sde_ps/hdl/verilog/xsdbs_v1_0_2_i2x.vh
new file: cl_sde/ip/ila_sde_ps/hdl/verilog/xsdbs_v1_0_2_in.vh
new file: cl_sde/ip/ila_sde_ps/hdl/xsdbm_v3_0_vl_rfs.v
new file: cl_sde/ip/ila_sde_ps/hdl/xsdbs_v1_0_vl_rfs.v
new file: cl_sde/ip/ila_sde_ps/ila_sde_ps.veo
new file: cl_sde/ip/ila_sde_ps/ila_sde_ps.xci
new file: cl_sde/ip/ila_sde_ps/ila_sde_ps.xml
new file: cl_sde/ip/ila_sde_ps/ila_sde_ps_ooc.xdc
new file: cl_sde/ip/ila_sde_ps/ila_v6_2/constraints/ila.xdc
new file: cl_sde/ip/ila_sde_ps/ila_v6_2/constraints/ila_impl.xdc
new file: cl_sde/ip/ila_sde_ps/sim/ila_sde_ps.v
new file: cl_sde/ip/ila_sde_ps/synth/ila_sde_ps.v
new file: cl_sde/ip/ila_sde_wb/doc/ila_v6_2_changelog.txt
new file: cl_sde/ip/ila_sde_wb/hdl/blk_mem_gen_v8_3_vhsyn_rfs.vhd
new file: cl_sde/ip/ila_sde_wb/hdl/fifo_generator_v13_1_vhsyn_rfs.vhd
new file: cl_sde/ip/ila_sde_wb/hdl/ila_v6_2_syn_rfs.v
new file: cl_sde/ip/ila_sde_wb/hdl/ltlib_v1_0_vl_rfs.v
new file: cl_sde/ip/ila_sde_wb/hdl/verilog/ila_v6_2_5_ila_in.vh
new file: cl_sde/ip/ila_sde_wb/hdl/verilog/ila_v6_2_5_ila_lib_fn.vh
new file: cl_sde/ip/ila_sde_wb/hdl/verilog/ila_v6_2_5_ila_lparam.vh
new file: cl_sde/ip/ila_sde_wb/hdl/verilog/ila_v6_2_5_ila_param.vh
new file: cl_sde/ip/ila_sde_wb/hdl/verilog/ila_v6_2_5_ila_ver.vh
new file: cl_sde/ip/ila_sde_wb/hdl/verilog/ltlib_v1_0_0_lib_fn.vh
new file: cl_sde/ip/ila_sde_wb/hdl/verilog/ltlib_v1_0_0_ver.vh
new file: cl_sde/ip/ila_sde_wb/hdl/verilog/xsdbm_v3_0_0_bs.vh
new file: cl_sde/ip/ila_sde_wb/hdl/verilog/xsdbm_v3_0_0_bs_core.vh
new file: cl_sde/ip/ila_sde_wb/hdl/verilog/xsdbm_v3_0_0_bs_core_vec.vh
new file: cl_sde/ip/ila_sde_wb/hdl/verilog/xsdbm_v3_0_0_bs_ports.vh
new file: cl_sde/ip/ila_sde_wb/hdl/verilog/xsdbm_v3_0_0_bs_vec.vh
new file: cl_sde/ip/ila_sde_wb/hdl/verilog/xsdbm_v3_0_0_bsid_ports.vh
new file: cl_sde/ip/ila_sde_wb/hdl/verilog/xsdbm_v3_0_0_bsid_vec_ports.vh
new file: cl_sde/ip/ila_sde_wb/hdl/verilog/xsdbm_v3_0_0_i2x.vh
new file: cl_sde/ip/ila_sde_wb/hdl/verilog/xsdbm_v3_0_0_icn.vh
new file: cl_sde/ip/ila_sde_wb/hdl/verilog/xsdbm_v3_0_0_id_map.vh
new file: cl_sde/ip/ila_sde_wb/hdl/verilog/xsdbm_v3_0_0_id_vec_map.vh
new file: cl_sde/ip/ila_sde_wb/hdl/verilog/xsdbm_v3_0_0_in.vh
new file: cl_sde/ip/ila_sde_wb/hdl/verilog/xsdbm_v3_0_0_sl_prt_map.vh
new file: cl_sde/ip/ila_sde_wb/hdl/verilog/xsdbs_v1_0_2_i2x.vh
new file: cl_sde/ip/ila_sde_wb/hdl/verilog/xsdbs_v1_0_2_in.vh
new file: cl_sde/ip/ila_sde_wb/hdl/xsdbm_v3_0_vl_rfs.v
new file: cl_sde/ip/ila_sde_wb/hdl/xsdbs_v1_0_vl_rfs.v
new file: cl_sde/ip/ila_sde_wb/ila_sde_wb.veo
new file: cl_sde/ip/ila_sde_wb/ila_sde_wb.xci
new file: cl_sde/ip/ila_sde_wb/ila_sde_wb.xml
new file: cl_sde/ip/ila_sde_wb/ila_sde_wb_ooc.xdc
new file: cl_sde/ip/ila_sde_wb/ila_v6_2/constraints/ila.xdc
new file: cl_sde/ip/ila_sde_wb/ila_v6_2/constraints/ila_impl.xdc
new file: cl_sde/ip/ila_sde_wb/sim/ila_sde_wb.v
new file: cl_sde/ip/ila_sde_wb/synth/ila_sde_wb.v
new file: cl_sde/software/include/.gitignore
new file: cl_sde/software/include/sh_dpi_tasks.h
new file: cl_sde/software/src/.gitignore
new file: cl_sde/software/src/test_null.c
new file: cl_sde/verif/scripts/Makefile
new file: cl_sde/verif/scripts/Makefile.questa
new file: cl_sde/verif/scripts/Makefile.vcs
new file: cl_sde/verif/scripts/Makefile.vivado
new file: cl_sde/verif/scripts/regress_err_handle
new file: cl_sde/verif/scripts/regress_nightly
new file: cl_sde/verif/scripts/regress_nightly_16K
new file: cl_sde/verif/scripts/regress_nightly_32K
new file: cl_sde/verif/scripts/regress_nightly_4K
new file: cl_sde/verif/scripts/regress_nightly_8K
new file: cl_sde/verif/scripts/regress_smoke
new file: cl_sde/verif/scripts/top.questa.f
new file: cl_sde/verif/scripts/top.vcs.f
new file: cl_sde/verif/scripts/top.vivado.f
new file: cl_sde/verif/scripts/waves.tcl
new file: cl_sde/verif/sv/dma_classes.sv
new file: cl_sde/verif/sv/perf_mon.sv
new file: cl_sde/verif/tests/test_base.inc
new file: cl_sde/verif/tests/test_c2h_h2c_using_atg.sv
new file: cl_sde/verif/tests/test_desc_access.sv
new file: cl_sde/verif/tests/test_null.sv
new file: cl_sde/verif/tests/test_pci_atg.sv
new file: cl_sde/verif/tests/test_random_c2h.sv
new file: cl_sde/verif/tests/test_random_combined.sv
new file: cl_sde/verif/tests/test_random_h2c.sv
new file: cl_sde/verif/tests/test_simple_c2h.sv
new file: cl_sde/verif/tests/test_simple_c2h_desc_oflow.sv
new file: cl_sde/verif/tests/test_simple_c2h_desc_ooo.sv
new file: cl_sde/verif/tests/test_simple_c2h_desc_unalin.sv
new file: cl_sde/verif/tests/test_simple_c2h_dm_desc_len_err.sv
new file: cl_sde/verif/tests/test_simple_c2h_pcim_bresp_err.sv
new file: cl_sde/verif/tests/test_simple_h2c.sv
new file: cl_sde/verif/tests/test_simple_h2c_desc_oflow.sv
new file: cl_sde/verif/tests/test_simple_h2c_desc_ooo.sv
new file: cl_sde/verif/tests/test_simple_h2c_desc_unalin.sv
new file: cl_sde/verif/tests/test_simple_h2c_dm_desc_len_err.sv
new file: cl_sde/verif/tests/test_simple_h2c_pcim_bresp_err.sv
new file: cl_sde/verif/tests/test_simple_h2c_pcim_rresp_err.sv
* adding the lib files & other missing files.
updated file paths
Licensing needs to be attached: pending.
* 1. updating CL_ID
2. Porting the writeback file from chimera for bug fix
modified: hdk/cl/examples/cl_sde/design/cl_sde.sv
modified: hdk/cl/examples/cl_sde/design/sde_wb.sv
modified: hdk/cl/examples/cl_sde/lib/bram_1w1r.sv
* sdk/apps/virtual-ethernet: Added pktgen-ena-range config for improved PPS consistency
Also allows customer tuning of packet size ranges
* Update Virtual_Ethernet_Application_Guide.md
* sdk/apps/virtual-ethernet: changes to support DPDK v18.05
* sdk/apps/virtual-ethernet: DPDK v18.05 related
- Added RTE_MEMZONE_IOVA_CONTIG to memzone reservation calls to get
the previous default memzone reservation behavior.
* Update Virtual_Ethernet_Application_Guide.md
* sdk/apps/virtual-ethernet: added mbuf trailer checking for SPP_DBG_USE_MBUF_SEQ_NUM
* Create README.md
* Update README.md
* Update README.md
* porting bug updates from chimera as indicated by kiran. validated customer flow.
modified: hdk/cl/examples/cl_sde/design/sde.sv
modified: hdk/cl/examples/cl_sde/design/sde_c2h.sv
modified: hdk/cl/examples/cl_sde/design/sde_c2h_axis.sv
modified: hdk/cl/examples/cl_sde/design/sde_c2h_buf.sv
modified: hdk/cl/examples/cl_sde/design/sde_c2h_cfg.sv
modified: hdk/cl/examples/cl_sde/design/sde_c2h_data.sv
modified: hdk/cl/examples/cl_sde/design/sde_desc.sv
modified: hdk/cl/examples/cl_sde/design/sde_h2c.sv
modified: hdk/cl/examples/cl_sde/design/sde_h2c_axis.sv
modified: hdk/cl/examples/cl_sde/design/sde_h2c_buf.sv
modified: hdk/cl/examples/cl_sde/design/sde_h2c_data.sv
modified: hdk/cl/examples/cl_sde/design/sde_pkg.sv
modified: hdk/cl/examples/cl_sde/design/sde_pm.sv
modified: hdk/cl/examples/cl_sde/design/sde_ps.sv
modified: hdk/cl/examples/cl_sde/design/sde_ps_acc.sv
modified: hdk/cl/examples/cl_sde/design/sde_wb.sv
* Update README.md
* Update README.md
* Update SDE_HW_Guide.md
* Update README.md
* Update README.md
* Update README.md
* Update README.md
* updating sde example with expanded customer configurations
* porting changes made directly to preview back to staging -branch
some updates mainly documentation & software patches were made directly to preview area. Porting them back to staging branch.
* Robertmj sde compact descs (#434)
* Added SDE info support
* allows dynamic queue size discovery by testpmd
* allows sanity checking of unsupported SDE configs.
* Added SDE compact descriptor support.
* see SPP_USE_COMPACT_DESCS in spp_defs.h
* Update Virtual_Ethernet_Application_Guide.md
* Update Virtual_Ethernet_Application_Guide.md
* updating license headers for jenkins header check
* fixing license header issues
* further license header cleanup
* fixing license headers
* script to generate IP and associated collateral
* updates jenkins on v141 branch with cl_sde dcp build ,create afi & cl_sde runtime loopback placeholder.
* updated softlink for script to stay within repo
* updating AFI to a rebased version DevKit 1.4.1
* Updated SDE resource counts
* Optimizations to SDE.
* SDE: Increasing Number of OT Reads
* Fixing license headers
* Fixing read txn fifo
* Revert "Fixing license headers"
This reverts commit 4147ec74a329166fb75c0b1c197732bca1231f8a.
* Revert "SDE: Increasing Number of OT Reads"
This reverts commit 7613db06cee03f648df17ee3e4e640bb0f7de719.
* Revert "Optimizations to SDE."
This reverts commit ba9d165166ecc9a9bde17dfcdb39ba0acc4c6456.
* Revert "Fixing read txn fifo"
This reverts commit 858df502505bf4eeb692c02879fd5f133f814575.
* updating qual run.
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
adding kernel version warning for SDAccel runtime setup
Adding instance placement group documentation to virtual ethernet application guide.