Release v1.3.8 #408
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Release v1.3.8 #408
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kyyalama2
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May 24, 2022
* Updating the build scripts with setting parameter hd.clockRoutingWireReduction to false as a workaorund for Vivado 2017.4 bug. modified: hdk/cl/examples/cl_dram_dma/build/scripts/create_dcp_from_cl.tcl modified: hdk/cl/examples/cl_hello_world/build/scripts/create_dcp_from_cl.tcl modified: hdk/cl/examples/cl_hello_world_vhdl/build/scripts/create_dcp_from_cl.tcl modified: hdk/cl/examples/cl_uram_example/build/scripts/create_dcp_from_cl.tcl * updating dsa with 062918 deiverable from xilinx. This dsa has the " xocc --xp vivado_param:hd.clockRoutingWireReduction=false" option baked in
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