v1.3.5 Release #385
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v1.3.5 Release #385
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deeppat
reviewed
Jan 17, 2018
| @@ -1,6 +1,36 @@ | |||
| /** | |||
| * Copyright (C) 2016-2017 Xilinx, Inc | |||
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We have two headers here, so might have to revisit this later with Xilinx about keeping the correct one or unifying their headers
deeppat
reviewed
Jan 17, 2018
| @@ -81,7 +81,7 @@ cp $ddr4_imports_dir/ddr4_db_delay_model.sv $ddr4_rdimm_model_dir/ | |||
| cp $ddr4_imports_dir/ddr4_db_dly_dir.sv $ddr4_rdimm_model_dir/ | |||
| cp $ddr4_imports_dir/ddr4_dimm.sv $ddr4_rdimm_model_dir/ | |||
| cp $ddr4_imports_dir/ddr4_dir_detect.sv $ddr4_rdimm_model_dir/ | |||
| cp $ddr4_imports_dir/ddr4_rank.sv $ddr4_rdimm_model_dir/ | |||
| #cp $ddr4_imports_dir/ddr4_rank.sv $ddr4_rdimm_model_dir/ | |||
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This seems odd. Commented out but not removed. Are we sure this is correct?
deeppat
approved these changes
Jan 17, 2018
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