XiangShan (香山) is an open-source high-performance RISC-V processor project.

中文说明在此。

Copyright 2020-2021 by Institute of Computing Technology, Chinese Academy of Sciences.

Copyright 2020-2021 by Peng Cheng Laboratory.

We gave 20+ presentations on RISC-V World Conference China 2021. XiangShan tutorial was held at the same place. Our slides for RVWC2021 have been updated on our doc repo (in Chinese).

我们在2021年RISC-V中国峰会的报告已经更新到这里。未来的文档和相关信息也将更新到相同的仓库。

You can contact us through our mail list. All mails from this list will be archived to here.

The first stable micro-architecture of XiangShan is called Yanqihu (雁栖湖) on this branch, which has been developed since June 2020. The current version of XiangShan, also known as Nanhu (南湖), is still under development on the master branch.

The micro-architecture overview is shown below.

Some of the key directories are shown below.

.
├── fpga                   # supported FPGA boards and files to build a Vivado project
├── read-to-run            # pre-built simulation images
├── scripts                # scripts for agile development
└── src
    ├── test               # test files (including diff-test, module-test, etc.)
    └── main/scala         # design files
        ├── bus/tilelink   # tilelink utils
        ├── device         # virtual device for simulation
        ├── difftest       # diff-test chisel interface
        ├── system         # SoC wrapper
        ├── top            # top module
        ├── utils          # utilization code
        ├── xiangshan      # main design code
        └── xstransforms   # some useful firrtl transforms

• Run make verilog to generate verilog code. The output file is build/XSTop.v.
• Refer to Makefile for more information.

• Set environment variable NEMU_HOME to the absolute path of the NEMU project.
• Set environment variable NOOP_HOME to the absolute path of the XiangShan project.
• Set environment variable AM_HOME to the absolute path of the AM project.
• Install mill. Refer to the Manual section in this guide.
• Clone this project and run make init to initialize submodules.

• Install Verilator, the open-source Verilog simulator.
• Run make emu to build the C++ simulator ./build/emu with Verilator.
• Refer to ./build/emu --help for run-time arguments of the simulator.
• Refer to Makefile and verilator.mk for more information.

Example:

make emu CONFIG=MinimalConfig SIM_ARGS=--disable-log EMU_THREADS=2 -j10
./build/emu -b 0 -e 0 -i ./ready-to-run/coremark-2-iteration.bin --diff ./ready-to-run/riscv64-nemu-interpreter-so

In the development of XiangShan, some sub-modules from the open-source community are employed. All relevant usage is listed below.

We are grateful for the support of the open-source community and encourage other open-source projects to reuse our code within the scope of the license.