GitHub - Mahdi-HF/centralProccessingUnit-MIPS: designing multi cycle mips processor with external interrupts handling in "Verilog"

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designing multi cycle mips processor with external interrupts handling in "Verilog"

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Name		Name	Last commit message	Last commit date
Latest commit History 57 Commits
_xmsgs		_xmsgs
iseconfig		iseconfig
isim		isim
xst/work		xst/work
ALU.lso		ALU.lso
ALU.prj		ALU.prj
ALU.stx		ALU.stx
ALU.v		ALU.v
ALU.xst		ALU.xst
ALUTest.v		ALUTest.v
ALUTest_isim_beh.exe		ALUTest_isim_beh.exe
ALUTest_stx_beh.prj		ALUTest_stx_beh.prj
ALU_summary.html		ALU_summary.html
Controller.lso		Controller.lso
Controller.prj		Controller.prj
Controller.stx		Controller.stx
Controller.v		Controller.v
Controller.xst		Controller.xst
ControllerTest.v		ControllerTest.v
ControllerTest_isim_beh.exe		ControllerTest_isim_beh.exe
ControllerTest_stx_beh.prj		ControllerTest_stx_beh.prj
DataPath.lso		DataPath.lso
DataPath.prj		DataPath.prj
DataPath.stx		DataPath.stx
DataPath.v		DataPath.v
DataPath.xst		DataPath.xst
DataPathTest.v		DataPathTest.v
DataPathTest_isim_beh.exe		DataPathTest_isim_beh.exe
DataPathTest_isim_beh1.wdb		DataPathTest_isim_beh1.wdb
DataPathTest_stx_beh.prj		DataPathTest_stx_beh.prj
MemariProject.gise		MemariProject.gise
MemariProject.xise		MemariProject.xise
Memory.lso		Memory.lso
Memory.prj		Memory.prj
Memory.stx		Memory.stx
Memory.v		Memory.v
Memory.xst		Memory.xst
MemoryTest.v		MemoryTest.v
MemoryTest_isim_beh.exe		MemoryTest_isim_beh.exe
MemoryTest_stx_beh.prj		MemoryTest_stx_beh.prj
Memory_isim_beh.exe		Memory_isim_beh.exe
MultiCycleProccessor.cmd_log		MultiCycleProccessor.cmd_log
MultiCycleProccessor.lso		MultiCycleProccessor.lso
MultiCycleProccessor.ngc		MultiCycleProccessor.ngc
MultiCycleProccessor.ngr		MultiCycleProccessor.ngr
MultiCycleProccessor.prj		MultiCycleProccessor.prj
MultiCycleProccessor.stx		MultiCycleProccessor.stx
MultiCycleProccessor.syr		MultiCycleProccessor.syr
MultiCycleProccessor.v		MultiCycleProccessor.v
MultiCycleProccessor.xst		MultiCycleProccessor.xst
MultiCycleProccessorTest.v		MultiCycleProccessorTest.v
MultiCycleProccessorTest_beh.prj		MultiCycleProccessorTest_beh.prj
MultiCycleProccessorTest_isim_beh.exe		MultiCycleProccessorTest_isim_beh.exe
MultiCycleProccessorTest_isim_beh.wdb		MultiCycleProccessorTest_isim_beh.wdb
MultiCycleProccessorTest_stx_beh.prj		MultiCycleProccessorTest_stx_beh.prj
MultiCycleProccessor_envsettings.html		MultiCycleProccessor_envsettings.html
MultiCycleProccessor_isim_beh.exe		MultiCycleProccessor_isim_beh.exe
MultiCycleProccessor_summary.html		MultiCycleProccessor_summary.html
MultiCycleProccessor_xst.xrpt		MultiCycleProccessor_xst.xrpt
Mux2-5bit.v		Mux2-5bit.v
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Mux2.stx		Mux2.stx
Mux2.v		Mux2.v
Mux2.xst		Mux2.xst
Mux2FiveBit.v		Mux2FiveBit.v
Mux2FiveBitTest.v		Mux2FiveBitTest.v
Mux2FiveBitTest_isim_beh.exe		Mux2FiveBitTest_isim_beh.exe
Mux2FiveBitTest_stx_beh.prj		Mux2FiveBitTest_stx_beh.prj
Mux2Test.v		Mux2Test.v
Mux2Test_isim_beh.exe		Mux2Test_isim_beh.exe
Mux2Test_stx_beh.prj		Mux2Test_stx_beh.prj
Mux4.lso		Mux4.lso
Mux4.prj		Mux4.prj
Mux4.stx		Mux4.stx
Mux4.v		Mux4.v
Mux4.xst		Mux4.xst
Mux4Fivebit.v		Mux4Fivebit.v
Mux4_stx_beh.prj		Mux4_stx_beh.prj
RegFile.cmd_log		RegFile.cmd_log
RegFile.lso		RegFile.lso
RegFile.ngc		RegFile.ngc
RegFile.ngr		RegFile.ngr
RegFile.prj		RegFile.prj
RegFile.stx		RegFile.stx
RegFile.syr		RegFile.syr
RegFile.v		RegFile.v
RegFile.xst		RegFile.xst
RegFileTest.v		RegFileTest.v
RegFileTest_isim_beh.exe		RegFileTest_isim_beh.exe
RegFileTest_stx_beh.prj		RegFileTest_stx_beh.prj
RegFile_xst.xrpt		RegFile_xst.xrpt
ShiftRegister.lso		ShiftRegister.lso
ShiftRegister.prj		ShiftRegister.prj
ShiftRegister.stx		ShiftRegister.stx
ShiftRegister.v		ShiftRegister.v
ShiftRegister.xst		ShiftRegister.xst
ShiftRegisterEnable.lso		ShiftRegisterEnable.lso
ShiftRegisterEnable.prj		ShiftRegisterEnable.prj
ShiftRegisterEnable.stx		ShiftRegisterEnable.stx