This document is a guideline which provides a brief description of the Hastlayer Hardware Framework for Xilinx FPGAs. The aim of this document is to help the reader to reconstruct and test the Hastlayer FPGA firmware design and to give a hand when you run into a problem.

If you're not familiar with Hastlayer take a look at https://hastlayer.com/.

Note that unfortunately, due to the compatibility of the FPGA development software Vivado, this project only works up to Windows 10, but not with Windows 11. Running Vivado in Windows 8 compatibility mode (configuring this for C:\Xilinx\Vivado\2016.4\bin\unwrapped\win64.o\vivado.exe and C:\Xilinx\Vivado\2016.4\bin\unwrapped\win64.o\vvgl.exe) doesn't help.

• Prerequisite requirements
• Getting started
• Running hardware designs
• Release notes
• Version control
• Upgrading the project to the latest Vivado version
• Design reproduction steps
• Testing custom IP cores
• AXI Lite interface slave registers
• Adding custom library functions to the design
• Debugging with an ILA core