Last active
December 24, 2024 16:06
-
-
Save davidlohr/d21a8680958e2168f2c92d2de5cdf35b to your computer and use it in GitHub Desktop.
syzkaller config - qemu deployment emulating a setup suitable for 4 way interleave. Only one fixed window provided, to enable 2 way interleave across 2 CXL host bridges. Each host bridge has 2 CXL Root Ports, with the CXL Type3 device directly attached (no switches).
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| { | |
| "target": "linux/amd64", | |
| "http": "127.0.0.1:56741", | |
| "workdir": "workdir", | |
| "kernel_obj": "/home/dave/code/linux/", | |
| "image": "/img/bullseye.img", | |
| "sshkey": "/img/bullseye.id_rsa", | |
| "syzkaller": "/home/dave/code/syzkaller", | |
| "procs": 8, | |
| "type": "qemu", | |
| "enable_syscalls": [ "openat$cxl*", "write$cxl*", "ioctl$CXL*","syz_open_dev$cxlmem*" ], | |
| "vm": { | |
| "qemu": "/home/dave/git/qemu-vanilla/build/qemu-system-x86_64", | |
| "count": 1, | |
| "qemu_args": "-machine q35,accel=kvm,cxl=on -object memory-backend-file,id=cxl-mem1,share=on,mem-path=/tmp/cxltest.raw,size=256M -object memory-backend-file,id=cxl-mem2,share=on,mem-path=/tmp/cxltest2.raw,size=256M -object memory-backend-file,id=cxl-mem3,share=on,mem-path=/tmp/cxltest3.raw,size=256M -object memory-backend-file,id=cxl-mem4,share=on,mem-path=/tmp/cxltest4.raw,size=256M -object memory-backend-file,id=cxl-lsa1,share=on,mem-path=/tmp/lsa.raw,size=256M -object memory-backend-file,id=cxl-lsa2,share=on,mem-path=/tmp/lsa2.raw,size=256M -object memory-backend-file,id=cxl-lsa3,share=on,mem-path=/tmp/lsa3.raw,size=256M -object memory-backend-file,id=cxl-lsa4,share=on,mem-path=/tmp/lsa4.raw,size=256M -device pxb-cxl,bus_nr=12,bus=pcie.0,id=cxl.1 -device pxb-cxl,bus_nr=222,bus=pcie.0,id=cxl.2 -device cxl-rp,port=0,bus=cxl.1,id=root_port13,chassis=0,slot=2 -device cxl-type3,bus=root_port13,persistent-memdev=cxl-mem1,lsa=cxl-lsa1,id=cxl-pmem0 -device cxl-rp,port=1,bus=cxl.1,id=root_port14,chassis=0,slot=3 -device cxl-type3,bus=root_port14,persistent-memdev=cxl-mem2,lsa=cxl-lsa2,id=cxl-pmem1 -device cxl-rp,port=0,bus=cxl.2,id=root_port15,chassis=0,slot=5 -device cxl-type3,bus=root_port15,persistent-memdev=cxl-mem3,lsa=cxl-lsa3,id=cxl-pmem2 -device cxl-rp,port=1,bus=cxl.2,id=root_port16,chassis=0,slot=6 -device cxl-type3,bus=root_port16,persistent-memdev=cxl-mem4,lsa=cxl-lsa4,id=cxl-pmem3 -M cxl-fmw.0.targets.0=cxl.1,cxl-fmw.0.targets.1=cxl.2,cxl-fmw.0.size=4G,cxl-fmw.0.interleave-granularity=8k", | |
| "kernel": "/home/dave/code/linux/arch/x86/boot/bzImage", | |
| "cmdline": "net.ifnames=0 cxl_acpi.dyndbg=+fplm cxl_pci.dyndbg=+fplm cxl_core.dyndbg=+fplm cxl_mem.dyndbg=+fplm cxl_pmem.dyndbg=+fplm cxl_port.dyndbg=+fplm cxl_region.dyndbg=+fplm cxl_test.dyndbg=+fplm", | |
| "cpu": 4, | |
| "mem": 2048 | |
| } | |
| } |
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment