Category:Semiconductor devices fabrication
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manufacturing process used to create integrated circuits | |||||
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| Location | semiconductor fabrication plant | ||||
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Subcategories
This category has the following 21 subcategories, out of 21 total.
Media in category "Semiconductor devices fabrication"
The following 69 files are in this category, out of 69 total.
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10nm node mt1 ppe vs pitch.png 674 × 324; 11 KB
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14 nm half-pitch multipatterning.png 910 × 375; 23 KB
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14 nm half-pitch multipatterning.svg 743 × 337; 49 KB
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4-fach-NAND-C10.JPG 967 × 1,206; 1.6 MB
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7 nm litho options.png 859 × 582; 410 KB
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Alu bridge.jpg 1,020 × 694; 214 KB
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Anti-spacer Double patterning.png 815 × 593; 16 KB
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APD structure.svg 750 × 678; 27 KB
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APD with Superlattice.svg 681 × 633; 8 KB
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APD.png 400 × 290; 21 KB
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Ballbond-trand.png 2,331 × 1,197; 148 KB
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Bell telephone magazine (1922) (14569544079).jpg 2,064 × 1,684; 1.34 MB
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Bivar-logo.png 213 × 60; 3 KB
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Buried zener structure-en.svg 521 × 283; 5 KB
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Buried zener structure.svg 521 × 283; 16 KB
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Buried zener vs npn epi.svg 521 × 616; 26 KB
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Centrotherm diffusion furnace at LAAS 0489.jpg 2,592 × 3,872; 3.85 MB
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Centrotherm diffusion furnace at LAAS 0491.jpg 2,592 × 3,872; 3.78 MB
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Centrotherm diffusion furnace at LAAS 0493.jpg 2,592 × 3,872; 4 MB
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Centrotherm diffusion furnaces at LAAS 0481.jpg 2,592 × 3,872; 4.22 MB
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Comparison semiconductor process nodes.svg 990 × 765; 72 KB
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Dicing blade.jpg 578 × 443; 87 KB
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Diferencia estructura.PNG 552 × 240; 41 KB
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DRAM burried capacitor configuration.svg 800 × 600; 4 KB
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DRAM self-aligned storage node locations.png 706 × 550; 52 KB
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DRAM trench configuration 2.svg 512 × 512; 4 KB
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DRAM trench structure configuration1 1.svg 512 × 512; 6 KB
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DRAM trench structure configuration1.svg 800 × 600; 6 KB
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Field-induced MRAM schematic ja.png 5,464 × 4,672; 132 KB
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GeS CVD setup.png 1,254 × 607; 89 KB
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GST CVD setup.png 467 × 233; 55 KB
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GST CVD setup.tif 1,074 × 538; 220 KB
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Illustration of C-V measurement.gif 322 × 308; 93 KB
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KO fig21 applications Corelv11.png 1,748 × 1,799; 483 KB
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Laser diode with case cut away.jpg 512 × 437; 118 KB
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LELE challenge.png 472 × 353; 5 KB
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Lift-off (microtechnology) process.svg 512 × 664; 31 KB
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Lift-off-Verfahren (Fehlerbilder).svg 1,100 × 600; 44 KB
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Lift-off-Verfahren (Halbleitertechnik).svg 1,024 × 756; 41 KB
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Line cut location offset.png 417 × 442; 6 KB
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Main applications of ALD.png 1,692 × 1,718; 317 KB
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Microprocessore silicio germano.jpg 250 × 324; 21 KB
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Molecular Beam Epitaxy.png 1,400 × 739; 153 KB
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Moore Kosten.png 943 × 665; 36 KB
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OR2 layout.PNG 678 × 348; 19 KB
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Organic transistor Greek.png 415 × 211; 95 KB
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Overflow.svg 1,000 × 800; 24 KB
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Overlay - typical model terms DE.svg 617 × 591; 16 KB
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Pellicle vs no pellicle in a photomask.svg 756 × 567; 78 KB
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Piranha solution.png 864 × 1,536; 1.55 MB
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SADP challenge.png 504 × 497; 8 KB
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SADP then SATP.png 668 × 253; 8 KB
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Salle blanche ensim.jpg 4,256 × 2,832; 5.61 MB
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Schottky-Transistor-Side.svg 364 × 204; 22 KB
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SE Making Ingot Step 02.svg 346 × 371; 11 KB
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SE Making Ingot Step 03.svg 317 × 329; 12 KB
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SE Making Ingot Step 04 ver01.svg 310 × 376; 16 KB
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Self-aligned silicidation.svg 1,990 × 692; 52 KB
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SemiconductorProcessSize.png 1,440 × 852; 48 KB
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Siliconchip by shapeshifter.png 1,276 × 891; 1.83 MB
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Spacer formation (DE).svg 875 × 361; 14 KB
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Spacer Patterning.JPG 393 × 576; 19 KB
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Spacer trimming.png 1,157 × 484; 17 KB
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The entrance of 3S Silicon Tech., Inc.jpg 898 × 783; 386 KB
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Trilogy WSI Wafer.png 1,920 × 1,920; 7.45 MB
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Two-bar challenge.png 601 × 351; 8 KB
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Wafermap showing fully and partially patterned dies.svg 657 × 657; 103 KB
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Worldwide Semiconductor Sales in Billion US-Dollar GERMAN.jpg 621 × 327; 27 KB
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