Changes to support release 1.2.2

wjblanke · May 31, 2017 · dd56025 · dd56025
1 parent 10222be
commit dd56025
Show file tree

Hide file tree

Showing 25 changed files with 205 additions and 57 deletions.
diff --git a/FAQs.md b/FAQs.md
@@ -204,7 +204,7 @@ We encourage you to use the [AWS FPGA Developer Forum](https://forums.aws.amazon
 
 The required AWS software is the [FPGA Management Tool set](./sdk/userspace/fpga_mgmt_tools). This software manages loading and clearing AFIs for the instance FPGAs. It also allows developers to retrieve FPGAs status from within the instance. Users will need to load the F1 AMI with the drivers and runtime libraries needed for their FPGA application.
 
-Typically, you will not need the HDK nor any Xilinx Vivado tools on an F1 instance that is using prebuilt AFIs; unless, you want to do in-field debug using Vivado's ChipScope.
+Typically, you will not need the HDK nor any Xilinx Vivado tools on an F1 instance that is using prebuilt AFIs; unless, you want to do in-field debug using Vivado's ChipScope (Virtual JTAG).
 
 
 ## Marketplace
@@ -235,7 +235,7 @@ There are two types of interfaces from the instance host CPU to the FPGAs:
 
 The first is the FPGA Image Management Tools. These APIs are detailed in the [SDK portion](./sdk/userspace/fpga_mgmt_tools) of the GitHub repository. FPGA Image Management Tools include APIs to load, clear, and get status of the FPGA. 
 
-The second type of interface is direct address access to the Application PCIe Physical Functions (PF) of the FPGA. There is no API for this access. Rather, there is direct access to resources in the Custom Logic (CL) region or Shell that can be accessed by software written on the instance. For example, the ChipScope software uses address space in a PF to provide FPGA debug support. Developers can create any API to the resources in their CL. See the [Shell Interface Specification](./hdk/docs/AWS_Shell_Interface_Specification.md) for more details on the address space mapping as seen from the instance.
+The second type of interface is direct address access to the Application PCIe Physical Functions (PF) of the FPGA. There is no API for this access. Rather, there is direct access to resources in the Custom Logic (CL) region or Shell that can be accessed by software written on the instance. For example, the ChipScope software (Virtual JTAG) uses address space in a PF to provide FPGA debug support. Developers can create any API to the resources in their CL. See the [Shell Interface Specification](./hdk/docs/AWS_Shell_Interface_Specification.md) for more details on the address space mapping as seen from the instance.
 
 
 
@@ -379,7 +379,7 @@ Yes. The HDK includes a simulation model for the AWS shell. See the [HDK common
 
 **Q: What resources within the FPGA does the AWS Shell consume?**
 
-The Shell consumes about 20% of the FPGA resources, and that includes the PCIe Gen3 X16, DMA engine, DRAM controller interface, ChipScope and other health monitoring and image loading logic. No modifications to the Shell or the partition pins between the Shell and the Custom Logic are possible by the FPGA developer.
+The Shell consumes about 20% of the FPGA resources, and that includes the PCIe Gen3 X16, DMA engine, DRAM controller interface, ChipScope (Virtual JTAG) and other health monitoring and image loading logic. No modifications to the Shell or the partition pins between the Shell and the Custom Logic are possible by the FPGA developer.
 
 
 

diff --git a/RELEASE_NOTES.md b/RELEASE_NOTES.md
@@ -26,12 +26,17 @@
          *     1 DDR controller implemented in the SH (always available)
          *     3 DDR controllers implemented in the CL (configurable number of implemented controllers allowed)
 
+# Release 1.2.1
+   *    Expanded [clock recipes](./hdk/docs/clock_recipes.csv) 
+   *    Virtual JTAG documentation updates
+   *    Included encryption of .sv files for CL examples
+
 # Release 1.2.1
    *    Updated CL example build scripts with Prohibit URAM sites 
    *    EDMA Performance improvments 
    *    Expanded EC2 Instance type support
    *    CL Examples @250Mhz (Clock recipe A1)
-   *    Option to exclude chipscope from building CL examples (DISABLE_CHIPSCOPE_DEBUG)
+   *    Option to exclude Chipscope (Virtual JTAG) from building CL examples (DISABLE_VJTAG_DEBUG)
 
 # Release 1.2.0
 

diff --git a/hdk/cl/examples/cl_dram_dma/build/scripts/.critical_warnings b/hdk/cl/examples/cl_dram_dma/build/scripts/.critical_warnings
@@ -1 +1 @@
-152
+152
diff --git a/hdk/cl/examples/cl_dram_dma/design/cl_dram_dma.sv b/hdk/cl/examples/cl_dram_dma/design/cl_dram_dma.sv
@@ -720,7 +720,7 @@ cl_sda_slv CL_SDA_SLV (
 //-----------------------------------------
 
 
-`ifndef DISABLE_CHIPSCOPE_DEBUG
+`ifndef DISABLE_VJTAG_DEBUG
 
 cl_ila CL_ILA (
 
@@ -751,7 +751,7 @@ cl_vio CL_VIO (
 );
 
 
-`endif //  `ifndef DISABLE_CHIPSCOPE_DEBUG
+`endif //  `ifndef DISABLE_VJTAG_DEBUG
 
 //----------------------------------------- 
 // Virtual JATG ILA Debug core example 

diff --git a/hdk/cl/examples/cl_dram_dma/design/cl_dram_dma_defines.vh b/hdk/cl/examples/cl_dram_dma/design/cl_dram_dma_defines.vh
@@ -27,8 +27,8 @@
 //uncomment below to make SH and CL async
 `define SH_CL_ASYNC
 
-// Uncomment to disable Chipscope
-//`define DISABLE_CHIPSCOPE_DEBUG
+// Uncomment to disable Virtual JTAG
+//`define DISABLE_VJTAG_DEBUG
 
 `endif
 
diff --git a/hdk/cl/examples/cl_dram_dma/verif/scripts/top.questa.f b/hdk/cl/examples/cl_dram_dma/verif/scripts/top.questa.f
@@ -49,7 +49,7 @@
 ${SH_LIB_DIR}/bram_2rw.sv
 ${SH_LIB_DIR}/flop_fifo.sv
 
-+define+DISABLE_CHIPSCOPE_DEBUG
++define+DISABLE_VJTAG_DEBUG
 ${CL_ROOT}/design/axil_slave.sv
 ${CL_ROOT}/design/cl_dram_dma_defines.vh
 ${CL_ROOT}/design/cl_tst_scrb.sv

diff --git a/hdk/cl/examples/cl_dram_dma/verif/scripts/top.vcs.f b/hdk/cl/examples/cl_dram_dma/verif/scripts/top.vcs.f
@@ -45,7 +45,7 @@
 ${SH_LIB_DIR}/../ip/axi_register_slice/sim/axi_register_slice.v
 ${SH_LIB_DIR}/../ip/axi_register_slice_light/sim/axi_register_slice_light.v
 
-+define+DISABLE_CHIPSCOPE_DEBUG
++define+DISABLE_VJTAG_DEBUG
 ${CL_ROOT}/design/axil_slave.sv
 ${CL_ROOT}/design/cl_dram_dma_defines.vh
 ${CL_ROOT}/design/cl_tst_scrb.sv

diff --git a/hdk/cl/examples/cl_dram_dma/verif/scripts/top.vivado.f b/hdk/cl/examples/cl_dram_dma/verif/scripts/top.vivado.f
@@ -47,7 +47,7 @@
 ${SH_LIB_DIR}/../ip/axi_register_slice/sim/axi_register_slice.v
 ${SH_LIB_DIR}/../ip/axi_register_slice_light/sim/axi_register_slice_light.v
 
---define DISABLE_CHIPSCOPE_DEBUG
+--define DISABLE_VJTAG_DEBUG
 ${CL_ROOT}/design/axil_slave.sv
 ${CL_ROOT}/design/cl_dram_dma_defines.vh
 ${CL_ROOT}/design/cl_tst_scrb.sv

diff --git a/hdk/cl/examples/cl_hello_world/design/cl_hello_world.sv b/hdk/cl/examples/cl_hello_world/design/cl_hello_world.sv
@@ -328,9 +328,9 @@ assign pre_cl_sh_status_vled[15:0] = vled_q[15:0] & sh_cl_status_vdip_q2[15:0];
   assign cl_sh_status1[31:0] = `CL_VERSION;
 
 //-----------------------------------------------
-// Debug bridge, used if need chipscope
+// Debug bridge, used if need Virtual JTAG
 //-----------------------------------------------
-`ifndef DISABLE_CHIPSCOPE_DEBUG
+`ifndef DISABLE_VJTAG_DEBUG
 
 // Flop for timing global clock counter
 logic[63:0] sh_cl_glcount0_q;
@@ -381,7 +381,7 @@ always_ff @(posedge clk_main_a0)
    );
 
 //-----------------------------------------------
-// VIO Example - Needs Chipscope
+// VIO Example - Needs Virtual JTAG
 //-----------------------------------------------
    // Counter running at 125MHz
 
@@ -465,7 +465,7 @@ always_ff @(posedge clk_main_a0)
                    .probe10 (vo_cnt_watermark_q)
                    );
 
-`endif //  `ifndef DISABLE_CHIPSCOPE_DEBUG
+`endif //  `ifndef DISABLE_VJTAG_DEBUG
 
 endmodule
 

diff --git a/hdk/cl/examples/cl_hello_world/design/cl_hello_world_defines.vh b/hdk/cl/examples/cl_hello_world/design/cl_hello_world_defines.vh
@@ -23,7 +23,7 @@
 // FPGA flop init capability).  This will help with routing resources.
 `define FPGA_LESS_RST
 
-// Uncomment to disable Chipscope
-//`define DISABLE_CHIPSCOPE_DEBUG
+// Uncomment to disable Virtual JTAG
+//`define DISABLE_VJTAG_DEBUG
 
 `endif
diff --git a/hdk/common/shell_v04151701/build/scripts/aws_build_dcp_from_cl.sh b/hdk/common/shell_v04151701/build/scripts/aws_build_dcp_from_cl.sh
@@ -18,7 +18,7 @@
 # Usage help
 function usage
 {
-    echo "usage: aws_build_dcp_from_cl.sh [ [-script <vivado_script>] | [-strategy BASIC | DEFAULT | EXPLORE | TIMING | CONGESTION] [-clock_recipe_a A0 | A1 | A2] [-clock_recipe_b B0 | B1] [-clock_recipe_c C0 | C1] [-foreground] [-notify] | [-h] | [-H] | [-help] |  ]"
+    echo "usage: aws_build_dcp_from_cl.sh [ [-script <vivado_script>] | [-strategy BASIC | DEFAULT | EXPLORE | TIMING | CONGESTION] [-clock_recipe_a A0 | A1 | A2] [-clock_recipe_b B0 | B1 | B2 | B3 | B4 | B5] [-clock_recipe_c C0 | C1 | C2 | C3] [-foreground] [-notify] | [-h] | [-H] | [-help] |  ]"
     echo " "
     echo "By default the build is run in the background using nohup so that the"
     echo "process will not be terminated if the terminal window is closed."
@@ -123,15 +123,15 @@ fi
 
 # Check that clock_recipe_b is valid
 shopt -s extglob
-if [[ $clock_recipe_b != @(B0|B1) ]]; then
-  err_msg "$clock_recipe_b isn't a valid Clock Group B recipe. Valid Clock Group B recipes are B0 and B1."
+if [[ $clock_recipe_b != @(B0|B1|B2|B3|B4|B5) ]]; then
+  err_msg "$clock_recipe_b isn't a valid Clock Group B recipe. Valid Clock Group B recipes are B0, B1, B2, B3, B4, and B5."
   exit 1
 fi
 
 # Check that clock_recipe_c is valid
 shopt -s extglob
-if [[ $clock_recipe_c != @(C0|C1) ]]; then
-  err_msg "$clock_recipe_c isn't a valid Clock Group C recipe. Valid Clock Group C recipes are C0 and C1."
+if [[ $clock_recipe_c != @(C0|C1|C2|C3) ]]; then
+  err_msg "$clock_recipe_c isn't a valid Clock Group C recipe. Valid Clock Group C recipes are C0, C1, C2, and C3."
   exit 1
 fi
 

diff --git a/hdk/common/shell_v04151701/build/scripts/aws_clock_properties.tcl b/hdk/common/shell_v04151701/build/scripts/aws_clock_properties.tcl
@@ -15,6 +15,8 @@
 
 # Set Clock Group properties based on specified recipe
 # Clock Group A
+set_property CLKFBOUT_MULT_F   6 [get_cells SH/kernel_clks_i/clkwiz_sys_clk/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
+set_property DIVCLK_DIVIDE     1 [get_cells SH/kernel_clks_i/clkwiz_sys_clk/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
 if {[string compare $clock_recipe_a "A1"] == 0} {
    set_property CLKOUT0_DIVIDE_F   6 [get_cells SH/kernel_clks_i/clkwiz_sys_clk/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
    set_property CLKOUT1_DIVIDE    12 [get_cells SH/kernel_clks_i/clkwiz_sys_clk/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
@@ -34,18 +36,56 @@ if {[string compare $clock_recipe_a "A1"] == 0} {
 
 # Clock Group B
 if {[string compare $clock_recipe_b "B1"] == 0} {
+   set_property CLKFBOUT_MULT_F   5 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
+   set_property DIVCLK_DIVIDE     1 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
    set_property CLKOUT0_DIVIDE_F 10 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
    set_property CLKOUT1_DIVIDE   20 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
+} elseif {[string compare $clock_recipe_b "B2"] == 0} {
+   set_property CLKFBOUT_MULT_F  18 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
+   set_property DIVCLK_DIVIDE     5 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
+   set_property CLKOUT0_DIVIDE_F  2 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
+   set_property CLKOUT1_DIVIDE    4 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
+} elseif {[string compare $clock_recipe_b "B3"] == 0} {
+   set_property CLKFBOUT_MULT_F   5 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
+   set_property DIVCLK_DIVIDE     1 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
+   set_property CLKOUT0_DIVIDE_F  5 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
+   set_property CLKOUT1_DIVIDE   20 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
+} elseif {[string compare $clock_recipe_b "B4"] == 0} {
+   set_property CLKFBOUT_MULT_F  24 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
+   set_property DIVCLK_DIVIDE     5 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
+   set_property CLKOUT0_DIVIDE_F  4 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
+   set_property CLKOUT1_DIVIDE   16 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
+} elseif {[string compare $clock_recipe_b "B5"] == 0} {
+   set_property CLKFBOUT_MULT_F  24 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
+   set_property DIVCLK_DIVIDE     5 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
+   set_property CLKOUT0_DIVIDE_F  3 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
+   set_property CLKOUT1_DIVIDE   12 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
 } else { #B0
+   set_property CLKFBOUT_MULT_F   5 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
+   set_property DIVCLK_DIVIDE     1 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
    set_property CLKOUT0_DIVIDE_F  5 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
    set_property CLKOUT1_DIVIDE   10 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
 }
 
 # Clock Group C
 if {[string compare $clock_recipe_c "C1"] == 0} {
+   set_property CLKFBOUT_MULT_F  24 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk1/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
+   set_property DIVCLK_DIVIDE     5 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk1/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
    set_property CLKOUT0_DIVIDE_F  8 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk1/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
    set_property CLKOUT1_DIVIDE    6 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk1/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
+} elseif {[string compare $clock_recipe_c "C2"] == 0} {
+   set_property CLKFBOUT_MULT_F  24 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk1/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
+   set_property DIVCLK_DIVIDE     5 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk1/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
+   set_property CLKOUT0_DIVIDE_F 16 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk1/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
+   set_property CLKOUT1_DIVIDE   12 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk1/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
+} elseif {[string compare $clock_recipe_c "C3"] == 0} {
+   set_property CLKFBOUT_MULT_F  16 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk1/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
+   set_property DIVCLK_DIVIDE     5 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk1/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
+   set_property CLKOUT0_DIVIDE_F  4 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk1/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
+   set_property CLKOUT1_DIVIDE    3 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk1/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
 } else { #C0
+   set_property CLKFBOUT_MULT_F  24 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk1/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
+   set_property DIVCLK_DIVIDE     5 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk1/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
    set_property CLKOUT0_DIVIDE_F  4 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk1/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
    set_property CLKOUT1_DIVIDE    3 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk1/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
 }

diff --git a/hdk/common/shell_v04151701/build/scripts/aws_gen_clk_constraints.tcl b/hdk/common/shell_v04151701/build/scripts/aws_gen_clk_constraints.tcl
@@ -65,6 +65,30 @@ switch $clock_recipe_b {
         set clk_extra_b1_period      16
         set clk_extra_b1_half_period  8
     }
+    "B2" {
+        set clk_extra_b0_period       2.222
+        set clk_extra_b0_half_period  1.111
+        set clk_extra_b1_period       4.444
+        set clk_extra_b1_half_period  2.222
+    }
+    "B3" {
+        set clk_extra_b0_period       4
+        set clk_extra_b0_half_period  2
+        set clk_extra_b1_period      16
+        set clk_extra_b1_half_period  8
+    }
+    "B4" {
+        set clk_extra_b0_period       3.333
+        set clk_extra_b0_half_period  1.667
+        set clk_extra_b1_period      13.333
+        set clk_extra_b1_half_period  6.667
+    }
+    "B5" {
+        set clk_extra_b0_period       2.5
+        set clk_extra_b0_half_period  1.25
+        set clk_extra_b1_period      10
+        set clk_extra_b1_half_period  5
+    }
     default {
         puts "$clock_recipe_b is NOT a valid clock_recipe_b."
     }
@@ -84,6 +108,18 @@ switch $clock_recipe_c {
         set clk_extra_c1_period       5
         set clk_extra_c1_half_period  2.5
     }
+    "C2" {
+        set clk_extra_c0_period      13.333
+        set clk_extra_c0_half_period  6.667
+        set clk_extra_c1_period      10
+        set clk_extra_c1_half_period  5
+    }
+    "C3" {
+        set clk_extra_c0_period       5
+        set clk_extra_c0_half_period  2.5
+        set clk_extra_c1_period       3.75
+        set clk_extra_c1_half_period  1.875
+    }
     default {
         puts "$clock_recipe_c is NOT a valid clock_recipe_c."
     }

diff --git a/hdk/common/shell_v04151701/new_cl_template/build/README.md b/hdk/common/shell_v04151701/new_cl_template/build/README.md
@@ -5,7 +5,7 @@
 1. [Overview of AFI Build process](#buildoverview)
 2. [Build procedure step by step](#stepbystep)
 3. [Build strategies and parallel builds](#strategies)
-4. [About Encrption during build process](#buildencryption)
+4. [About Encryption during build process](#buildencryption)
 5. [Advanced Notes](#buildadvanced_notes)
 6. [Build Frequently Asked Questions](#buildfaq)
 
@@ -61,7 +61,7 @@ The build script performs:
 
 <a name="strategies"></a>  
 #### Build Strategies   
-In order to help developers close timing goals and successfully build their designs efficiently, the build script provides the means to synthesize with different strategies. The different strategies alter the directives used by the synthesis tool. For example, some directives might specify additional optimizations to close timing, while others may specify less effort to minimize synthesis time for designs that can more easily close timing and area goals. Since every design is different, some strategies may provide better results than anothers. If a developer has trouble successfully building their design with one strategy it is encouraged that they try a different strategy, or run a few strategies in parallel using the FPGA Developer AMI. The strategies are described in more detail below.
+In order to help developers close timing goals and successfully build their designs efficiently, the build script provides the means to synthesize with different strategies. The different strategies alter the directives used by the synthesis tool. For example, some directives might specify additional optimizations to close timing, while others may specify less effort to minimize synthesis time for designs that can more easily close timing and area goals. Since every design is different, some strategies may provide better results than another build strategies. If a developer has trouble successfully building their design with one strategy it is encouraged that they try a different strategy, or run a few strategies in parallel using the FPGA Developer AMI. The strategies are described in more detail below.
 
 Build script usage:
 
@@ -96,7 +96,7 @@ Options:
 Strategy descriptions:
 
 * BASIC
-  * This is the basic flow in Vivado and contains the mandatory steps to be able to build a design. It is designed to provide a good balance betwwen runtime and Quality of Results (QOR).
+  * This is the basic flow in Vivado and contains the mandatory steps to be able to build a design. It is designed to provide a good balance between runtime and Quality of Results (QOR).
 
 * EXPLORE
   * This is a high-effort flow which is designed to give improved QOR results at the expense of runtime.