Additional v1.3.1 changes

wjblanke · Sep 5, 2017 · c3a0625 · c3a0625
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diff --git a/FAQs.md b/FAQs.md
@@ -28,7 +28,7 @@ AWS designed its FPGA instances to provide a developer experience with ease of u
 
 - AWS provides an [FPGA Developer AMI](https://aws.amazon.com/marketplace/pp/B06VVYBLZZ) that contains Xilinx Vivado development environment, with all the needed licenses. By using the FPGA developer AMI developers have a choice to a wide range of instance (different CPU and Memory configutation) allowing developers to optimize their development flow.
 
-- AWS provides cloud based debug tools: [Virtual JTAG](./hdk/docs/Virtual_JTAG_XVC.md) which is equivalent to debug using JTAG with on-premise development, and Virtual LED together with Virtual DIP Switch emulation the LED and DIP switches in typical development board.
+- AWS provides cloud based debug tools: [Virtual JTAG](./hdk/docs/Virtual_JTAG_XVC.md) which is equivalent to debug using JTAG with on-premises development, and Virtual LED together with Virtual DIP Switch emulation the LED and DIP switches in typical development board.
 
 - For developers who want to develop on-premises, Xilinx provides an [on-premises license](./hdk/docs/on_premise_licensing_help.md ) that matches all the needed components needed to be licensed for F1 development on premises. 
 
@@ -104,13 +104,22 @@ It is the compiled FPGA code that is loaded into an FPGA in AWS for performing t
 
 The developer can create multiple AFIs at no extra cost, up to a defined limited (typically 100 AFIs per region per AWS account). An AFI can be loaded into as many FPGAs as needed. 
 
+**Q: What regions are supported?**
+
+AWS FPGA generation and EC2 F1 instances are supported in us-east-1 (N. Virginia), us-west-2 (Oregon) and ue-west-1 (Ireland).
 
 **Q: What is the process for creating an AFI?**
 
 The AFI process starts by creating Custom Logic (CL) code that conforms to the [Shell Specification]((./hdk/docs/AWS_Shell_Interface_Specification.md). Then, the CL must be compiled using the HDK scripts which leverages Vivado tools to create a Design Checkpoint (DCP). That DCP is submitted to AWS for generating an AFI using the `aws ec2 create-fpga-image` API.
 
 Use the AWS CLI `describe-fpga-images` API to get information about the created AFIs using the AFI ID provided by `create-fpga-image`, or to list available AFIs for your account. See [describe-fpga-images](./hdk/docs/describe_fpga_images.md) document for details on how to use this API.
 
+**Q: Can I load an AFI on every region AWS FPGA is supported?**
+
+Yes, but you must first copy the AFI using the [copy-fpga-image](./hdk/docs/copy_fpga_image.md) API.  You should generate AFIs in one region and use copy to make them available in other regions.  Copy preserves the Global AFI ID used to load an AFI on a EC2 instance.
+
+Use [describe-fpga-images](./hdk/docs/describe_fpga_images.md) with the [--region command line option](http://docs.aws.amazon.com/cli/latest/userguide/cli-command-line.html) to list AFIs available in a specific region.  Use `FpgaImageGlobalId` attribute and `fpga-image-global-id` filter to match AFI copies accross regions.
+
 **Q: Can I bring my own bitstream for loading on an F1 FPGA?**
 
 No. There is no mechanism for loading a bitstream directly onto the FPGAs of an F1 instance. All Custom Logic is loaded onto the FPGA by calling `$ fpga-local-load-image` tool at [AWS FPGA SDK](https://github.com/aws/aws-fpga/sdk). 

diff --git a/README.md b/README.md
@@ -3,8 +3,8 @@
 # Table of Contents
 
 1. [AWS EC2 FPGA Hardware and Software Development Kits](#devkit)
-    - [FPGA Hardware Development Kit (HDK)](#fpgahdk)
-    - [Vivado IP Integrator (IPI) and GUI Workflow](#ipi)    
+    - [FPGA Hardware Development Kit Workflow(HDK)](#fpgahdk)
+    - [GUI Workflow with Vivado IP Integrator (IPI)](#ipi)    
     - [FPGA Software Development Kit (SDK)](#fpgasdk)
     - [FPGA Developer AMI available on AWS Marketplace](#devAmi)
     - [Developer Support](#devSupport)
@@ -15,12 +15,12 @@
 <a name="devkit"></a>
 # AWS EC2 FPGA Hardware and Software Development Kits 
 
-This release includes two portions: [HDK](./hdk) for developing Amazon FPGA Image (AFI),  and [SDK](./sdk) for using AFIs on FPGA-enabled EC2 instances [such as F1](https://aws.amazon.com/ec2/instance-types/f1/).
+The AWS EC2 FPGA Hardware and Software Development Kits include two portions: Development workflows for developing Amazon FPGA Image (AFI) with the [HDK](./hdk) or the GUI workflow, and [SDK](./sdk) for using AFIs on FPGA-enabled EC2 instances [such as F1](https://aws.amazon.com/ec2/instance-types/f1/).
 
 Execute `git clone https://github.com/aws/aws-fpga.git` to download this HDK+SDK release to your EC2 Instance or local server.
 For an SSH connection execute `git clone [email protected]:aws/aws-fpga.git`. [To get help with connecting to Github via SSH](https://help.github.com/articles/connecting-to-github-with-ssh/)
 
-The [Release Notes](./RELEASE_NOTES.md) document covers the list of supported features, programming environment, and known restrictions.
+The [Release Notes](./RELEASE_NOTES.md) document covers the list of supported features, programming environments, and known restrictions.
 
 **NOTE: The HDK and SDK are tested and supported for Linux operating systems, for the time being, other OSs haven't been tested by AWS**
 
@@ -38,15 +38,15 @@ The [HDK directory](./hdk) contains useful information and scripts for developer
 [FPGA PCIe Address Map](./hdk/docs/AWS_Fpga_Pcie_Memory_Map.md)
 
 <a name="ipi"></a>
-## Vivado IP Integrator (IPI) and GUI Workflow
+## GUI Workflow with Vivado IP Integrator (IPI)
 
-Developers have the option of working in a GUI mode using Vivado IP Integator (IPI).   With IPI you can create complex F1 customer designs on a graphical interface design canvas.   The HDK development kit provides AWS IP which will help you quickly develop your customer design and enable you to quickly drop in IP blocks.
+Developers have the option of working in a GUI mode using Vivado IPI.  With IPI you can create complex F1 custom designs on a graphical interface design canvas.  The HDK development kit provides AWS FPGA IP which will help you quickly develop your custom designs by enabling you to quickly drop in IP blocks into your design.
 
-The IP Integrator flow isolates the Customer Logic (CL) from the shell, allowing the developer to focus on differentiation within the F1 image.  Generating a logic diagram is simplified with designer automation that connects RTL, IP, and peripherals like DDR and PCIe in a correct by construction flow.  The “what you see is what you get” tool generates the equivalent code by instantiating the underlying IP and RTL and gives access via the Vivado project to the entire FPGA hardware design flow.  A video walk through of this flow for a simple diagram is available at https://www.xilinx.com/video/hardware/using-vivado-ip-integrator-and-amazon-f1.html.  This flow is a good starting point for developers who want to quickly add IP blocks with high performance access to multiple external memories.
+The IPI flow isolates the Custom Logic (CL) from the shell, allowing the developer to focus on differentiating logic and leave the heavy lifting, undeferentiated hardware interfaces development to the AWS FPGA Shell.  Generating a logic diagram is simplified with designer automation that connects RTL, IP, and peripherals like DDR and PCIe in a correct by construction flow.  The “what you see is what you get” tool generates the equivalent code by instantiating the underlying IP and RTL with access via the Vivado project to the entire FPGA hardware design flow.  A video walk through of this flow for a simple diagram is available at https://www.xilinx.com/video/hardware/using-vivado-ip-integrator-and-amazon-f1.html.  This flow example is a good starting point for developers who want to quickly add IP blocks with high performance access to multiple external memories.
 
-The IP Integrator RTL flow enables the developer a single graphical environment to add sources and IP, simulate, synthesize the RTL, and then stitch together the Customer Logic (CL) with the shell’s design check point (DCP).  Developers can easily instantiate logic analyzers or other debug logic, investigate timing and resource reports, and quickly link from implementation messages to the design view and source code when applicable.  This flow is a good starting point for experts in RTL design or developers who have a minimal amount of interconnection between RTL modules.
+The IPI RTL flow enables the developer a single graphical environment to add sources and IP, simulate, synthesize the RTL, and then stitch together the Custom Logic (CL) with the Shell’s design checkpoint (DCP).  For design debug, developers can easily instantiate logic analyzers or other debug logic, investigate timing and resource reports, and quickly link from implementation messages to the design view and source code when applicable.  This flow is a good starting point for experts in RTL design or designs who have a minimal amount of interconnection between RTL modules.
 
-The below documentation covers the setup, tutorials of the IP Integrator flows and FAQ.  Developers are recommended to read all documents before starting any design.  
+The below documentation covers the setup, tutorials of the IPI flows and IPI FAQ.  Developers are advised to read all documents before starting thier first AWS FPGA design with IPI.  
 
 [IPI Setup](./hdk/docs/IPI_GUI_Vivado_Setup.md)
 

diff --git a/RELEASE_NOTES.md b/RELEASE_NOTES.md
@@ -103,7 +103,7 @@ See example for more details [CL_HELLO_WORLD_VHDL](./hdk/cl/examples/cl_hello_wo
 * First installation of AWS FPGA SDK requires having gcc installed in the instance server. If that's not available, try `sudo yum update && sudo yum group install "Development Tools"`
 * The HDK build step requires having Xilinx's Vivado tool and Vivado License Management running.  Tools and licenses are provided with AWS FPGA Developer AMI at no additional cost
 * This release is tested and validated with Xilinx 2017.1 SDX (Vivado)
-* Developers that choose to not use the developer AMI in AWS EC2, need to have Xilinx license 'EF-VIVADO-SDX-VU9P-OP' installed on premise.  For more help, please refer to [On-premise licensing help](./hdk/docs/on_premise_licensing_help.md)
+* Developers that choose to not use the developer AMI in AWS EC2, need to have Xilinx license 'EF-VIVADO-SDX-VU9P-OP' installed on premises.  For more help, please refer to [On-premise licensing help](./hdk/docs/on_premise_licensing_help.md)
 * Vivado XSIM RTL simulator supported by the HDK
 * MentorGraphic's Questa RTL simulator supported by the HDK (but requires a purchase of separate license from MentorGraphics)
 * Synopsys' VCS RTL simulator supported by the HDK (but requires a purchase of separate license from Synopsys)

diff --git a/hdk/README.md b/hdk/README.md
@@ -21,7 +21,7 @@ Useful resources:
 <a name="overview"></a>
 ## Overview 
 
-The AWS FPGA HDK includes all the design files and scripts required to build an Amazon FPGA Image (AFI) from RTL (Verilog/VHDL) custom design. Developers can download the HDK and use it in their preferred design environment: In the cloud or on-premise. AWS offers the [FPGA Developer AMI on AWS Marketplace](https://aws.amazon.com/marketplace/pp/B06VVYBLZZ) with pre-installed tools to develop, simulate, and build an AFI.
+The AWS FPGA HDK includes all the design files and scripts required to build an Amazon FPGA Image (AFI) from RTL (Verilog/VHDL) custom design. Developers can download the HDK and use it in their preferred design environment: In the cloud or on-premises. AWS offers the [FPGA Developer AMI on AWS Marketplace](https://aws.amazon.com/marketplace/pp/B06VVYBLZZ) with pre-installed tools to develop, simulate, and build an AFI.
 
 **NOTE:** The HDK is developed and tested in a **Linux** environment only
 
@@ -40,11 +40,11 @@ The HDK also includes test benches for each provided example, and instructions o
 <a name="gettingstarted"></a>
 ## Getting Started 
 
-### Have an instance or server with Xilinx Vivado tools and License <a name="vivado"></a>
+### Have an EC2 instance or on-premises server installed with Xilinx Vivado tools and License <a name="vivado"></a>
 
 To get started, the developer needs to have a development environment with Xilinx Vivado tools installed. An easy way to get this by using the [AWS FPGA Developer AMI](https://aws.amazon.com/marketplace/pp/B06VVYBLZZ) which comes with all the tools and required licenses pre-installed.
 
-For developers who like to work on-premise or different AMI in the cloud, follow the [required license for on-premise document](./docs/on_premise_licensing_help.md).
+For developers who like to work on-premises or different AMI in the cloud, follow the [required license for on-premises document](./docs/on_premise_licensing_help.md).
 
 Please refer to the [release notes](../RELEASE_NOTES.md) or the [supported Vivado version](./supported_vivado_versions.txt) for the exact version of Vivado tools, and the required license components.
 
@@ -86,15 +86,15 @@ You can follow the [build scripts readme](./common/shell_v04151701/new_cl_templa
 This [checklist](./cl/CHECKLIST_BEFORE_BUILDING_CL.md) should be consulted before you start the build process.
 
 <a name="ipi"></a>
-## Vivado IP Integrator (IPI) and GUI Workflow
+## GUI Workflow with Vivado IP Integrator (IPI)
 
-Developers have the option of working in a GUI mode using Vivado IP Integator (IPI).   With IPI you can create complex F1 customer designs on a graphical interface design canvas.   The HDK development kit provides AWS IP which will help you quickly develop your customer design and enable you to quickly drop in IP blocks.
+Developers have the option of working in a GUI mode using Vivado IPI. With IPI you can create complex F1 custom designs on a graphical interface design canvas. The HDK development kit provides AWS FPGA IP which will help you quickly develop your custom designs by enabling you to quickly drop in IP blocks into your design.
 
-The IP Integrator flow isolates the Customer Logic (CL) from the shell, allowing the developer to focus on differentiation within the F1 image.  Generating a logic diagram is simplified with designer automation that connects RTL, IP, and peripherals like DDR and PCIe in a correct by construction flow.  The “what you see is what you get” tool generates the equivalent code by instantiating the underlying IP and RTL and gives access via the Vivado project to the entire FPGA hardware design flow.  A video walk through of this flow for a simple diagram is available at https://www.xilinx.com/video/hardware/using-vivado-ip-integrator-and-amazon-f1.html.  This flow is a good starting point for developers who want to quickly add IP blocks with high performance access to multiple external memories.
-
-The IP Integrator RTL flow enables the developer a single graphical environment to add sources and IP, simulate, synthesize the RTL, and then stitch together the Customer Logic (CL) with the shell’s design check point (DCP).  Developers can easily instantiate logic analyzers or other debug logic, investigate timing and resource reports, and quickly link from implementation messages to the design view and source code when applicable.  This flow is a good starting point for experts in RTL design or developers who have a minimal amount of interconnection between RTL modules.
+The IPI flow isolates the Custom Logic (CL) from the shell, allowing the developer to focus on differentiating logic and leave the heavy lifting, undeferentiated hardware interfaces development to the AWS FPGA Shell. Generating a logic diagram is simplified with designer automation that connects RTL, IP, and peripherals like DDR and PCIe in a correct by construction flow. The “what you see is what you get” tool generates the equivalent code by instantiating the underlying IP and RTL with access via the Vivado project to the entire FPGA hardware design flow. A video walk through of this flow for a simple diagram is available at https://www.xilinx.com/video/hardware/using-vivado-ip-integrator-and-amazon-f1.html. This flow example is a good starting point for developers who want to quickly add IP blocks with high performance access to multiple external memories.
 
-The below documentation covers the setup, tutorials of the IP Integrator flows and FAQ.  Developers are recommended to read all documents before starting any design.  
+The IPI RTL flow enables the developer a single graphical environment to add sources and IP, simulate, synthesize the RTL, and then stitch together the Custom Logic (CL) with the Shell’s design checkpoint (DCP). For design debug, developers can easily instantiate logic analyzers or other debug logic, investigate timing and resource reports, and quickly link from implementation messages to the design view and source code when applicable. This flow is a good starting point for experts in RTL design or designs who have a minimal amount of interconnection between RTL modules.
+
+The below documentation covers the setup, tutorials of the IPI flows and IPI FAQ. Developers are advised to read all documents before starting thier first AWS FPGA design with IPI.
 
 [IPI Setup](./docs/IPI_GUI_Vivado_Setup.md)