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efabless / openlane2

Star

The next generation of OpenLane, rewritten from scratch with a modular architecture

flow asic eda verilog vlsi pnr silicon lvs flows sta gdsii drc pdk openroad openlane sky130 gf180mcu rtl-to-gds

Updated Nov 25, 2024
Python

US-CBP / GTAS

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Global Travel Assessment System | A passenger data screening and analysis system for enhancing global security

Updated Dec 27, 2023
Java

ghdl / docker

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Scripts to build and use docker images including GHDL

dockerfiles hardware ci simulation vhdl actions verilog synthesis icestorm gtkwave ghdl testbench vunit yosys openocd pnr nextpnr prjtrellis

Updated Nov 20, 2024
Shell

basemhesham / Design-and-ASIC-Implementation-of-UART

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This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been implemented by using Verilog description language which has been synthesized using Design Compiler and Back End design using Synopsys IC Compiler II

asic dft verilog synthesis uart fm pnr

Updated Apr 29, 2024
Verilog

abdelazeem201 / ICC2_scripts

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This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of ORCA which was taped-out by NTI.

tcl soc pnr tcl-extension

Updated Feb 11, 2024
Tcl

abdelazeem201 / ASIC-Implementation-UART

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This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between computer and peripherals. UART mainly contains Transmitter, Receiver and Baud Rate Generator. Baud Rate Generator generates the clock for the UART. We can achieve the desired Baud Rate by using divide factor from sys…

asic fpga vhdl eda rtl verilog synthesis uart soc pnr

Updated Mar 30, 2022
Verilog

porglezomp / minecraft-eda

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Electronic design automation for Minecraft

minecraft eda logic-synthesis pnr place-and-route

Updated May 3, 2019
Python

crackCodeLogn / PNR_Enquiry_IndianRailways_v2.0

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This project caters to the extraction of the status of PNR number (Passenger Name Record) of Indian Railways. PNR number is unique to each and every ticket bought in the railways. With the help of it, we can get the exact details of the ticket in hand

java ticket slf4j lombok gson guava mockito assertj java-8 java-swing pnr indian-railways apache-commons slf4j-api openfeign

Updated Dec 9, 2021
Java

Transavia / ShoppingCartExample

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Shopping Cart Example

shopping-cart airline flights pnr flights-api airlines-booking

Updated Apr 23, 2018
JavaScript

kholoud0 / ASIC-implementation-of-CV32E40P-RISC-V-core-

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This repository contains my BSc graduation project at the Faculty of Engineering, Ain Shams University. The project focuses on implementing the RISC-V core, specifically the CV32E40 ,with a focus on achieving high performance and maximizing frequency through synthesis, place and route (PNR).

asic synthesis implementation synopsys pnr synopsys-dc synopsys-iccii

Updated May 12, 2024
SystemVerilog

abdelazeem201 / RV32E201X

Star

RV32E201X is a 5-stage pipelined 32-bit RISC-V processor core.

fpga icc rtl verilog synthesis hdl soc risc-v pnr rv32e201x risc-v32 designcomp

Updated May 1, 2023
Verilog

AkshayXPatil / Physical-Layout-Design

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Complete design of USART interface with baud rate selection

scripting rtl verilog uart vlsi-physical-design gds2 pnr gdsii

Updated Aug 24, 2022
Verilog

Li-Yueting / aloe-sky130

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eda pnr analog-design

Updated Nov 15, 2024
Verilog

vipulwairagade / get-pnr-status

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Get Coach, Birth Number and Status from your PNR number

status railway india coach pnr indian-railways birth pnrstatus

Updated Sep 4, 2018
Python

crackCodeLogn / PNR_Enquiry_IndianRailways

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This project caters to the extraction of the status of PNR number (Passenger Name Record) of Indian Railways. PNR number is unique to each and every ticket bought in the railways. With the help of it, we can get the exact details of the ticket in hand

java java-swing java-network pnr indian-railways

Updated Jun 19, 2019
Java

mohamedtareq24 / ASICs_Design_Diploma

Star

RTL to GDSII flow of a low Power configurable multi clock digital system

project rtl verilog-hdl pnr asics

Updated Mar 3, 2024
Verilog

mohamedtareq24 / ASIC_implementation_of_PULPino_SoC

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My Graduation Project for BSc of Engineering Ain Shams Uni which is ASIC implementation of PULPino SoC based on the cv32e40p (RISCY) core sponserd by ICpedia using Synopsys tools

asic risc-v pnr synopsys-dc synopsys-iccii