Opensource DDR3 Controller

An FPGA-based MII to RMII & SMII converter to connect 100M ethernet PHY chip such as LAN8720 or KSZ8041TLI-S. 基于FPGA的MII转RMII和MII转SMII，用来连接LAN8720、KSZ8041TLI-S等百兆以太网PHY芯片。

An HDL design for sending data over Ethernet

Open Sigfox Stack Reference Implementation - Physical Layer for SDR

Everything you need to know on how to connect the LAN8720 PHY to the ESP32.

Go package for parsing Source Engine StudioModel formats (.mdl, .vtx, .vvd, .phy)

Let's see how fast and accurate we could detect 5G NR slot boundary

Plugins to Phy1 - additional features to Phy

External PHY RTL8201F with HR871181A

Python module for 5G NR sync signals and decoding.

External PHY RTL8201F with switch RTL8305NB and 2xHR871181A

Plugins for the manual spike sorting program phy

Analysis of physical layer security of MIMO system using Machine Learning algorithms vs theoretical best

an 100% python navigator

Neural Signal Analysis

🧶 Deriving the Feigenbaum constant from a DDP bifurcation diagram

BRAVE is a collaborative research project started in January 2018, that aims at creating new physical-layer (PHY) techniques devoted to beyond-5G wireless communications. The partners (Siradel, Central-Supélec, CEA-Leti and ANFR) are designing new high-data-rate and energy-efficient waveforms that operate in frequencies above 90 GHz. Application…

LibreLoRa: GNURadio Based LoRa PHY receiver and transmitter implementations. This is just a mirror, main repo at: https://gitlab.com/jpsimas/librelora

WiSCoP - Wireless Sensor Communication Prototyping Platform