🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).

🔑 Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.

📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.

🐛 JTAG debug transport module (DTM) - compatible to the RISC-V debug specification.

🌉 A transparent Wishbone-to-SPI bridge supporting Execute-In-Place (XIP).

Delivrables and code base from a CentraleSupéléc project

This repo contains the work developed in the SIEAV Master practices 🎓✏️📚

Simulating the NEORV32 RISC-V Processor using the VUnit testing framework.