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fpga-soc

Here are 14 public repositories matching this topic...

trivialmips / nontrivial-mips

NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.

cpu fpga mips xilinx fpga-soc-linux systemverilog fpga-soc

Updated Jul 7, 2020
SystemVerilog

dpretet / axi-crossbar

An AXI4 crossbar implementation in SystemVerilog

arm asic fpga processor riscv verilog soc fpga-soc interconnect amba crossbar riscv32 axi4 axi4-lite riscv64 monodraw axi4-protocol asic-design axi4-full

Updated Nov 21, 2024
SystemVerilog

trivialmips / TrivialMIPS

MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support

cpu fpga mips xilinx systemverilog fpga-soc

Updated Apr 29, 2019
SystemVerilog

dpretet / friscv

RISCV CPU implementation in SystemVerilog

asic fpga assembler riscv verilog systemverilog fpga-soc risc-v rv32i crossbar axi4 axi4-protocol asic-design riscv-cpu

Updated Oct 8, 2024
SystemVerilog

habibaouinti / NPU_X_Interface

Implementation of an NPU that can be integrated into a RISC- V core through X-Interface.

fpga fpga-soc risc-v npu vcu118

Updated Sep 17, 2024
SystemVerilog

ngrabbs / arm_projects

ARM single cycle processor on nandland.com go-board

arm embedded fpga assembly assembler systemverilog hdl fpga-soc system-architecture ice40 system-design fpga-programming

Updated Oct 23, 2023
SystemVerilog

monistode / ISA_stack

An implementation of the RISC stack ISA spec from ISA-docs

cpu systemverilog fpga-soc

Updated Dec 28, 2023
SystemVerilog

geitanksha / rubiks-cube-simulator

Designed and implemented a 3x3 Rubik's Cube Simulator on an FPGA and associated NIOS-II Microcontroller as a System-on-Chip. Skills Employed: SystemVerilog, FPGA development, NIOS-II, SoC, USB Protocol.

fpga systemverilog fpga-soc

Updated Mar 24, 2023
SystemVerilog

sgq995 / rc4-de0-nano-soc

It's a cryptoprocessor that implements de RC4 algorithm

fpga rc4 verilog de0-nano-soc fpga-soc

Updated Jun 3, 2017
SystemVerilog

0xD503 / SPI-Interface

SPI Interface RTL Description

fpga ip spi soc fpga-soc serial-communication serial-communications

Updated May 21, 2019
SystemVerilog

kelhuynh / MECHTRON-3TB4-Labs

3TB4-Embedded Systems II

fpga verilog fpga-soc quartus

Updated Jun 9, 2022
SystemVerilog

messes2 / ECE-385-Final-project

I made a motion controlled digital synthesizer known as a puppeteer theremin that uses AI to get motion control data from a server hosted on a phone onto an FPGA.

python ai fpga embedded-systems tesseract-ocr systemverilog fpga-soc audio-processing pytesseract ece385

Updated Dec 15, 2022
SystemVerilog

0xD503 / I2C-Interface

I2C Interface RTL description

i2c fpga-soc serial-communication serial-interface

Updated May 30, 2019
SystemVerilog

0xD503 / Digital-music-project

Laboratory work project

embedded fpga audio-player audio-codec hobby-project fpga-soc systemverilog-hdl laboratory-exercises

Updated May 23, 2019
SystemVerilog

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