An OpenCL-based FPGA Accelerator for Convolutional Neural Networks

QKeras: a quantization deep learning library for Tensorflow Keras

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

Research and Materials on Hardware implementation of Transformer Model

Open Source Specialized Computing Stack for Accelerating Deep Neural Networks.

Convolutional accelerator kernel, target ASIC & FPGA

Small-scale Tensor Processing Unit built on an FPGA

The codes and artifacts associated with our MICRO'22 paper titled: "Adaptable Butterfly Accelerator for Attention-based NNs via Hardware and Algorithm Co-design"

Squeezenet V1.1 on Cyclone V SoC-FPGA at 450ms/image, 20x faster than ARM A9 processor alone. A project for 2017 Innovate FPGA design contest.

BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/

OpenCL HLS based CNN Accelerator on Intel DE10 Nano FPGA.

OpenGL 1.x implementation for FPGAs

OPAE porting to Xilinx FPGA devices.

This project implements a convolution kernel based on vivado HLS on zcu104

Lenet for MNIST handwritten digit recognition using Vivado hls tool

Basic OpenGL 1.x implementation for small FPGAs (like iCE40UP5K)

Synthesizeable VHDL and Verilog implementation of 64-point FFT/IFFT Processor with Q4.12 Fixed Point Data Format.

FPGA-based hardware acceleration for dropout-based Bayesian Neural Networks.

A crypto accelerator written for HLS to an FPGA that actually makes it slower than running it on your computer

Hardware-accelerated sorting algorithm